Hi Mark,
On Friday 20 September 2013 02:28 PM, Mark Rutland wrote:
> Hi,
>
> I have a few comments, mostly on the DT binding and parsing.
>
Thanks for the review. The idea of seeing the crossbar as a new IRQCHIP
itself did not go and the latest direction on this was to handle it inside the
GIC.
Hi,
I have a few comments, mostly on the DT binding and parsing.
> diff --git a/Documentation/devicetree/bindings/arm/omap/irq-crossbar.txt
> b/Documentation/devicetree/bindings/arm/omap/irq-crossbar.txt
> new file mode 100644
> index 000..5d465cf
> --- /dev/null
> +++ b/Documentation/device
On Wed, 18 Sep 2013, Santosh Shilimkar wrote:
> On Friday 13 September 2013 10:55 AM, Santosh Shilimkar wrote:
> > On Friday 13 September 2013 10:24 AM, Thomas Gleixner wrote:
>
> [...]
>
> >> Before you dig into MSI, lets talk about irq domains first.
> >>
> >> GIC implements a legacy irq domain
On Wed, 18 Sep 2013, Sricharan R wrote:
> On Wednesday 18 September 2013 07:22 PM, Sricharan R wrote:
> > Hi Thomas,
> >
> > On Tuesday 17 September 2013 05:56 PM, Linus Walleij wrote:
> >> On Fri, Sep 13, 2013 at 4:24 PM, Thomas Gleixner
> >> wrote:
> >>
> >>> So why can't you make use of irq do
On Wednesday 18 September 2013 07:22 PM, Sricharan R wrote:
> Hi Thomas,
>
> On Tuesday 17 September 2013 05:56 PM, Linus Walleij wrote:
>> On Fri, Sep 13, 2013 at 4:24 PM, Thomas Gleixner wrote:
>>
>>> So why can't you make use of irq domains and have the whole routing
>>> business implemented sa
Thomas,
On Friday 13 September 2013 10:55 AM, Santosh Shilimkar wrote:
> On Friday 13 September 2013 10:24 AM, Thomas Gleixner wrote:
[...]
>> Before you dig into MSI, lets talk about irq domains first.
>>
>> GIC implements a legacy irq domain, i.e. a linear domain of all
>> possible GIC interru
Hi Thomas,
On Tuesday 17 September 2013 05:56 PM, Linus Walleij wrote:
> On Fri, Sep 13, 2013 at 4:24 PM, Thomas Gleixner wrote:
>
>> So why can't you make use of irq domains and have the whole routing
>> business implemented sanely?
>>
>> What's needed is in gic_init_bases():
>> irq
>>if
On Fri, Sep 13, 2013 at 4:24 PM, Thomas Gleixner wrote:
> So why can't you make use of irq domains and have the whole routing
> business implemented sanely?
>
> What's needed is in gic_init_bases():
>
>if (of_property_read(node, "routable_irqs", &nr_routable_irqs) {
> irq_domain
On Friday 13 September 2013 10:24 AM, Thomas Gleixner wrote:
> On Thu, 12 Sep 2013, Santosh Shilimkar wrote:
>> On Thursday 12 September 2013 08:26 PM, Thomas Gleixner wrote:
>>> Let me summarize:
>>>
>>>- GIC supports up to 160 interrupts
>>>
>>>- CROSSBAR supports up to 250 interrupts
>>
On Thu, 12 Sep 2013, Santosh Shilimkar wrote:
> On Thursday 12 September 2013 08:26 PM, Thomas Gleixner wrote:
> > Let me summarize:
> >
> >- GIC supports up to 160 interrupts
> >
> >- CROSSBAR supports up to 250 interrupts
> >
> >- CROSSBAR routes up to 160 out of 250 interrupts to
On Friday 13 September 2013 07:12 AM, Santosh Shilimkar wrote:
> On Thursday 12 September 2013 08:26 PM, Thomas Gleixner wrote:
>> On Thu, 12 Sep 2013, Santosh Shilimkar wrote:
>>> On Thursday 12 September 2013 06:22 PM, Thomas Gleixner wrote:
Now the real question is, how that expansion mecha
On Thursday 12 September 2013 08:26 PM, Thomas Gleixner wrote:
> On Thu, 12 Sep 2013, Santosh Shilimkar wrote:
>> On Thursday 12 September 2013 06:22 PM, Thomas Gleixner wrote:
>>> Now the real question is, how that expansion mechanism is supposed to
>>> work. There are two possible scenarios:
>>>
On Thu, 12 Sep 2013, Santosh Shilimkar wrote:
> On Thursday 12 September 2013 06:22 PM, Thomas Gleixner wrote:
> > Now the real question is, how that expansion mechanism is supposed to
> > work. There are two possible scenarios:
> >
> > 1) Expand the number of handled interrupts beyond the GIC cap
On Thursday 12 September 2013 06:22 PM, Thomas Gleixner wrote:
> On Thu, 12 Sep 2013, Santosh Shilimkar wrote:
>> Specifically for the IRQ case addressed here, the cross-bar IP
>> sits between the interrupt controller and peripheral interrupts.
>>
>> CPU <-- GIC <- CROSSBAR <- PERIPHERAL I
On Thu, 12 Sep 2013, Santosh Shilimkar wrote:
> Specifically for the IRQ case addressed here, the cross-bar IP
> sits between the interrupt controller and peripheral interrupts.
>
> CPU <-- GIC <- CROSSBAR <- PERIPHERAL IRQs
>
> Just to expand it better, cross-bar input IRQ lines are mor
On Thu, 12 Sep 2013, Thomas Gleixner wrote:
> On Thu, 12 Sep 2013, Felipe Balbi wrote:
>
> > On Thu, Sep 12, 2013 at 09:09:08PM +0530, Sricharan R wrote:
> > > +unsigned int crossbar_request_irq(struct irq_data *d)
> > > +{
> > > + int cb_no = d->hwirq;
> > > + int virq = allocate_free_irq(cb_no)
On Thu, 12 Sep 2013, Felipe Balbi wrote:
> On Thu, Sep 12, 2013 at 09:09:08PM +0530, Sricharan R wrote:
> > +unsigned int crossbar_request_irq(struct irq_data *d)
> > +{
> > + int cb_no = d->hwirq;
> > + int virq = allocate_free_irq(cb_no);
> > + void *irq = &cb->crossbar_map[cb_no].hwirq;
>
Thomas,
On Thursday 12 September 2013 04:18 PM, Thomas Gleixner wrote:
> On Thu, 12 Sep 2013, Sricharan R wrote:
>> Signed-off-by: Sricharan R
>> ---
>> There is lockdep warning during the boot. This is because we try to
>> do one request_irq with in another and that results in kmalloc being
>> c
On Thu, Sep 12, 2013 at 09:09:08PM +0530, Sricharan R wrote:
> +unsigned int crossbar_request_irq(struct irq_data *d)
> +{
> + int cb_no = d->hwirq;
> + int virq = allocate_free_irq(cb_no);
> + void *irq = &cb->crossbar_map[cb_no].hwirq;
> + int err;
> +
> + err = request_thread
On Thu, 12 Sep 2013, Sricharan R wrote:
> Signed-off-by: Sricharan R
> ---
> There is lockdep warning during the boot. This is because we try to
> do one request_irq with in another and that results in kmalloc being
> called from an atomic context, which generates the warning.
> Any suggestions to
Some socs have a large number of interrupts requests to service
the needs of its many peripherals and subsystems. All of the
interrupt lines from the subsystems are not needed at the same
time, so they have to be muxed to the irq-controller appropriately.
In such places a interrupt controllers are
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