> I did some investigation and now I have some details.
> The term 'PHY' described in Ether Group Spec should be the PCS + PMA, a figure
> below for one configuration:
>
> ++ +-+
> | Host Side Ether Group | | XL710 |
> |
Hi Andrew:
On Mon, Oct 26, 2020 at 08:14:00PM +0100, Andrew Lunn wrote:
> > > > > Do you really mean PHY? I actually expect it is PCS?
> > > >
> > > > For this implementation, yes.
> > >
> > > Yes, you have a PHY? Or Yes, it is PCS?
> >
> > Sorry, I mean I have a PHY.
> >
> > >
> > > To me,
On Mon, Oct 26, 2020 at 08:14:00PM +0100, Andrew Lunn wrote:
> > > > > Do you really mean PHY? I actually expect it is PCS?
> > > >
> > > > For this implementation, yes.
> > >
> > > Yes, you have a PHY? Or Yes, it is PCS?
> >
> > Sorry, I mean I have a PHY.
> >
> > >
> > > To me, the phylib
On Mon, Oct 26, 2020 at 11:35:52AM -0700, Jakub Kicinski wrote:
> On Tue, 27 Oct 2020 01:38:04 +0800 Xu Yilun wrote:
> > > > The line/host side Ether Group is not the terminal of the network data
> > > > stream.
> > > > Eth1 will not paticipate in the network data exchange to host.
> > > >
> > >
> > > > Do you really mean PHY? I actually expect it is PCS?
> > >
> > > For this implementation, yes.
> >
> > Yes, you have a PHY? Or Yes, it is PCS?
>
> Sorry, I mean I have a PHY.
>
> >
> > To me, the phylib maintainer, having a PHY means you have a base-T
> > interface, 25Gbase-T,
On Tue, 27 Oct 2020 01:38:04 +0800 Xu Yilun wrote:
> > > The line/host side Ether Group is not the terminal of the network data
> > > stream.
> > > Eth1 will not paticipate in the network data exchange to host.
> > >
> > > The main purposes for eth1 are:
> > > 1. For users to monitor the network
On Mon, Oct 26, 2020 at 02:00:01PM +0100, Andrew Lunn wrote:
> > > > +The Intel(R) PAC N3000 is a FPGA based SmartNIC platform for
> > > > multi-workload
> > > > +networking application acceleration. A simple diagram below to for the
> > > > board:
> > > > +
> > > > +
> > > +The Intel(R) PAC N3000 is a FPGA based SmartNIC platform for
> > > multi-workload
> > > +networking application acceleration. A simple diagram below to for the
> > > board:
> > > +
> > > + ++
> > > + |
Hi Andrew
Thanks for your fast response, see comments inline.
On Fri, Oct 23, 2020 at 05:37:31PM +0200, Andrew Lunn wrote:
> Hi Xu
>
> Before i look at the other patches, i want to understand the
> architecture properly.
I have a doc to describe the architecture:
On 10/23/20 1:45 AM, Xu Yilun wrote:
> This patch adds the document for DFL Ether Group driver.
>
> Signed-off-by: Xu Yilun
> ---
> .../networking/device_drivers/ethernet/index.rst | 1 +
> .../ethernet/intel/dfl-eth-group.rst | 102
> +
> 2 files
Hi Xu
Before i look at the other patches, i want to understand the
architecture properly.
> +===
> +DFL device driver for Ether Group private feature on Intel(R) PAC N3000
>
This patch adds the document for DFL Ether Group driver.
Signed-off-by: Xu Yilun
---
.../networking/device_drivers/ethernet/index.rst | 1 +
.../ethernet/intel/dfl-eth-group.rst | 102 +
2 files changed, 103 insertions(+)
create mode 100644
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