Hi Matti,
On Mon, Apr 12, 2021 at 11:08:49AM +, Vaittinen, Matti wrote:
> Hi,
>
> On Mon, 2021-04-12 at 09:05 +0300, Matti Vaittinen wrote:
> > Hi All,
> >
> > On Wed, 2021-03-10 at 16:39 -0800, Guru Das Srinagesh wrote:
> > > Qualcomm's MFD chips have a top level interrupt status register a
Hi,
On Mon, 2021-04-12 at 09:05 +0300, Matti Vaittinen wrote:
> Hi All,
>
> On Wed, 2021-03-10 at 16:39 -0800, Guru Das Srinagesh wrote:
> > Qualcomm's MFD chips have a top level interrupt status register and
> > sub-irqs (peripherals). When a bit in the main status register
> > goes
> > high, i
Hi All,
On Wed, 2021-03-10 at 16:39 -0800, Guru Das Srinagesh wrote:
> Qualcomm's MFD chips have a top level interrupt status register and
> sub-irqs (peripherals). When a bit in the main status register goes
> high, it means that the peripheral corresponding to that bit has an
> unserviced inter
Qualcomm's MFD chips have a top level interrupt status register and
sub-irqs (peripherals). When a bit in the main status register goes
high, it means that the peripheral corresponding to that bit has an
unserviced interrupt. If the bit is not set, this means that the
corresponding peripheral does
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