>> +{ "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ)
>> },
>> +{ "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SPI_NOR_QUAD_READ)
>> },
>> +{ "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ)
>> },
>> +{ "n25q128a13", INFO(0x20ba18,
On Fri, Dec 05, 2014 at 07:09:59AM +, Bean Huo 霍斌斌 (beanhuo) wrote:
> This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes.
>
> For Micron SPI NOR flash,enabling or disabling quad I/O protocol can be done
> By two methods, which are to use EVCR(Enhanced Volatile
On Fri, Dec 05, 2014 at 07:09:59AM +, Bean Huo 霍斌斌 (beanhuo) wrote:
This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes.
For Micron SPI NOR flash,enabling or disabling quad I/O protocol can be done
By two methods, which are to use EVCR(Enhanced Volatile
+{ n25q032, INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ)
},
+{ n25q064, INFO(0x20ba17, 0, 64 * 1024, 128, SPI_NOR_QUAD_READ)
},
+{ n25q128a11, INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ)
},
+{ n25q128a13, INFO(0x20ba18, 0, 64 * 1024, 256,
>> + { "n25q256a",INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K |
>> SPI_NOR_QUAD_READ) },
>> + { "n25q512a",INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K |
>> USE_FSR | SPI_NOR_QUAD_READ) },
>> + { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K |
>> USE_FSR |
+ { n25q256a,INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K |
SPI_NOR_QUAD_READ) },
+ { n25q512a,INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K |
USE_FSR | SPI_NOR_QUAD_READ) },
+ { n25q512ax3, INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K |
USE_FSR | SPI_NOR_QUAD_READ) },
On 8 December 2014 at 09:50, Bean Huo 霍斌斌 (beanhuo) wrote:
> This patch is based on the latest l2-mtd,I don't know if can pass?
> I have one question is that about following code.
> I have added our Mciron quad flag into spi_nor_ids[] table,but line over 80
> characters,
> If I divided one line
>This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes.
>For Micron SPI NOR flash,enabling or disabling quad I/O protocol can be done
>By two methods, which are to
>use EVCR(Enhanced Volatile Configuration Register) and the ENTER QUAD I/O MODE
>command.There is no
This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes.
For Micron SPI NOR flash,enabling or disabling quad I/O protocol can be done
By two methods, which are to
use EVCR(Enhanced Volatile Configuration Register) and the ENTER QUAD I/O MODE
command.There is no
difference
On 8 December 2014 at 09:50, Bean Huo 霍斌斌 (beanhuo) bean...@micron.com wrote:
This patch is based on the latest l2-mtd,I don't know if can pass?
I have one question is that about following code.
I have added our Mciron quad flag into spi_nor_ids[] table,but line over 80
characters,
If I
This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes.
For Micron SPI NOR flash,enabling or disabling quad I/O protocol can be done
By two methods, which are to use EVCR(Enhanced Volatile Configuration Register)
and the ENTER QUAD I/O MODE command.There is no difference
This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes.
For Micron SPI NOR flash,enabling or disabling quad I/O protocol can be done
By two methods, which are to use EVCR(Enhanced Volatile Configuration Register)
and the ENTER QUAD I/O MODE command.There is no difference
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