Ensure that the M1XCLK and MCLK are sourced from
the same PLL (and refuse to bind the driver if they
are not).
Update the PCI to safe initialisation values, as 72MHz
is the maximum clock for 33MHz PCI bus mastering.
Signed-off-by: Ben Dooks <[EMAIL PROTECTED]>
Index:
Ensure that the M1XCLK and MCLK are sourced from
the same PLL (and refuse to bind the driver if they
are not).
Update the PCI to safe initialisation values, as 72MHz
is the maximum clock for 33MHz PCI bus mastering.
Signed-off-by: Ben Dooks [EMAIL PROTECTED]
Index:
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