gshan wrote:
Hey Guys,
I got a strange problem recently but no ideas, so to post the question
here. We have a FPGA what finish ATM AAL5 to ethernet frame, and CPU
receives IP packets from it. The interface based on the FPGA (called
sar0) has been bound with several IP addresses. When the MTU
gshan wrote:
Hey Guys,
I got a strange problem recently but no ideas, so to post the question
here. We have a FPGA what finish ATM AAL5 to ethernet frame, and CPU
receives IP packets from it. The interface based on the FPGA (called
sar0) has been bound with several IP addresses. When the MTU
Hey Guys,
I got a strange problem recently but no ideas, so to post the question
here. We have a FPGA what finish ATM AAL5 to ethernet frame, and CPU
receives IP packets from it. The interface based on the FPGA (called
sar0) has been bound with several IP addresses. When the MTU of the
Hey Guys,
I got a strange problem recently but no ideas, so to post the question
here. We have a FPGA what finish ATM AAL5 to ethernet frame, and CPU
receives IP packets from it. The interface based on the FPGA (called
sar0) has been bound with several IP addresses. When the MTU of the
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