Andrew Shewmaker wrote:
John Sigler wrote:
Andi Kleen wrote:
There are usually chipset specific bits that can be set to disable
SMMs. See the datasheet if you can get them. Unfortunately most
chipset vendors don't give out data sheets easily.
I managed to find the south bridge data sheet.
On 4/18/07, John Sigler <[EMAIL PROTECTED]> wrote:
Andi Kleen wrote:
> There are usually chipset specific bits that can be set to disable
> SMMs. See the datasheet if you can get them. Unfortunately most
> chipset vendors don't give out data sheets easily.
I managed to find the south bridge
Andi Kleen wrote:
There are usually chipset specific bits that can be set to disable
SMMs. See the datasheet if you can get them. Unfortunately most
chipset vendors don't give out data sheets easily.
I managed to find the south bridge data sheet.
http://linux.kernel.free.fr/VT82C686B.pdf
John Sigler wrote:
# : >/var/log/kern.log; cat /proc/interrupts; /bin/time insmod houba.ko;
cat /proc/interrupts; rmmod houba
CPU0
0: 519083XT-PIC-XTtimer
2: 0XT-PIC-XTcascade
9: 0XT-PIC-XTacpi
10: 9786
John Sigler wrote:
# : /var/log/kern.log; cat /proc/interrupts; /bin/time insmod houba.ko;
cat /proc/interrupts; rmmod houba
CPU0
0: 519083XT-PIC-XTtimer
2: 0XT-PIC-XTcascade
9: 0XT-PIC-XTacpi
10: 9786
Andi Kleen wrote:
There are usually chipset specific bits that can be set to disable
SMMs. See the datasheet if you can get them. Unfortunately most
chipset vendors don't give out data sheets easily.
I managed to find the south bridge data sheet.
http://linux.kernel.free.fr/VT82C686B.pdf
On 4/18/07, John Sigler [EMAIL PROTECTED] wrote:
Andi Kleen wrote:
There are usually chipset specific bits that can be set to disable
SMMs. See the datasheet if you can get them. Unfortunately most
chipset vendors don't give out data sheets easily.
I managed to find the south bridge data
Andrew Shewmaker wrote:
John Sigler wrote:
Andi Kleen wrote:
There are usually chipset specific bits that can be set to disable
SMMs. See the datasheet if you can get them. Unfortunately most
chipset vendors don't give out data sheets easily.
I managed to find the south bridge data sheet.
Andi Kleen wrote:
Modern x86 CPUs execute code out of order and in parallel.
I am aware of the (apparent) non-deterministic nature of
superscalar out-of-order speculative execution.
The reordering window can be quite large and the CPU can execute code
speculatively. This can add large
John Sigler wrote:
static int hello_init(void)
{
int i;
int *lat;
printk(KERN_ALERT "INIT\n");
lat = kmalloc(MAX * sizeof *lat, GFP_KERNEL);
if (lat == NULL) return -1;
for (i=0; i < MAX; ++i) lat[i] = 0;
for (i=0; i < 5; ++i) foo();
for (i=0; i < N; ++i)
{
unsigned count,
On Tue, Apr 17, 2007 at 06:49:09PM +0200, John Sigler wrote:
> >>.globl foo
> >>foo:
> >> push %ebx
> >> push %esi
> >> cpuid
> >> rdtsc
> >
> >At least some SMM implementations restore the old TSC value. Sad but true.
>
> Why would they do that?
I asked the same question. But it has
Andi Kleen wrote:
Please use a full real name for posting.
OK.
John Sigler wrote:
AFAIU, even a hard real-time OS is "defenseless" against SMIs that
kick the CPU into SMM.
There are usually chipset specific bits that can be set to disable SMMs.
See the datasheet if you can get them.
Andi Kleen wrote:
Please use a full real name for posting.
OK.
John Sigler wrote:
AFAIU, even a hard real-time OS is defenseless against SMIs that
kick the CPU into SMM.
There are usually chipset specific bits that can be set to disable SMMs.
See the datasheet if you can get them.
On Tue, Apr 17, 2007 at 06:49:09PM +0200, John Sigler wrote:
.globl foo
foo:
push %ebx
push %esi
cpuid
rdtsc
At least some SMM implementations restore the old TSC value. Sad but true.
Why would they do that?
I asked the same question. But it has been observed.
How would
John Sigler wrote:
static int hello_init(void)
{
int i;
int *lat;
printk(KERN_ALERT INIT\n);
lat = kmalloc(MAX * sizeof *lat, GFP_KERNEL);
if (lat == NULL) return -1;
for (i=0; i MAX; ++i) lat[i] = 0;
for (i=0; i 5; ++i) foo();
for (i=0; i N; ++i)
{
unsigned count, res;
Andi Kleen wrote:
Modern x86 CPUs execute code out of order and in parallel.
I am aware of the (apparent) non-deterministic nature of
superscalar out-of-order speculative execution.
The reordering window can be quite large and the CPU can execute code
speculatively. This can add large
John <[EMAIL PROTECTED]> writes:
Please use a full real name for posting.
> AFAIU, even a hard real-time OS is "defenseless" against SMIs that
> kick the CPU into SMM.
There are usually chipset specific bits that can be set to disable SMMs.
See the datasheet if you can get them. Unfortunately
On 4/16/07, John <[EMAIL PROTECTED]> wrote:
Chipset: VIA Pro133T
http://www.via.com.tw/en/products/chipsets/legacy/pro133/
VT82C694T north bridge + VT82C686B south bridge
AFAIU, the south bridge can be a source of SMIs.
Can the north bridge also be a source of SMIs?
What I/O ports do I need to
John wrote:
On the systems I have to work with [...]
I didn't specify what they were.
CPU: Intel Pentium 3
# cat /proc/cpuinfo
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 11
model name : Intel(R) Pentium(R) III CPU - S 1266MHz
Hello everyone,
According to Wikipedia:
http://en.wikipedia.org/wiki/Non-Maskable_Interrupt
http://en.wikipedia.org/wiki/System_Management_Mode
"SMM is an operating mode of the Intel 386SL and later microprocessor in
which all normal execution (including the operating system) is
suspended,
Hello everyone,
According to Wikipedia:
http://en.wikipedia.org/wiki/Non-Maskable_Interrupt
http://en.wikipedia.org/wiki/System_Management_Mode
SMM is an operating mode of the Intel 386SL and later microprocessor in
which all normal execution (including the operating system) is
suspended, and
John wrote:
On the systems I have to work with [...]
I didn't specify what they were.
CPU: Intel Pentium 3
# cat /proc/cpuinfo
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 11
model name : Intel(R) Pentium(R) III CPU - S 1266MHz
On 4/16/07, John [EMAIL PROTECTED] wrote:
Chipset: VIA Pro133T
http://www.via.com.tw/en/products/chipsets/legacy/pro133/
VT82C694T north bridge + VT82C686B south bridge
AFAIU, the south bridge can be a source of SMIs.
Can the north bridge also be a source of SMIs?
What I/O ports do I need to
John [EMAIL PROTECTED] writes:
Please use a full real name for posting.
AFAIU, even a hard real-time OS is defenseless against SMIs that
kick the CPU into SMM.
There are usually chipset specific bits that can be set to disable SMMs.
See the datasheet if you can get them. Unfortunately most
24 matches
Mail list logo
