Re: How long should be PCIe card in Warm Reset state?

2021-03-30 Thread Maciej W. Rozycki
On Tue, 30 Mar 2021, Pali Rohár wrote: > > The spec does not give any exceptions AFAICT as to the timeouts required > > between the three kinds of a Conventional Reset (Hot, Warm, or Cold) and > > refers to them collectively as a Conventional Reset across the relevant > > parts of the document

Re: How long should be PCIe card in Warm Reset state?

2021-03-30 Thread Pali Rohár
On Tuesday 30 March 2021 16:34:47 Maciej W. Rozycki wrote: > On Tue, 30 Mar 2021, Pali Rohár wrote: > > > > If I were to implement this stuff, for good measure I'd give it a safety > > > margin beyond what the spec requires and use a timeout of say 2-4s while > > > actively querying the status

Re: How long should be PCIe card in Warm Reset state?

2021-03-30 Thread Maciej W. Rozycki
On Tue, 30 Mar 2021, Pali Rohár wrote: > > If I were to implement this stuff, for good measure I'd give it a safety > > margin beyond what the spec requires and use a timeout of say 2-4s while > > actively querying the status of the device. The values given in the spec > > are only the minimu

Re: How long should be PCIe card in Warm Reset state?

2021-03-30 Thread Pali Rohár
On Tuesday 30 March 2021 15:04:02 Maciej W. Rozycki wrote: > On Thu, 25 Mar 2021, David Laight wrote: > > > I can't see the value in the (nice bound) copy of the PCI 2.0 spec I have. > > But IIRC it is 100ms (it might just me 500ms). > > While this might seem like ages it can be problematic if tar

RE: How long should be PCIe card in Warm Reset state?

2021-03-30 Thread Maciej W. Rozycki
On Thu, 25 Mar 2021, David Laight wrote: > I can't see the value in the (nice bound) copy of the PCI 2.0 spec I have. > But IIRC it is 100ms (it might just me 500ms). > While this might seem like ages it can be problematic if targets have > to load large FPGA images from serial EEPROMs. AFAICT i

RE: How long should be PCIe card in Warm Reset state?

2021-03-25 Thread David Laight
s doing this Warm > > > > Reset of connected PCIe card during native driver initialization > > > > procedure. > > > > > > > > And now the important question is: How long should be PCIe card in Warm > > > > Reset state? After which timeout can

Re: How long should be PCIe card in Warm Reset state?

2021-03-23 Thread Amey Narkhede
s triggered by asserting PERST# signal and in most cases > > > PERST# signal is controlled by GPIO. > > > > > > Basically every native Linux PCIe controller driver is doing this Warm > > > Reset of connected PCIe card during native driver initialization > > &

Re: How long should be PCIe card in Warm Reset state?

2021-03-23 Thread Pali Rohár
RST# signal is controlled by GPIO. > > > > Basically every native Linux PCIe controller driver is doing this Warm > > Reset of connected PCIe card during native driver initialization > > procedure. > > > > And now the important question is: How long should be PCIe c

Re: How long should be PCIe card in Warm Reset state?

2021-03-23 Thread Amey Narkhede
oller driver is doing this Warm > Reset of connected PCIe card during native driver initialization > procedure. > > And now the important question is: How long should be PCIe card in Warm > Reset state? After which timeout can be PERST# signal de-asserted by > Linux controller driver

How long should be PCIe card in Warm Reset state?

2021-03-10 Thread Pali Rohár
driver initialization procedure. And now the important question is: How long should be PCIe card in Warm Reset state? After which timeout can be PERST# signal de-asserted by Linux controller driver? Lorenzo and Rob already expressed concerns [1] [2] that this Warm Reset timeout should not be driver