On Thu, 5 Apr 2007 22:37:45 +0200 (MEST)
Jan Engelhardt <[EMAIL PROTECTED]> wrote:
> Hello Stephen,
>
> On Apr 5 2007 12:23, Stephen Hemminger wrote:
> >
> >If the radeon and/or the Ethernet driver support MSI, that would split
> >out the IRQ's as well.
>
> Would Linux do that automatically? How
Hello Stephen,
On Apr 5 2007 12:23, Stephen Hemminger wrote:
>
>If the radeon and/or the Ethernet driver support MSI, that would split
>out the IRQ's as well.
Would Linux do that automatically? How to find out whether a given
device -- or device driver? -- supports MSI?
Thanks,
Jan
--
-
To uns
On Thu, 05 Apr 2007 08:34:59 -0600
Robert Hancock <[EMAIL PROTECTED]> wrote:
> Jan Engelhardt wrote:
> > Hello list,
> >
> >
> >
> > let's take the following /proc/interrupts dump (CPU2,CPU3 trimmed)...
> >
> >CPU0 CPU1
> > 0: 37041766 37038991 IO-APIC-edge timer
> >
Jan Engelhardt wrote:
Hello list,
let's take the following /proc/interrupts dump (CPU2,CPU3 trimmed)...
CPU0 CPU1
0: 37041766 37038991 IO-APIC-edge timer
1: 10 2 IO-APIC-edge i8042
8: 0 0 IO-APIC-edge rtc
9: 0
On Thu, Apr 05, 2007 at 12:40:57PM +0200, Jan Engelhardt wrote:
> let's take the following /proc/interrupts dump (CPU2,CPU3 trimmed)...
>
>CPU0 CPU1
> 0: 37041766 37038991 IO-APIC-edge timer
> 1: 10 2 IO-APIC-edge i8042
> 8: 0 0 I
Jiri Kosina wrote:
> On Thu, 5 Apr 2007, Jan Engelhardt wrote:
>
>> My question is whether it is possible that eth0's interrupts go to CPU0
>
> Documentation/IRQ-affinity.txt
>
There is nothing in there tells ya how to get them off the same IRQ.
That has to be done first usually be moving one
On Thu, 5 Apr 2007, Jan Engelhardt wrote:
> My question is whether it is possible that eth0's interrupts go to CPU0
Documentation/IRQ-affinity.txt
--
Jiri Kosina
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More majordo
Hello list,
let's take the following /proc/interrupts dump (CPU2,CPU3 trimmed)...
CPU0 CPU1
0: 37041766 37038991 IO-APIC-edge timer
1: 10 2 IO-APIC-edge i8042
8: 0 0 IO-APIC-edge rtc
9: 0 0 IO-APIC-level a
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