On 26 August 2013 16:49, Alan Stern wrote:
> Here's a question that doesn't seem to be answered in
> Documentation/memory-barriers.txt. Are memory accesses within an
> interrupt handler synchronized with respect to interrupts?
>
> In more detail, suppose we have an interrupt handler that uses a
On 26 August 2013 16:49, Alan Stern st...@rowland.harvard.edu wrote:
Here's a question that doesn't seem to be answered in
Documentation/memory-barriers.txt. Are memory accesses within an
interrupt handler synchronized with respect to interrupts?
In more detail, suppose we have an interrupt
On 08/29/2013 04:51 PM, Paul E. McKenney wrote:
> On Wed, Aug 28, 2013 at 01:28:08PM -0700, H. Peter Anvin wrote:
>> On 08/28/2013 12:16 PM, Alan Stern wrote:
>>> Russell, Peter, and Ingo:
>>>
>>> Can you folks enlighten us regarding this issue for some common
>>> architectures?
>>
>> On x86,
On Thu, 2013-08-29 at 16:51 -0700, Paul E. McKenney wrote:
> On Wed, Aug 28, 2013 at 01:28:08PM -0700, H. Peter Anvin wrote:
> > On 08/28/2013 12:16 PM, Alan Stern wrote:
> > > Russell, Peter, and Ingo:
> > >
> > > Can you folks enlighten us regarding this issue for some common
> > >
On Wed, Aug 28, 2013 at 01:28:08PM -0700, H. Peter Anvin wrote:
> On 08/28/2013 12:16 PM, Alan Stern wrote:
> > Russell, Peter, and Ingo:
> >
> > Can you folks enlighten us regarding this issue for some common
> > architectures?
>
> On x86, IRET is a serializing instruction; it guarantees hard
On Wed, 28 Aug 2013, H. Peter Anvin wrote:
> On 08/28/2013 12:16 PM, Alan Stern wrote:
> > Russell, Peter, and Ingo:
> >
> > Can you folks enlighten us regarding this issue for some common
> > architectures?
> >
>
> On x86, IRET is a serializing instruction; it guarantees hard
> serialization
On Wed, 28 Aug 2013, H. Peter Anvin wrote:
On 08/28/2013 12:16 PM, Alan Stern wrote:
Russell, Peter, and Ingo:
Can you folks enlighten us regarding this issue for some common
architectures?
On x86, IRET is a serializing instruction; it guarantees hard
serialization of absolutely
On Wed, Aug 28, 2013 at 01:28:08PM -0700, H. Peter Anvin wrote:
On 08/28/2013 12:16 PM, Alan Stern wrote:
Russell, Peter, and Ingo:
Can you folks enlighten us regarding this issue for some common
architectures?
On x86, IRET is a serializing instruction; it guarantees hard
On Thu, 2013-08-29 at 16:51 -0700, Paul E. McKenney wrote:
On Wed, Aug 28, 2013 at 01:28:08PM -0700, H. Peter Anvin wrote:
On 08/28/2013 12:16 PM, Alan Stern wrote:
Russell, Peter, and Ingo:
Can you folks enlighten us regarding this issue for some common
architectures?
On
On 08/29/2013 04:51 PM, Paul E. McKenney wrote:
On Wed, Aug 28, 2013 at 01:28:08PM -0700, H. Peter Anvin wrote:
On 08/28/2013 12:16 PM, Alan Stern wrote:
Russell, Peter, and Ingo:
Can you folks enlighten us regarding this issue for some common
architectures?
On x86, IRET is a serializing
On 08/28/2013 12:16 PM, Alan Stern wrote:
> Russell, Peter, and Ingo:
>
> Can you folks enlighten us regarding this issue for some common
> architectures?
>
On x86, IRET is a serializing instruction; it guarantees hard
serialization of absolutely everything.
I would expect architectures that
Russell, Peter, and Ingo:
Can you folks enlighten us regarding this issue for some common
architectures?
On Tue, 27 Aug 2013, Paul E. McKenney wrote:
> On Mon, Aug 26, 2013 at 11:49:15AM -0400, Alan Stern wrote:
> > David and Paul:
> >
> > Here's a question that doesn't seem to be answered in
Russell, Peter, and Ingo:
Can you folks enlighten us regarding this issue for some common
architectures?
On Tue, 27 Aug 2013, Paul E. McKenney wrote:
On Mon, Aug 26, 2013 at 11:49:15AM -0400, Alan Stern wrote:
David and Paul:
Here's a question that doesn't seem to be answered in
On 08/28/2013 12:16 PM, Alan Stern wrote:
Russell, Peter, and Ingo:
Can you folks enlighten us regarding this issue for some common
architectures?
On x86, IRET is a serializing instruction; it guarantees hard
serialization of absolutely everything.
I would expect architectures that have
On Mon, Aug 26, 2013 at 11:49:15AM -0400, Alan Stern wrote:
> David and Paul:
>
> Here's a question that doesn't seem to be answered in
> Documentation/memory-barriers.txt. Are memory accesses within an
> interrupt handler synchronized with respect to interrupts?
>
> In more detail, suppose
On Mon, Aug 26, 2013 at 11:49:15AM -0400, Alan Stern wrote:
David and Paul:
Here's a question that doesn't seem to be answered in
Documentation/memory-barriers.txt. Are memory accesses within an
interrupt handler synchronized with respect to interrupts?
In more detail, suppose we have
David and Paul:
Here's a question that doesn't seem to be answered in
Documentation/memory-barriers.txt. Are memory accesses within an
interrupt handler synchronized with respect to interrupts?
In more detail, suppose we have an interrupt handler that uses a memory
variable A. The device
David and Paul:
Here's a question that doesn't seem to be answered in
Documentation/memory-barriers.txt. Are memory accesses within an
interrupt handler synchronized with respect to interrupts?
In more detail, suppose we have an interrupt handler that uses a memory
variable A. The device
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