On 01/18/2019 03:06 PM, Peter Zijlstra wrote:
> On Fri, Jan 18, 2019 at 09:50:12AM -0500, Waiman Long wrote:
>> On 01/18/2019 05:02 AM, Peter Zijlstra wrote:
e.g. We can't take an SError during the SError handler.
But we can take this SError/NMI on another CPU while the first one is
On Fri, Jan 18, 2019 at 09:50:12AM -0500, Waiman Long wrote:
> On 01/18/2019 05:02 AM, Peter Zijlstra wrote:
> >
> >> e.g. We can't take an SError during the SError handler.
> >>
> >> But we can take this SError/NMI on another CPU while the first one is still
> >> running the handler.
> >>
> >>
On 01/18/2019 05:02 AM, Peter Zijlstra wrote:
>
>> e.g. We can't take an SError during the SError handler.
>>
>> But we can take this SError/NMI on another CPU while the first one is still
>> running the handler.
>>
>> These multiple NMIlike notifications mean having multiple locks/fixmap-slots,
On Fri, Jan 18, 2019 at 11:02:29AM +0100, Peter Zijlstra wrote:
> Well, x86 too has multiple non-maskable vectors, and afaik only the
> actual NMI vector is covered in tricky. But our MCE vector is
> non-maskable too (and I have vague memories of there being more).
>
> Boris, Rostedt, WTH happens
On Mon, Jan 14, 2019 at 01:54:49PM +, James Morse wrote:
> On 14/01/2019 13:16, Peter Zijlstra wrote:
> > What avoids the trivial self-recursion:
> >
> > spin_lock(&)
> >
> > spin_lock()
> > ... wait forever more ...
> >
> > spin_unlock()
> >
> > ?
>
> If its trying to
On 01/14/2019 08:54 AM, James Morse wrote:
> Hi Peter,
>
> On 14/01/2019 13:16, Peter Zijlstra wrote:
>> On Fri, Jan 11, 2019 at 06:32:58PM +, James Morse wrote:
>>> On 10/01/2019 20:12, Peter Zijlstra wrote:
On Thu, Jan 10, 2019 at 06:25:57PM +, James Morse wrote:
The thing is,
Hi Peter,
On 14/01/2019 13:16, Peter Zijlstra wrote:
> On Fri, Jan 11, 2019 at 06:32:58PM +, James Morse wrote:
>> On 10/01/2019 20:12, Peter Zijlstra wrote:
>>> On Thu, Jan 10, 2019 at 06:25:57PM +, James Morse wrote:
>>> The thing is, everything non-maskable (NMI like) really should not
On Fri, Jan 11, 2019 at 06:32:58PM +, James Morse wrote:
> Hi Peter,
>
> On 10/01/2019 20:12, Peter Zijlstra wrote:
> > On Thu, Jan 10, 2019 at 06:25:57PM +, James Morse wrote:
> >
> >> On arm64 if all the RAS and psuedo-NMI patches land, our worst-case
> >> interleaving
> >> jumps to
- long...@redhat.com wrote:
> On 01/11/2019 12:06 AM, Zhenzhong Duan wrote:
> >
> >
> > On 2019/1/10 22:43, Waiman Long wrote:
> >> On 01/10/2019 03:02 AM, Zhenzhong Duan wrote:
> >>> Hi Maintainer,
> >>>
> >>>
> >>> There is a question confused me for days. Appreciate an answer.
> >>>
>
Hi Peter,
On 10/01/2019 20:12, Peter Zijlstra wrote:
> On Thu, Jan 10, 2019 at 06:25:57PM +, James Morse wrote:
>
>> On arm64 if all the RAS and psuedo-NMI patches land, our worst-case
>> interleaving
>> jumps to at least 7. The culprit is APEI using spinlocks to protect fixmap
>> slots.
On Fri, Jan 11, 2019 at 10:16:38AM +0100, Peter Zijlstra wrote:
> > Not for debug exception, for MCE exception handler I found below two:
> >
> > do_machine_check->mce_report_event->schedule_work
That has been the case at least since 2009. We probably never hit it or
I've never seen a deadlock
On 01/11/2019 12:06 AM, Zhenzhong Duan wrote:
>
>
> On 2019/1/10 22:43, Waiman Long wrote:
>> On 01/10/2019 03:02 AM, Zhenzhong Duan wrote:
>>> Hi Maintainer,
>>>
>>>
>>> There is a question confused me for days. Appreciate an answer.
>>>
>>> In below code, the comment says we never have more than
On Fri, Jan 11, 2019 at 04:06:52PM +0800, Zhenzhong Duan wrote:
>
> On 2019/1/10 22:43, Waiman Long wrote:
> > On 01/10/2019 03:02 AM, Zhenzhong Duan wrote:
> > > Hi Maintainer,
> > >
> > >
> > > There is a question confused me for days. Appreciate an answer.
> > >
> > > In below code, the
On Thu, Jan 10, 2019 at 06:25:57PM +, James Morse wrote:
> On arm64 if all the RAS and psuedo-NMI patches land, our worst-case
> interleaving
> jumps to at least 7. The culprit is APEI using spinlocks to protect fixmap
> slots.
>
> I have an RFC to bump the number of node bits from 2 to 3,
On Thu, Jan 10, 2019 at 04:02:53PM +0800, Zhenzhong Duan wrote:
> Hi Maintainer,
>
>
> There is a question confused me for days. Appreciate an answer.
>
> In below code, the comment says we never have more than 4 nested contexts.
>
> What happen if debug and mce exceptions nest with the four,
On 01/10/2019 01:25 PM, James Morse wrote:
> Hi Longman, Zhenzhong,
>
> On 10/01/2019 14:43, Waiman Long wrote:
>> On 01/10/2019 03:02 AM, Zhenzhong Duan wrote:
>>> There is a question confused me for days. Appreciate an answer.
>>>
>>> In below code, the comment says we never have more than 4
Hi Longman, Zhenzhong,
On 10/01/2019 14:43, Waiman Long wrote:
> On 01/10/2019 03:02 AM, Zhenzhong Duan wrote:
>> There is a question confused me for days. Appreciate an answer.
>>
>> In below code, the comment says we never have more than 4 nested
>> contexts.
>>
>> What happen if debug and mce
On 01/10/2019 03:02 AM, Zhenzhong Duan wrote:
> Hi Maintainer,
>
>
> There is a question confused me for days. Appreciate an answer.
>
> In below code, the comment says we never have more than 4 nested
> contexts.
>
> What happen if debug and mce exceptions nest with the four, or we
> ensure it
Hi Maintainer,
There is a question confused me for days. Appreciate an answer.
In below code, the comment says we never have more than 4 nested contexts.
What happen if debug and mce exceptions nest with the four, or we ensure
it never happen?
/*
* Per-CPU queue node structures; we can
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