On Fri, Jul 01, 2016 at 07:24:27PM +, Yu, Fenghua wrote:
> I haven't tested on AMD. But I think AMD should have the same code.
Again, bear in mind, this is a qemu+kvm guest.
> Could you please check if
> /sys/device/system/cpu/cpu#/cache/index#/shared_cpu_map contains only
> the cpu itself?
On Fri, Jul 01, 2016 at 07:24:27PM +, Yu, Fenghua wrote:
> I haven't tested on AMD. But I think AMD should have the same code.
Again, bear in mind, this is a qemu+kvm guest.
> Could you please check if
> /sys/device/system/cpu/cpu#/cache/index#/shared_cpu_map contains only
> the cpu itself?
On Fri, Jul 01, 2016 at 07:08:56PM +, Yu, Fenghua wrote:
> For L3 schema on a two socket system which has two L3 caches, user input:
> L3:0=3;1=f
Ok, so you basically want to read out the cache id from sysfs so that
userspace can configure CAT properly. Thanks for the detailed writeup.
Btw,
On Fri, Jul 01, 2016 at 07:08:56PM +, Yu, Fenghua wrote:
> For L3 schema on a two socket system which has two L3 caches, user input:
> L3:0=3;1=f
Ok, so you basically want to read out the cache id from sysfs so that
userspace can configure CAT properly. Thanks for the detailed writeup.
Btw,
<h.peter.an...@intel.com>; Peter Zijlstra <pet...@infradead.org>;
> Stephane Eranian <eran...@google.com>; Shankar, Ravi V
> <ravi.v.shan...@intel.com>; Vikas Shivappa
> <vikas.shiva...@linux.intel.com>; linux-kernel ker...@vger.kernel.org>; x86 <x...@ker
er...@vger.kernel.org>; x86
> Subject: Re: [PATCH] cacheinfo: Introduce cache id
>
> On Fri, Jul 01, 2016 at 06:01:06PM +, Yu, Fenghua wrote:
> > Cache id is unique on the same level of cache across platform.
>
> Btw, I forgot to ask in the reply to Tony: how are tho
> From: Borislav Petkov [mailto:b...@suse.de]
> Sent: Friday, July 01, 2016 11:40 AM
> On Fri, Jul 01, 2016 at 06:32:19PM +, Yu, Fenghua wrote:
> > We has prefix "L3" or "L2" in the syntax, id is for that level in each
> > line.b
>
> Give me a full example, please, how the id is going to be
> From: Borislav Petkov [mailto:b...@suse.de]
> Sent: Friday, July 01, 2016 11:40 AM
> On Fri, Jul 01, 2016 at 06:32:19PM +, Yu, Fenghua wrote:
> > We has prefix "L3" or "L2" in the syntax, id is for that level in each
> > line.b
>
> Give me a full example, please, how the id is going to be
On Fri, Jul 01, 2016 at 11:00:35AM -0700, Luck, Tony wrote:
> For CAT we only need the IDs to be unique at each level. Our tentative
> syntax for the schema file for CAT looks like this (for a theoretical
> system supporting CAT in both L2 and L3 with two L3 caches and eight L2
> caches)
>
>
On Fri, Jul 01, 2016 at 11:00:35AM -0700, Luck, Tony wrote:
> For CAT we only need the IDs to be unique at each level. Our tentative
> syntax for the schema file for CAT looks like this (for a theoretical
> system supporting CAT in both L2 and L3 with two L3 caches and eight L2
> caches)
>
>
On Fri, Jul 01, 2016 at 06:32:19PM +, Yu, Fenghua wrote:
> We has prefix "L3" or "L2" in the syntax, id is for that level in each line.b
Give me a full example, please, how the id is going to be used.
Thanks.
--
Regards/Gruss,
Boris.
SUSE Linux GmbH, GF: Felix Imendörffer, Jane
On Fri, Jul 01, 2016 at 06:32:19PM +, Yu, Fenghua wrote:
> We has prefix "L3" or "L2" in the syntax, id is for that level in each line.b
Give me a full example, please, how the id is going to be used.
Thanks.
--
Regards/Gruss,
Boris.
SUSE Linux GmbH, GF: Felix Imendörffer, Jane
On Fri, Jul 01, 2016 at 06:01:06PM +, Yu, Fenghua wrote:
> Cache id is unique on the same level of cache across platform.
Btw, I forgot to ask in the reply to Tony: how are those cache IDs
exactly going to be used? An example please...
> Could you check cpu#/cache/index#/shared_cpu_map or
On Fri, Jul 01, 2016 at 06:01:06PM +, Yu, Fenghua wrote:
> Cache id is unique on the same level of cache across platform.
Btw, I forgot to ask in the reply to Tony: how are those cache IDs
exactly going to be used? An example please...
> Could you check cpu#/cache/index#/shared_cpu_map or
h.peter.an...@intel.com>; Peter Zijlstra <pet...@infradead.org>;
> Stephane Eranian <eran...@google.com>; Shankar, Ravi V
> <ravi.v.shan...@intel.com>; Vikas Shivappa
> <vikas.shiva...@linux.intel.com>; linux-kernel ker...@vger.kernel.org>; x86 <x...@ker
er...@vger.kernel.org>; x86
> Subject: Re: [PATCH] cacheinfo: Introduce cache id
>
> On Fri, Jul 01, 2016 at 11:00:35AM -0700, Luck, Tony wrote:
> > For CAT we only need the IDs to be unique at each level. Our tentative
> > syntax for the schema file for CAT looks like this (
h.peter.an...@intel.com>; Peter Zijlstra <pet...@infradead.org>;
> Stephane Eranian <eran...@google.com>; Shankar, Ravi V
> <ravi.v.shan...@intel.com>; Vikas Shivappa
> <vikas.shiva...@linux.intel.com>; linux-kernel ker...@vger.kernel.org>; x86 <x...@ker
er...@vger.kernel.org>; x86
> Subject: Re: [PATCH] cacheinfo: Introduce cache id
>
> On Fri, Jul 01, 2016 at 09:50:41AM -0700, Luck, Tony wrote:
> > Here's the situation. We have lots of (mostly) independent caches on a
> system.
> > The L3 cache (also called LLC - La
> Basically all cache indices carry the APIC ID of the core, so L1D on
> CPU0 has ID 0 and then L1I has ID 0 too and then L2 has also the same
> ID.
>
> How does that look on a CAT system? Do all the different cache levels
> get different IDs?
For CAT we only need the IDs to be unique at each
> Basically all cache indices carry the APIC ID of the core, so L1D on
> CPU0 has ID 0 and then L1I has ID 0 too and then L2 has also the same
> ID.
>
> How does that look on a CAT system? Do all the different cache levels
> get different IDs?
For CAT we only need the IDs to be unique at each
On Fri, Jul 01, 2016 at 09:50:41AM -0700, Luck, Tony wrote:
> Here's the situation. We have lots of (mostly) independent caches on a
> system.
> The L3 cache (also called LLC - Last Level Cache - in some documentation) is
> usually shared by all cpus on a physical socket. The L1 and L2 caches
On Fri, Jul 01, 2016 at 09:50:41AM -0700, Luck, Tony wrote:
> Here's the situation. We have lots of (mostly) independent caches on a
> system.
> The L3 cache (also called LLC - Last Level Cache - in some documentation) is
> usually shared by all cpus on a physical socket. The L1 and L2 caches
On Fri, Jul 01, 2016 at 12:21:43PM +0200, Borislav Petkov wrote:
> On Wed, Jun 29, 2016 at 06:56:10PM -0700, Fenghua Yu wrote:
> > From: Fenghua Yu
> >
> > Each cache node is described by cacheinfo and is a unique node across
>
> What is a cache node?
Clearly not a good
On Fri, Jul 01, 2016 at 12:21:43PM +0200, Borislav Petkov wrote:
> On Wed, Jun 29, 2016 at 06:56:10PM -0700, Fenghua Yu wrote:
> > From: Fenghua Yu
> >
> > Each cache node is described by cacheinfo and is a unique node across
>
> What is a cache node?
Clearly not a good name for the concept we
On Wed, Jun 29, 2016 at 06:56:10PM -0700, Fenghua Yu wrote:
> From: Fenghua Yu
>
> Each cache node is described by cacheinfo and is a unique node across
What is a cache node?
> the platform. But there is no id for a cache node. We introduce cache ID
> to identify a cache
On Wed, Jun 29, 2016 at 06:56:10PM -0700, Fenghua Yu wrote:
> From: Fenghua Yu
>
> Each cache node is described by cacheinfo and is a unique node across
What is a cache node?
> the platform. But there is no id for a cache node. We introduce cache ID
> to identify a cache node.
>
> Intel Cache
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