On Wed, Apr 14, 2021 at 08:23:51AM +0800, Guo Ren wrote:
> On Tue, Apr 13, 2021 at 5:31 PM Catalin Marinas
> wrote:
> > On Tue, Apr 13, 2021 at 11:22:40AM +0200, Christoph Müllner wrote:
> > > On Tue, Apr 13, 2021 at 10:03 AM Peter Zijlstra
> > > wrote:
> > > > On Mon, Apr 12, 2021 at
On Wed, Apr 14, 2021 at 09:08:18AM +0200, Peter Zijlstra wrote:
> On Wed, Apr 14, 2021 at 10:26:57AM +0800, Guo Ren wrote:
> > Thx Peter,
> >
> > On Tue, Apr 13, 2021 at 4:17 PM Peter Zijlstra wrote:
> > >
> > > On Tue, Apr 13, 2021 at 10:03:01AM +0200, Peter Zijlstra wrote:
> > >
> > > > For
On Wed, Apr 14, 2021 at 10:26:57AM +0800, Guo Ren wrote:
> Thx Peter,
>
> On Tue, Apr 13, 2021 at 4:17 PM Peter Zijlstra wrote:
> >
> > On Tue, Apr 13, 2021 at 10:03:01AM +0200, Peter Zijlstra wrote:
> >
> > > For ticket locks you really only needs atomic_fetch_add() and
> > >
On Tue, Apr 13, 2021 at 6:54 PM David Laight wrote:
>
> From: Catalin Marinas
> > Sent: 13 April 2021 11:45
> ...
> > This indeed needs some care. IIUC RISC-V has similar restrictions as arm
> > here, no load/store instructions are allowed between LR and SC. You
> > can't guarantee that the
Thx Peter,
On Tue, Apr 13, 2021 at 4:17 PM Peter Zijlstra wrote:
>
> On Tue, Apr 13, 2021 at 10:03:01AM +0200, Peter Zijlstra wrote:
>
> > For ticket locks you really only needs atomic_fetch_add() and
> > smp_store_release() and an architectural guarantees that the
> > atomic_fetch_add() has fwd
On Tue, Apr 13, 2021 at 5:31 PM Catalin Marinas wrote:
>
> On Tue, Apr 13, 2021 at 11:22:40AM +0200, Christoph Müllner wrote:
> > On Tue, Apr 13, 2021 at 10:03 AM Peter Zijlstra
> > wrote:
> > > On Mon, Apr 12, 2021 at 11:54:55PM +0200, Christoph Müllner wrote:
> > > > On Mon, Apr 12, 2021 at
On Tue, Apr 13, 2021 at 6:25 PM Christoph Müllner
wrote:
>
> On Tue, Apr 13, 2021 at 11:37 AM Peter Zijlstra wrote:
> >
> > On Tue, Apr 13, 2021 at 11:22:40AM +0200, Christoph Müllner wrote:
> >
> > > > For ticket locks you really only needs atomic_fetch_add() and
> > > > smp_store_release() and
On Tue, Apr 13, 2021 at 12:45 PM Catalin Marinas
wrote:
>
> On Tue, Apr 13, 2021 at 12:25:00PM +0200, Christoph Müllner wrote:
> > On Tue, Apr 13, 2021 at 11:37 AM Peter Zijlstra
> > wrote:
> > > On Tue, Apr 13, 2021 at 11:22:40AM +0200, Christoph Müllner wrote:
> > > > What about trylock()?
>
From: Catalin Marinas
> Sent: 13 April 2021 11:45
...
> This indeed needs some care. IIUC RISC-V has similar restrictions as arm
> here, no load/store instructions are allowed between LR and SC. You
> can't guarantee that the compiler won't spill some variable onto the
> stack.
You can probably
On Tue, Apr 13, 2021 at 12:25:00PM +0200, Christoph Müllner wrote:
> On Tue, Apr 13, 2021 at 11:37 AM Peter Zijlstra wrote:
> > On Tue, Apr 13, 2021 at 11:22:40AM +0200, Christoph Müllner wrote:
> > > What about trylock()?
> > > I.e. one could implement trylock() without a loop, by letting
> > >
On Tue, Apr 13, 2021 at 11:37 AM Peter Zijlstra wrote:
>
> On Tue, Apr 13, 2021 at 11:22:40AM +0200, Christoph Müllner wrote:
>
> > > For ticket locks you really only needs atomic_fetch_add() and
> > > smp_store_release() and an architectural guarantees that the
> > > atomic_fetch_add() has fwd
On Tue, Apr 13, 2021 at 11:31 AM Catalin Marinas
wrote:
>
> On Tue, Apr 13, 2021 at 11:22:40AM +0200, Christoph Müllner wrote:
> > On Tue, Apr 13, 2021 at 10:03 AM Peter Zijlstra
> > wrote:
> > > On Mon, Apr 12, 2021 at 11:54:55PM +0200, Christoph Müllner wrote:
> > > > On Mon, Apr 12, 2021 at
On Tue, Apr 13, 2021 at 11:22:40AM +0200, Christoph Müllner wrote:
> > For ticket locks you really only needs atomic_fetch_add() and
> > smp_store_release() and an architectural guarantees that the
> > atomic_fetch_add() has fwd progress under contention and that a sub-word
> > store (through
On Tue, Apr 13, 2021 at 11:22:40AM +0200, Christoph Müllner wrote:
> On Tue, Apr 13, 2021 at 10:03 AM Peter Zijlstra wrote:
> > On Mon, Apr 12, 2021 at 11:54:55PM +0200, Christoph Müllner wrote:
> > > On Mon, Apr 12, 2021 at 7:33 PM Palmer Dabbelt wrote:
> > > > My plan is to add a generic
On Tue, Apr 13, 2021 at 10:03 AM Peter Zijlstra wrote:
>
> On Mon, Apr 12, 2021 at 11:54:55PM +0200, Christoph Müllner wrote:
> > On Mon, Apr 12, 2021 at 7:33 PM Palmer Dabbelt wrote:
>
> > > My plan is to add a generic ticket-based lock, which can be selected at
> > > compile time. It'll have
On Tue, Apr 13, 2021 at 10:03:01AM +0200, Peter Zijlstra wrote:
> For ticket locks you really only needs atomic_fetch_add() and
> smp_store_release() and an architectural guarantees that the
> atomic_fetch_add() has fwd progress under contention and that a sub-word
> store (through
On Mon, Apr 12, 2021 at 11:54:55PM +0200, Christoph Müllner wrote:
> On Mon, Apr 12, 2021 at 7:33 PM Palmer Dabbelt wrote:
> > My plan is to add a generic ticket-based lock, which can be selected at
> > compile time. It'll have no architecture dependencies (though it'll
> > likely have some
On Mon, Apr 12, 2021 at 7:33 PM Palmer Dabbelt wrote:
>
> On Mon, 12 Apr 2021 06:32:27 PDT (-0700), christoph...@gmail.com wrote:
> > On Sun, Apr 11, 2021 at 11:11 PM Palmer Dabbelt wrote:
> >>
> >> On Wed, 24 Mar 2021 05:53:51 PDT (-0700), a...@brainfault.org wrote:
> >> > On Wed, Mar 24, 2021
On Mon, Apr 12, 2021 at 4:52 PM Peter Zijlstra wrote:
>
>
> Please fix your mailer to properly flow text. Reflowed it for you.
>
> On Mon, Apr 12, 2021 at 03:32:27PM +0200, Christoph Müllner wrote:
>
> > This discussion came up again a few weeks ago because I've been
> > stumbling over the
On Mon, 12 Apr 2021 06:32:27 PDT (-0700), christoph...@gmail.com wrote:
On Sun, Apr 11, 2021 at 11:11 PM Palmer Dabbelt wrote:
On Wed, 24 Mar 2021 05:53:51 PDT (-0700), a...@brainfault.org wrote:
> On Wed, Mar 24, 2021 at 6:08 PM Peter Zijlstra wrote:
>>
>> On Wed, Mar 24, 2021 at 05:58:58PM
Please fix your mailer to properly flow text. Reflowed it for you.
On Mon, Apr 12, 2021 at 03:32:27PM +0200, Christoph Müllner wrote:
> This discussion came up again a few weeks ago because I've been
> stumbling over the test-and-set implementation and was wondering if
> nobody cared to
On Sun, Apr 11, 2021 at 11:11 PM Palmer Dabbelt wrote:
>
> On Wed, 24 Mar 2021 05:53:51 PDT (-0700), a...@brainfault.org wrote:
> > On Wed, Mar 24, 2021 at 6:08 PM Peter Zijlstra wrote:
> >>
> >> On Wed, Mar 24, 2021 at 05:58:58PM +0530, Anup Patel wrote:
> >> > On Wed, Mar 24, 2021 at 3:45 PM
On Wed, 24 Mar 2021 05:53:51 PDT (-0700), a...@brainfault.org wrote:
On Wed, Mar 24, 2021 at 6:08 PM Peter Zijlstra wrote:
On Wed, Mar 24, 2021 at 05:58:58PM +0530, Anup Patel wrote:
> On Wed, Mar 24, 2021 at 3:45 PM wrote:
> >
> > From: Guo Ren
> >
> > This patch introduces a ticket lock
On Wed, Mar 24, 2021 at 6:08 PM Peter Zijlstra wrote:
>
> On Wed, Mar 24, 2021 at 05:58:58PM +0530, Anup Patel wrote:
> > On Wed, Mar 24, 2021 at 3:45 PM wrote:
> > >
> > > From: Guo Ren
> > >
> > > This patch introduces a ticket lock implementation for riscv, along the
> > > same lines as the
On Wed, Mar 24, 2021 at 05:58:58PM +0530, Anup Patel wrote:
> On Wed, Mar 24, 2021 at 3:45 PM wrote:
> >
> > From: Guo Ren
> >
> > This patch introduces a ticket lock implementation for riscv, along the
> > same lines as the implementation for arch/arm & arch/csky.
> >
> > Signed-off-by: Guo Ren
On Wed, Mar 24, 2021 at 08:24:34PM +0800, Guo Ren wrote:
> On Wed, Mar 24, 2021 at 7:16 PM Vitaly Wool wrote:
> >
> >
> >
> > On Wed, Mar 24, 2021, 11:16 AM wrote:
> >>
> >> From: Guo Ren
> >>
> >> This patch introduces a ticket lock implementation for riscv, along the
> >> same lines as the
On Wed, Mar 24, 2021 at 3:45 PM wrote:
>
> From: Guo Ren
>
> This patch introduces a ticket lock implementation for riscv, along the
> same lines as the implementation for arch/arm & arch/csky.
>
> Signed-off-by: Guo Ren
> Cc: Catalin Marinas
> Cc: Will Deacon
> Cc: Peter Zijlstra
> Cc:
On Wed, Mar 24, 2021 at 7:16 PM Vitaly Wool wrote:
>
>
>
> On Wed, Mar 24, 2021, 11:16 AM wrote:
>>
>> From: Guo Ren
>>
>> This patch introduces a ticket lock implementation for riscv, along the
>> same lines as the implementation for arch/arm & arch/csky.
>
>
> Could you please provide a
On Wed, Mar 24, 2021 at 12:15:47PM +0100, Vitaly Wool wrote:
> On Wed, Mar 24, 2021, 11:16 AM wrote:
>
> > From: Guo Ren
> >
> > This patch introduces a ticket lock implementation for riscv, along the
> > same lines as the implementation for arch/arm & arch/csky.
> >
>
> Could you please
Thx Peter,
On Wed, Mar 24, 2021 at 7:09 PM Peter Zijlstra wrote:
>
> On Wed, Mar 24, 2021 at 10:14:52AM +, guo...@kernel.org wrote:
> > +static inline void arch_spin_lock(arch_spinlock_t *lock)
> > +{
> > + arch_spinlock_t lockval;
> > + u32 tmp;
> > +
> > + asm volatile (
> > +
On Wed, Mar 24, 2021 at 10:14:52AM +, guo...@kernel.org wrote:
> +static inline void arch_spin_lock(arch_spinlock_t *lock)
> +{
> + arch_spinlock_t lockval;
> + u32 tmp;
> +
> + asm volatile (
> + "1: lr.w%0, %2 \n"
> + " mv %1,
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