Re: [PATCH 1/2] RISC-V: Update l2 cache DT documentation to add support for SiFive FU740

nathan.came...@huawei.com; w...@kernel.org; s...@ravnborg.org; > > Sagar Kadam ; a...@brainfault.org; > > b...@suse.de; devicet...@vger.kernel.org; linux-ri...@lists.infradead.org; > > linux-kernel@vger.kernel.org; Sachin Ghadi > > Subject: Re: [PATCH 1/2] RISC-V: Update l2 cache D

RE: [PATCH 1/2] RISC-V: Update l2 cache DT documentation to add support for SiFive FU740

ault.org; > b...@suse.de; devicet...@vger.kernel.org; linux-ri...@lists.infradead.org; > linux-kernel@vger.kernel.org; Sachin Ghadi > Subject: Re: [PATCH 1/2] RISC-V: Update l2 cache DT documentation to add > support for SiFive FU740 > > [External Email] Do not click links or attachm

Re: [PATCH 1/2] RISC-V: Update l2 cache DT documentation to add support for SiFive FU740

On Thu, Nov 12, 2020 at 02:41:13PM +0530, Yash Shah wrote: > The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as > compared to 3 in FU540. Update the DT documentation accordingly with > "compatible" and "interrupt" property changes. > > Signed-off-by: Yash Shah > --- > .../dev