Hi,
Manish Narani writes:
>> -Original Message-
>> From: Felipe Balbi
>> Sent: Tuesday, September 1, 2020 5:45 PM
>>
>> >> > + goto err;
>> >> > + }
>> >> > +
>> >> > + ret = dwc3_xlnx_rst_assert(priv_data->apbrst);
>> >> > + if (ret < 0) {
>> >> > +
Hi Felipe,
Thanks for the response.
> -Original Message-
> From: Felipe Balbi
> Sent: Tuesday, September 1, 2020 5:45 PM
>
> >> > +goto err;
> >> > +}
> >> > +
> >> > +ret = dwc3_xlnx_rst_assert(priv_data->apbrst);
> >> > +if (ret < 0) {
> >> > +
Hi,
(remember to break your lines at 80-columns)
Manish Narani writes:
>> > + goto err;
>> > + }
>> > +
>> > + ret = dwc3_xlnx_rst_assert(priv_data->apbrst);
>> > + if (ret < 0) {
>> > + dev_err(dev, "%s: %d: Failed to assert reset\n",
>> > + __func__,
...@kernel.org;
p.za...@pengutronix.de
Cc: devicet...@vger.kernel.org; linux-...@vger.kernel.org; linux-
ker...@vger.kernel.org; git ; linux-arm-
ker...@lists.infradead.org
Subject: Re: [PATCH 2/2] usb: dwc3: Add driver for Xilinx platforms
On 2020-08-26 19:44, Manish Narani wrote
engutronix.de
> Cc: devicet...@vger.kernel.org; linux-...@vger.kernel.org; linux-
> ker...@vger.kernel.org; git ; linux-arm-
> ker...@lists.infradead.org
> Subject: Re: [PATCH 2/2] usb: dwc3: Add driver for Xilinx platforms
>
> On 2020-08-26 19:44, Manish Narani wrote:
>
nix.de
> Cc: linux-...@vger.kernel.org; devicet...@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org; git
> ;
> Manish Narani
> Subject: Re: [PATCH 2/2] usb: dwc3: Add driver for Xilinx platforms
>
> Manish Narani writes:
>
> >
On 2020-08-26 19:44, Manish Narani wrote:
[...]
+ /*
+* This routes the usb dma traffic to go through CCI path instead
+* of reaching DDR directly. This traffic routing is needed to
+* make SMMU and CCI work with USB dma.
+*/
+ if
Hi Manish,
On Thu, 2020-08-27 at 00:14 +0530, Manish Narani wrote:
> Add a new driver for supporting Xilinx platforms. This driver handles
> the USB 3.0 PHY initialization and PIPE control & reset operations for
> ZynqMP platforms. This also handles the USB 2.0 PHY initialization and
> reset
On Thu, 2020-08-27 at 00:14 +0530, Manish Narani wrote:
> Add a new driver for supporting Xilinx platforms. This driver handles
> the USB 3.0 PHY initialization and PIPE control & reset operations for
> ZynqMP platforms. This also handles the USB 2.0 PHY initialization and
> reset operations for
Manish Narani writes:
> Add a new driver for supporting Xilinx platforms. This driver handles
> the USB 3.0 PHY initialization and PIPE control & reset operations for
PHY initialization should be done as part of a drivers/phy driver.
> ZynqMP platforms. This also handles the USB 2.0 PHY
On 8/26/20 11:44 AM, Manish Narani wrote:
> diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
> index 7a2304565a73..416063ee9d05 100644
> --- a/drivers/usb/dwc3/Kconfig
> +++ b/drivers/usb/dwc3/Kconfig
> @@ -139,4 +139,12 @@ config USB_DWC3_QCOM
> for peripheral mode
11 matches
Mail list logo
