Hi Marc,
On 20 February 2019 11:33 Phil Edworthy wrote:
> On 20 February 2019 10:05 Marc Zyngier wrote:
> > On Wed, 20 Feb 2019 09:07:02 +, Phil Edworthy wrote:
> > > On 19 February 2019 20:29 Marc Zyngier wrote:
> >
> > [...]
> >
> > > > > + for (i = 0; i < MAX_NR_INPUT_IRQS; i++)
> > >
Hi Marc,
On 20 February 2019 10:05 Marc Zyngier wrote:
> On Wed, 20 Feb 2019 09:07:02 +, Phil Edworthy wrote:
> > On 19 February 2019 20:29 Marc Zyngier wrote:
>
> [...]
>
> > > > + for (i = 0; i < MAX_NR_INPUT_IRQS; i++)
> > > > + irq_create_mapping(priv->irq_domain,
On Wed, 20 Feb 2019 09:07:02 +,
Phil Edworthy wrote:
>
> Hi Marc
>
> On 19 February 2019 20:29 Marc Zyngier wrote:
[...]
> > > + for (i = 0; i < MAX_NR_INPUT_IRQS; i++)
> > > + irq_create_mapping(priv->irq_domain, i);
> >
> > This should never happen. Mappings should be created
Hi Marc
On 19 February 2019 20:29 Marc Zyngier wrote:
> On Tue, 19 Feb 2019 15:55:11 + Phil Edworthy wrote:
>
> + LinusW, who seem to have taken an interest in irqchip hierarchies...
>
> > On RZ/N1 devices, there are 3 Synopsys DesignWare GPIO blocks each
> > configured to have 32 interrupt
On Tue, 19 Feb 2019 15:55:11 +
Phil Edworthy wrote:
+ LinusW, who seem to have taken an interest in irqchip hierarchies...
> On RZ/N1 devices, there are 3 Synopsys DesignWare GPIO blocks each
> configured to have 32 interrupt outputs, so we have a total of 96 GPIO
> interrupts. All of these
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