RE: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller

> Subject: Re: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL > PCIe Host Controller > > On Wed, 25 Nov 2015 05:40:49 + > Bharat Kumar Gogada wrote: > > > > On Thu, 19 Nov 2015 11:05:23 +0530 > > > Bharat Kumar Gogada wrote: > &

Re: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller

On Wed, 25 Nov 2015 14:23:29 +0530 Amit Tomer wrote: > Sorry to intervene but just trying to learn from your comments. > > > You have plenty, and that's the whole of your device space. *All of it*. So > > just take the base address of your PCIe controller, and be done with > > it. > > but

Re: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller

Sorry to intervene but just trying to learn from your comments. > You have plenty, and that's the whole of your device space. *All of it*. So > just take the base address of your PCIe controller, and be done with > it. but isn't few of PCIe controller's registers itself are mapped here(base

RE: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller

> Subject: Re: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL > PCIe Host Controller > > On Wed, 25 Nov 2015 05:40:49 + > Bharat Kumar Gogada <bharat.kumar.gog...@xilinx.com> wrote: > > > > On Thu, 19 Nov 2015 11:05:23 +0530 > >

Re: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller

On Wed, 25 Nov 2015 14:23:29 +0530 Amit Tomer wrote: > Sorry to intervene but just trying to learn from your comments. > > > You have plenty, and that's the whole of your device space. *All of it*. So > > just take the base address of your PCIe controller, and be done

Re: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller

Sorry to intervene but just trying to learn from your comments. > You have plenty, and that's the whole of your device space. *All of it*. So > just take the base address of your PCIe controller, and be done with > it. but isn't few of PCIe controller's registers itself are mapped here(base

Re: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller

On Wed, 25 Nov 2015 05:40:49 + Bharat Kumar Gogada wrote: > > On Thu, 19 Nov 2015 11:05:23 +0530 > > Bharat Kumar Gogada wrote: > > > > > Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP. > > > > > > Signed-off-by: Bharat Kumar Gogada > > > Signed-off-by: Ravi Kiran Gummaluri >

RE: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller

> On Thu, 19 Nov 2015 11:05:23 +0530 > Bharat Kumar Gogada wrote: > > > Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP. > > > > Signed-off-by: Bharat Kumar Gogada > > Signed-off-by: Ravi Kiran Gummaluri > > Acked-by: Rob Herring > > --- > > + > > +#define MSI_ADDRESS

Re: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller

On Thu, 19 Nov 2015 11:05:23 +0530 Bharat Kumar Gogada wrote: > Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP. > > Signed-off-by: Bharat Kumar Gogada > Signed-off-by: Ravi Kiran Gummaluri > Acked-by: Rob Herring > --- > Changes for v9: > - Modified logic in nwl_irq_domain_alloc

Re: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller

On Wed, 25 Nov 2015 05:40:49 + Bharat Kumar Gogada wrote: > > On Thu, 19 Nov 2015 11:05:23 +0530 > > Bharat Kumar Gogada wrote: > > > > > Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP. > > > > > > Signed-off-by:

Re: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller

On Thu, 19 Nov 2015 11:05:23 +0530 Bharat Kumar Gogada wrote: > Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP. > > Signed-off-by: Bharat Kumar Gogada > Signed-off-by: Ravi Kiran Gummaluri > Acked-by: Rob

RE: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller

> On Thu, 19 Nov 2015 11:05:23 +0530 > Bharat Kumar Gogada wrote: > > > Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP. > > > > Signed-off-by: Bharat Kumar Gogada > > Signed-off-by: Ravi Kiran Gummaluri > >