RE: [PATCHv4] dmaengine: fsl-edma: fixup reg offset and hw S/G support in big-endian model

M >To: Lu Jingchang-B35083 >Cc: dmaeng...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; >linux-kernel@vger.kernel.org >Subject: Re: [PATCHv4] dmaengine: fsl-edma: fixup reg offset and hw S/G >support in big-endian model > >On Wed, Oct 22, 2014 at 04:53:55PM +0800, Jingch

Re: [PATCHv4] dmaengine: fsl-edma: fixup reg offset and hw S/G support in big-endian model

On Wed, Oct 22, 2014 at 04:53:55PM +0800, Jingchang Lu wrote: > The offset of all 8-/16-bit registers in big-endian eDMA model are > swapped in a 32-bit size opposite those in the little-endian model. > > The hardware Scatter/Gather requires the subsequent TCDs stored in memory > in little endian

RE: [PATCHv4] dmaengine: fsl-edma: fixup reg offset and hw S/G support in big-endian model

Hi, Vinod, Could you please help review and merge this patch if possible. Thanks. Thanks and Best Regards, Jingchang >>-Original Message- >>From: Jingchang Lu [mailto:jingchang...@freescale.com] >>Sent: Wednesday, October 22, 2014 4:54 PM >>To: vinod.k...@intel.com >>Cc: dmaeng...@vger

RE: [PATCHv4] dmaengine: fsl-edma: fixup reg offset and hw S/G support in big-endian model

Hi, Vinod, Could you please help review and merge this patch if possible. Thanks. Best Regards, Jingchang >-Original Message- >From: Jingchang Lu [mailto:jingchang...@freescale.com] >Sent: Wednesday, October 22, 2014 4:54 PM >To: vinod.k...@intel.com >Cc: dmaeng...@vger.kernel.org; lin