On 10/04/18 19:17, Stephen Boyd wrote:
Anyway, this is mostly an FYI that I don't have the hardware to test
with anymore and I'm not going to keep sending patches on this topic.
Srini should have some hardware to test whatever solution you come up
with.
Yep, I can test PCI MSI side of it with
On 10/04/18 19:17, Stephen Boyd wrote:
Anyway, this is mostly an FYI that I don't have the hardware to test
with anymore and I'm not going to keep sending patches on this topic.
Srini should have some hardware to test whatever solution you come up
with.
Yep, I can test PCI MSI side of it with
Hi Stephen,
On 10/04/18 19:17, Stephen Boyd wrote:
> Quoting Marc Zyngier (2018-04-10 08:23:00)
>> On 10/04/18 16:01, Thomas Petazzoni wrote:
>>
>>> In the upcoming Armada 8KP, we have a GICv3, which has built-in support
>>> for memory-triggered SPIs, thanks to the GICD_SETSPI_NSR and
>>>
Hi Stephen,
On 10/04/18 19:17, Stephen Boyd wrote:
> Quoting Marc Zyngier (2018-04-10 08:23:00)
>> On 10/04/18 16:01, Thomas Petazzoni wrote:
>>
>>> In the upcoming Armada 8KP, we have a GICv3, which has built-in support
>>> for memory-triggered SPIs, thanks to the GICD_SETSPI_NSR and
>>>
Quoting Marc Zyngier (2018-04-10 08:23:00)
> On 10/04/18 16:01, Thomas Petazzoni wrote:
>
> > In the upcoming Armada 8KP, we have a GICv3, which has built-in support
> > for memory-triggered SPIs, thanks to the GICD_SETSPI_NSR and
> > GICD_CLRSPI_NSR, and the ICU will directly use this GICv3
> >
Quoting Marc Zyngier (2018-04-10 08:23:00)
> On 10/04/18 16:01, Thomas Petazzoni wrote:
>
> > In the upcoming Armada 8KP, we have a GICv3, which has built-in support
> > for memory-triggered SPIs, thanks to the GICD_SETSPI_NSR and
> > GICD_CLRSPI_NSR, and the ICU will directly use this GICv3
> >
On 10/04/18 16:23, Marc Zyngier wrote:
> I have a vague idea how to support this. Given that level-triggered MSIs
> have to be platform MSIs (because it is just madness otherwise), we can
> probably store an extra message in the struct platform_msi_desc for the
> "lower the line" write. On
On 10/04/18 16:23, Marc Zyngier wrote:
> I have a vague idea how to support this. Given that level-triggered MSIs
> have to be platform MSIs (because it is just madness otherwise), we can
> probably store an extra message in the struct platform_msi_desc for the
> "lower the line" write. On
On 10/04/18 16:41, Thomas Petazzoni wrote:
> Hello,
>
> Thanks for your feedback!
>
> On Tue, 10 Apr 2018 16:23:00 +0100, Marc Zyngier wrote:
>
>>> In the current Marvell Armada 7K/8K, we have a unit called the ICU
>>> that turns wired level interrupts on one side of the chip into MSIs,
>>>
On 10/04/18 16:41, Thomas Petazzoni wrote:
> Hello,
>
> Thanks for your feedback!
>
> On Tue, 10 Apr 2018 16:23:00 +0100, Marc Zyngier wrote:
>
>>> In the current Marvell Armada 7K/8K, we have a unit called the ICU
>>> that turns wired level interrupts on one side of the chip into MSIs,
>>>
Hello,
Thanks for your feedback!
On Tue, 10 Apr 2018 16:23:00 +0100, Marc Zyngier wrote:
> > In the current Marvell Armada 7K/8K, we have a unit called the ICU
> > that turns wired level interrupts on one side of the chip into MSIs,
> > signaled to the GIC through a special unit called GICP,
Hello,
Thanks for your feedback!
On Tue, 10 Apr 2018 16:23:00 +0100, Marc Zyngier wrote:
> > In the current Marvell Armada 7K/8K, we have a unit called the ICU
> > that turns wired level interrupts on one side of the chip into MSIs,
> > signaled to the GIC through a special unit called GICP,
Hi Thomas,
On 10/04/18 16:01, Thomas Petazzoni wrote:
> Hello Marc, Hello Stephen,
>
> On Tue, 21 Mar 2017 09:43:24 +, Marc Zyngier wrote:
>
>> The whole idea behind this GICD_SETSPI_NSR is to offer a way to signal
>> SPIs using memory transaction, even allowing level interrupts (in
>>
Hi Thomas,
On 10/04/18 16:01, Thomas Petazzoni wrote:
> Hello Marc, Hello Stephen,
>
> On Tue, 21 Mar 2017 09:43:24 +, Marc Zyngier wrote:
>
>> The whole idea behind this GICD_SETSPI_NSR is to offer a way to signal
>> SPIs using memory transaction, even allowing level interrupts (in
>>
Hello Marc, Hello Stephen,
On Tue, 21 Mar 2017 09:43:24 +, Marc Zyngier wrote:
> The whole idea behind this GICD_SETSPI_NSR is to offer a way to signal
> SPIs using memory transaction, even allowing level interrupts (in
> combinaison with the GICD_CLRSPI_NSR at offset 0x48). This is *not* a
Hello Marc, Hello Stephen,
On Tue, 21 Mar 2017 09:43:24 +, Marc Zyngier wrote:
> The whole idea behind this GICD_SETSPI_NSR is to offer a way to signal
> SPIs using memory transaction, even allowing level interrupts (in
> combinaison with the GICD_CLRSPI_NSR at offset 0x48). This is *not* a
On 20/03/17 22:36, Stephen Boyd wrote:
> Some GIC configurations don't have an ITS or v2m frame, but they
> want to support MSIs through the distributor's "v2m backwards
> compatible" mode. This mode allows software written for the v2m
> to treat the distributor as the only frame and support a
On 20/03/17 22:36, Stephen Boyd wrote:
> Some GIC configurations don't have an ITS or v2m frame, but they
> want to support MSIs through the distributor's "v2m backwards
> compatible" mode. This mode allows software written for the v2m
> to treat the distributor as the only frame and support a
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