在 2021/1/20 18:27, Paraschiv, Andra-Irina 写道:
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> On 19/01/2021 05:30, Longpeng(Mike) wrote:
>> According the PCI spec:
>> Bus Master Enable – Controls the ability of a PCI Express
>> Endpoint to issue Memory and I/O Read/Write Requests, and
>> the ability of a Root or Switch Port
On 19/01/2021 05:30, Longpeng(Mike) wrote:
According the PCI spec:
Bus Master Enable – Controls the ability of a PCI Express
Endpoint to issue Memory and I/O Read/Write Requests, and
the ability of a Root or Switch Port to forward Memory and
I/O Read/Write Requests in the Upstream
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