On Fri, 2015-08-07 at 11:19 +0800, Chenhui Zhao wrote:
> On Fri, Aug 7, 2015 at 2:02 AM, Scott Wood
> wrote:
> > On Thu, 2015-08-06 at 13:54 +0800, Chenhui Zhao wrote:
> > > On Thu, Aug 6, 2015 at 1:46 PM, Scott Wood
> > > wrote:
> > > > On Thu, 2015-08-06 at 12:20 +0800, Chenhui Zhao wrote:
On Fri, 2015-08-07 at 11:19 +0800, Chenhui Zhao wrote:
On Fri, Aug 7, 2015 at 2:02 AM, Scott Wood scottw...@freescale.com
wrote:
On Thu, 2015-08-06 at 13:54 +0800, Chenhui Zhao wrote:
On Thu, Aug 6, 2015 at 1:46 PM, Scott Wood scottw...@freescale.com
wrote:
On Thu, 2015-08-06 at
On Fri, Aug 7, 2015 at 2:02 AM, Scott Wood
wrote:
On Thu, 2015-08-06 at 13:54 +0800, Chenhui Zhao wrote:
On Thu, Aug 6, 2015 at 1:46 PM, Scott Wood
wrote:
> On Thu, 2015-08-06 at 12:20 +0800, Chenhui Zhao wrote:
> > On Thu, Aug 6, 2015 at 10:57 AM, Scott Wood
> >
> > wrote:
> >
On Thu, 2015-08-06 at 13:54 +0800, Chenhui Zhao wrote:
> On Thu, Aug 6, 2015 at 1:46 PM, Scott Wood
> wrote:
> > On Thu, 2015-08-06 at 12:20 +0800, Chenhui Zhao wrote:
> > > On Thu, Aug 6, 2015 at 10:57 AM, Scott Wood
> > >
> > > wrote:
> > > > On Wed, 2015-08-05 at 18:11 +0800, Chenhui
On Fri, Aug 7, 2015 at 2:02 AM, Scott Wood scottw...@freescale.com
wrote:
On Thu, 2015-08-06 at 13:54 +0800, Chenhui Zhao wrote:
On Thu, Aug 6, 2015 at 1:46 PM, Scott Wood scottw...@freescale.com
wrote:
On Thu, 2015-08-06 at 12:20 +0800, Chenhui Zhao wrote:
On Thu, Aug 6, 2015 at
On Thu, 2015-08-06 at 13:54 +0800, Chenhui Zhao wrote:
On Thu, Aug 6, 2015 at 1:46 PM, Scott Wood scottw...@freescale.com
wrote:
On Thu, 2015-08-06 at 12:20 +0800, Chenhui Zhao wrote:
On Thu, Aug 6, 2015 at 10:57 AM, Scott Wood
scottw...@freescale.com
wrote:
On Wed,
On Thu, Aug 6, 2015 at 1:46 PM, Scott Wood
wrote:
On Thu, 2015-08-06 at 12:20 +0800, Chenhui Zhao wrote:
On Thu, Aug 6, 2015 at 10:57 AM, Scott Wood
wrote:
> On Wed, 2015-08-05 at 18:11 +0800, Chenhui Zhao wrote:
> > On Tue, Aug 4, 2015 at 4:26 AM, Scott Wood
> > wrote:
> > >
On Thu, 2015-08-06 at 12:20 +0800, Chenhui Zhao wrote:
> On Thu, Aug 6, 2015 at 10:57 AM, Scott Wood
> wrote:
> > On Wed, 2015-08-05 at 18:11 +0800, Chenhui Zhao wrote:
> > > On Tue, Aug 4, 2015 at 4:26 AM, Scott Wood
> > > wrote:
> > > > On Mon, 2015-08-03 at 19:32 +0800, Chenhui Zhao
On Thu, Aug 6, 2015 at 10:57 AM, Scott Wood
wrote:
On Wed, 2015-08-05 at 18:11 +0800, Chenhui Zhao wrote:
On Tue, Aug 4, 2015 at 4:26 AM, Scott Wood
wrote:
> On Mon, 2015-08-03 at 19:32 +0800, Chenhui Zhao wrote:
> > >
>
> > On Sat, Aug 1, 2015 at 7:59 AM, Scott Wood
> >
On Wed, 2015-08-05 at 18:11 +0800, Chenhui Zhao wrote:
> On Tue, Aug 4, 2015 at 4:26 AM, Scott Wood
> wrote:
> > On Mon, 2015-08-03 at 19:32 +0800, Chenhui Zhao wrote:
> > > >
> >
> > > On Sat, Aug 1, 2015 at 7:59 AM, Scott Wood
> > > wrote:
> >
> > > >
> > > > Could you explain
On Tue, Aug 4, 2015 at 4:26 AM, Scott Wood
wrote:
On Mon, 2015-08-03 at 19:32 +0800, Chenhui Zhao wrote:
>
On Sat, Aug 1, 2015 at 7:59 AM, Scott Wood
wrote:
>
> Could you explain irq_mask()? Why would there still be IRQs
destined
> for
> this CPU at this point?
This
On Tue, Aug 4, 2015 at 4:26 AM, Scott Wood scottw...@freescale.com
wrote:
On Mon, 2015-08-03 at 19:32 +0800, Chenhui Zhao wrote:
On Sat, Aug 1, 2015 at 7:59 AM, Scott Wood scottw...@freescale.com
wrote:
Could you explain irq_mask()? Why would there still be IRQs
destined
On Thu, Aug 6, 2015 at 1:46 PM, Scott Wood scottw...@freescale.com
wrote:
On Thu, 2015-08-06 at 12:20 +0800, Chenhui Zhao wrote:
On Thu, Aug 6, 2015 at 10:57 AM, Scott Wood
scottw...@freescale.com
wrote:
On Wed, 2015-08-05 at 18:11 +0800, Chenhui Zhao wrote:
On Tue, Aug 4, 2015 at
On Thu, Aug 6, 2015 at 10:57 AM, Scott Wood scottw...@freescale.com
wrote:
On Wed, 2015-08-05 at 18:11 +0800, Chenhui Zhao wrote:
On Tue, Aug 4, 2015 at 4:26 AM, Scott Wood scottw...@freescale.com
wrote:
On Mon, 2015-08-03 at 19:32 +0800, Chenhui Zhao wrote:
On Sat, Aug 1,
On Thu, 2015-08-06 at 12:20 +0800, Chenhui Zhao wrote:
On Thu, Aug 6, 2015 at 10:57 AM, Scott Wood scottw...@freescale.com
wrote:
On Wed, 2015-08-05 at 18:11 +0800, Chenhui Zhao wrote:
On Tue, Aug 4, 2015 at 4:26 AM, Scott Wood scottw...@freescale.com
wrote:
On Mon, 2015-08-03 at
On Wed, 2015-08-05 at 18:11 +0800, Chenhui Zhao wrote:
On Tue, Aug 4, 2015 at 4:26 AM, Scott Wood scottw...@freescale.com
wrote:
On Mon, 2015-08-03 at 19:32 +0800, Chenhui Zhao wrote:
On Sat, Aug 1, 2015 at 7:59 AM, Scott Wood scottw...@freescale.com
wrote:
Could
On Mon, 2015-08-03 at 19:32 +0800, Chenhui Zhao wrote:
> >
> On Sat, Aug 1, 2015 at 7:59 AM, Scott Wood
> wrote:
> >
> > Could you explain irq_mask()? Why would there still be IRQs destined
> > for
> > this CPU at this point?
>
> This function just masks irq by setting the registers in
On Sat, Aug 1, 2015 at 7:59 AM, Scott Wood
wrote:
On Fri, 2015-07-31 at 17:20 +0800, b29...@freescale.com wrote:
@@ -71,7 +56,7 @@ static void mpc85xx_give_timebase(void)
barrier();
tb_req = 0;
- mpc85xx_timebase_freeze(1);
+
On Sat, Aug 1, 2015 at 7:59 AM, Scott Wood scottw...@freescale.com
wrote:
On Fri, 2015-07-31 at 17:20 +0800, b29...@freescale.com wrote:
@@ -71,7 +56,7 @@ static void mpc85xx_give_timebase(void)
barrier();
tb_req = 0;
- mpc85xx_timebase_freeze(1);
+
On Mon, 2015-08-03 at 19:32 +0800, Chenhui Zhao wrote:
On Sat, Aug 1, 2015 at 7:59 AM, Scott Wood scottw...@freescale.com
wrote:
Could you explain irq_mask()? Why would there still be IRQs destined
for
this CPU at this point?
This function just masks irq by setting the
On Fri, 2015-07-31 at 17:20 +0800, b29...@freescale.com wrote:
> @@ -71,7 +56,7 @@ static void mpc85xx_give_timebase(void)
> barrier();
> tb_req = 0;
>
> - mpc85xx_timebase_freeze(1);
> + qoriq_pm_ops->freeze_time_base(1);
freeze_time_base() takes a bool. Use
On Fri, 2015-07-31 at 17:20 +0800, b29...@freescale.com wrote:
@@ -71,7 +56,7 @@ static void mpc85xx_give_timebase(void)
barrier();
tb_req = 0;
- mpc85xx_timebase_freeze(1);
+ qoriq_pm_ops-freeze_time_base(1);
freeze_time_base() takes a bool. Use true/false.
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