On 24 January 2017 14:43:56 GMT+00:00, Fabrice Gasnier
wrote:
>On 01/22/2017 02:14 PM, Jonathan Cameron wrote:
>> On 19/01/17 13:34, Fabrice Gasnier wrote:
>>> Add optional DMA support to STM32 ADC.
>>> Use dma cyclic mode with at least two periods.
>>>
>>>
On 24 January 2017 14:43:56 GMT+00:00, Fabrice Gasnier
wrote:
>On 01/22/2017 02:14 PM, Jonathan Cameron wrote:
>> On 19/01/17 13:34, Fabrice Gasnier wrote:
>>> Add optional DMA support to STM32 ADC.
>>> Use dma cyclic mode with at least two periods.
>>>
>>> Signed-off-by: Fabrice Gasnier
>>
On 01/22/2017 02:14 PM, Jonathan Cameron wrote:
On 19/01/17 13:34, Fabrice Gasnier wrote:
Add optional DMA support to STM32 ADC.
Use dma cyclic mode with at least two periods.
Signed-off-by: Fabrice Gasnier
What is the point going forward in supporting non dma
On 01/22/2017 02:14 PM, Jonathan Cameron wrote:
On 19/01/17 13:34, Fabrice Gasnier wrote:
Add optional DMA support to STM32 ADC.
Use dma cyclic mode with at least two periods.
Signed-off-by: Fabrice Gasnier
What is the point going forward in supporting non dma buffered reads at all?
Is there
On 19/01/17 13:34, Fabrice Gasnier wrote:
> Add optional DMA support to STM32 ADC.
> Use dma cyclic mode with at least two periods.
>
> Signed-off-by: Fabrice Gasnier
What is the point going forward in supporting non dma buffered reads at all?
Is there hardware that
On 19/01/17 13:34, Fabrice Gasnier wrote:
> Add optional DMA support to STM32 ADC.
> Use dma cyclic mode with at least two periods.
>
> Signed-off-by: Fabrice Gasnier
What is the point going forward in supporting non dma buffered reads at all?
Is there hardware that doesn't have DMA support?
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