Re: [PATCH i2c-next v4] i2c: aspeed: Handle master/slave combined irq events properly

2018-08-23 Thread Jae Hyun Yoo
Hi Brendan, On 8/22/2018 11:46 PM, Brendan Higgins wrote: On Mon, Aug 20, 2018 at 1:16 PM Jae Hyun Yoo wrote: In most of cases, interrupt bits are set one by one but there are also a lot of other cases that Aspeed I2C IP sends multiple interrupt bits with combining master and slave events

Re: [PATCH i2c-next v4] i2c: aspeed: Handle master/slave combined irq events properly

2018-08-23 Thread Jae Hyun Yoo
Hi Brendan, On 8/22/2018 11:46 PM, Brendan Higgins wrote: On Mon, Aug 20, 2018 at 1:16 PM Jae Hyun Yoo wrote: In most of cases, interrupt bits are set one by one but there are also a lot of other cases that Aspeed I2C IP sends multiple interrupt bits with combining master and slave events

Re: [PATCH i2c-next v4] i2c: aspeed: Handle master/slave combined irq events properly

2018-08-23 Thread Brendan Higgins
On Mon, Aug 20, 2018 at 1:16 PM Jae Hyun Yoo wrote: > > In most of cases, interrupt bits are set one by one but there are > also a lot of other cases that Aspeed I2C IP sends multiple > interrupt bits with combining master and slave events using a > single interrupt call. It happens much more in

Re: [PATCH i2c-next v4] i2c: aspeed: Handle master/slave combined irq events properly

2018-08-23 Thread Brendan Higgins
On Mon, Aug 20, 2018 at 1:16 PM Jae Hyun Yoo wrote: > > In most of cases, interrupt bits are set one by one but there are > also a lot of other cases that Aspeed I2C IP sends multiple > interrupt bits with combining master and slave events using a > single interrupt call. It happens much more in