Hi Brendan,
On 8/22/2018 11:46 PM, Brendan Higgins wrote:
On Mon, Aug 20, 2018 at 1:16 PM Jae Hyun Yoo
wrote:
In most of cases, interrupt bits are set one by one but there are
also a lot of other cases that Aspeed I2C IP sends multiple
interrupt bits with combining master and slave events
Hi Brendan,
On 8/22/2018 11:46 PM, Brendan Higgins wrote:
On Mon, Aug 20, 2018 at 1:16 PM Jae Hyun Yoo
wrote:
In most of cases, interrupt bits are set one by one but there are
also a lot of other cases that Aspeed I2C IP sends multiple
interrupt bits with combining master and slave events
On Mon, Aug 20, 2018 at 1:16 PM Jae Hyun Yoo
wrote:
>
> In most of cases, interrupt bits are set one by one but there are
> also a lot of other cases that Aspeed I2C IP sends multiple
> interrupt bits with combining master and slave events using a
> single interrupt call. It happens much more in
On Mon, Aug 20, 2018 at 1:16 PM Jae Hyun Yoo
wrote:
>
> In most of cases, interrupt bits are set one by one but there are
> also a lot of other cases that Aspeed I2C IP sends multiple
> interrupt bits with combining master and slave events using a
> single interrupt call. It happens much more in
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