* Catalin Marinas [120817 02:21]:
> On Fri, Aug 17, 2012 at 10:04:52AM +0100, Tony Lindgren wrote:
> > * Catalin Marinas [120814 10:57]:
> > > The virtual memory layout is described in
> > > Documentation/arm64/memory.txt. This patch adds the MMU definitions for
> > > the 4KB and 64KB
On Fri, Aug 17, 2012 at 10:04:52AM +0100, Tony Lindgren wrote:
> * Catalin Marinas [120814 10:57]:
> > The virtual memory layout is described in
> > Documentation/arm64/memory.txt. This patch adds the MMU definitions for
> > the 4KB and 64KB translation table configurations. The SECTION_SIZE is
>
* Catalin Marinas [120814 10:57]:
> The virtual memory layout is described in
> Documentation/arm64/memory.txt. This patch adds the MMU definitions for
> the 4KB and 64KB translation table configurations. The SECTION_SIZE is
> 2MB with 4KB page and 512MB with 64KB page configuration.
>
>
* Catalin Marinas catalin.mari...@arm.com [120814 10:57]:
The virtual memory layout is described in
Documentation/arm64/memory.txt. This patch adds the MMU definitions for
the 4KB and 64KB translation table configurations. The SECTION_SIZE is
2MB with 4KB page and 512MB with 64KB page
On Fri, Aug 17, 2012 at 10:04:52AM +0100, Tony Lindgren wrote:
* Catalin Marinas catalin.mari...@arm.com [120814 10:57]:
The virtual memory layout is described in
Documentation/arm64/memory.txt. This patch adds the MMU definitions for
the 4KB and 64KB translation table configurations. The
* Catalin Marinas catalin.mari...@arm.com [120817 02:21]:
On Fri, Aug 17, 2012 at 10:04:52AM +0100, Tony Lindgren wrote:
* Catalin Marinas catalin.mari...@arm.com [120814 10:57]:
The virtual memory layout is described in
Documentation/arm64/memory.txt. This patch adds the MMU definitions
On Wed, Aug 15, 2012 at 05:34:46PM +0100, Geert Uytterhoeven wrote:
> On Wed, Aug 15, 2012 at 3:30 PM, Arnd Bergmann wrote:
> >> +#define TCR_IPS_40BIT(2 << 32)
>
> By default, constants are int, i.e. 32-bit. So you must write
>
> 2ULL << 32
>
> >> +#define TCR_ASID16
On Wed, Aug 15, 2012 at 3:30 PM, Arnd Bergmann wrote:
>> +#define TCR_IPS_40BIT(2 << 32)
By default, constants are int, i.e. 32-bit. So you must write
2ULL << 32
>> +#define TCR_ASID16 (1 << 36)
1ULL
> As a matter of coding style, I would much prefer tables like
Hi Arnd,
On Wed, Aug 15, 2012 at 02:30:01PM +0100, Arnd Bergmann wrote:
> On Tuesday 14 August 2012, Catalin Marinas wrote:
> > +/*
> > + * TCR flags.
> > + */
> > +#define TCR_TxSZ(x)(((64 - (x)) << 16) | ((64 - (x)) << 0))
> > +#define TCR_IRGN_NC((0 << 8) | (0
On Tuesday 14 August 2012, Catalin Marinas wrote:
>
> +/*
> + * TCR flags.
> + */
> +#define TCR_TxSZ(x) (((64 - (x)) << 16) | ((64 - (x)) << 0))
> +#define TCR_IRGN_NC ((0 << 8) | (0 << 24))
> +#define TCR_IRGN_WBWA((1 << 8) | (1 << 24))
> +#define TCR_IRGN_WT
On Tuesday 14 August 2012, Catalin Marinas wrote:
+/*
+ * TCR flags.
+ */
+#define TCR_TxSZ(x) (((64 - (x)) 16) | ((64 - (x)) 0))
+#define TCR_IRGN_NC ((0 8) | (0 24))
+#define TCR_IRGN_WBWA((1 8) | (1 24))
+#define TCR_IRGN_WT ((2 8) | (2
Hi Arnd,
On Wed, Aug 15, 2012 at 02:30:01PM +0100, Arnd Bergmann wrote:
On Tuesday 14 August 2012, Catalin Marinas wrote:
+/*
+ * TCR flags.
+ */
+#define TCR_TxSZ(x)(((64 - (x)) 16) | ((64 - (x)) 0))
+#define TCR_IRGN_NC((0 8) | (0 24))
+#define
On Wed, Aug 15, 2012 at 3:30 PM, Arnd Bergmann a...@arndb.de wrote:
+#define TCR_IPS_40BIT(2 32)
By default, constants are int, i.e. 32-bit. So you must write
2ULL 32
+#define TCR_ASID16 (1 36)
1ULL
As a matter of coding style, I would much prefer tables like
On Wed, Aug 15, 2012 at 05:34:46PM +0100, Geert Uytterhoeven wrote:
On Wed, Aug 15, 2012 at 3:30 PM, Arnd Bergmann a...@arndb.de wrote:
+#define TCR_IPS_40BIT(2 32)
By default, constants are int, i.e. 32-bit. So you must write
2ULL 32
+#define TCR_ASID16 (1
14 matches
Mail list logo
