Re: [PATCH v2 1/1] MIPS: Add Kconfig variable for CPUs with unaligned load/store instructions

2018-09-26 Thread Yasha Cherikovsky
Hi Paul, On Wed, 2018-09-26 at 22:18 +, Paul Burton wrote: > Hi Yasha, > > On Wed, Sep 26, 2018 at 02:16:15PM +0300, Yasha Cherikovsky wrote: > > MIPSR6 CPUs do not support unaligned load/store instructions > > (LWL, LWR, SWL, SWR and LDL, LDR, SDL, SDR for 64bit). > > > > Currently the

Re: [PATCH v2 1/1] MIPS: Add Kconfig variable for CPUs with unaligned load/store instructions

2018-09-26 Thread Yasha Cherikovsky
Hi Paul, On Wed, 2018-09-26 at 22:18 +, Paul Burton wrote: > Hi Yasha, > > On Wed, Sep 26, 2018 at 02:16:15PM +0300, Yasha Cherikovsky wrote: > > MIPSR6 CPUs do not support unaligned load/store instructions > > (LWL, LWR, SWL, SWR and LDL, LDR, SDL, SDR for 64bit). > > > > Currently the

Re: [PATCH v2 1/1] MIPS: Add Kconfig variable for CPUs with unaligned load/store instructions

2018-09-26 Thread Paul Burton
Hi Yasha, On Wed, Sep 26, 2018 at 02:16:15PM +0300, Yasha Cherikovsky wrote: > MIPSR6 CPUs do not support unaligned load/store instructions > (LWL, LWR, SWL, SWR and LDL, LDR, SDL, SDR for 64bit). > > Currently the MIPS tree has some special cases to avoid these > instructions, and the code is

Re: [PATCH v2 1/1] MIPS: Add Kconfig variable for CPUs with unaligned load/store instructions

2018-09-26 Thread Paul Burton
Hi Yasha, On Wed, Sep 26, 2018 at 02:16:15PM +0300, Yasha Cherikovsky wrote: > MIPSR6 CPUs do not support unaligned load/store instructions > (LWL, LWR, SWL, SWR and LDL, LDR, SDL, SDR for 64bit). > > Currently the MIPS tree has some special cases to avoid these > instructions, and the code is