On Fri, Jan 5, 2018 at 6:12 PM, Tim Chen wrote:
> cpuid ax=0x7, return rdx bit 26 to indicate presence of this feature
> IA32_SPEC_CTRL (0x48)
> IA32_SPEC_CTRL, bit0 – Indirect Branch Restricted Speculation (IBRS)
>
> If IBRS is set, near returns and near indirect
On Fri, Jan 5, 2018 at 6:12 PM, Tim Chen wrote:
> cpuid ax=0x7, return rdx bit 26 to indicate presence of this feature
> IA32_SPEC_CTRL (0x48)
> IA32_SPEC_CTRL, bit0 – Indirect Branch Restricted Speculation (IBRS)
>
> If IBRS is set, near returns and near indirect jumps/calls will not allow
>
On 01/09/2018 09:58 AM, Paolo Bonzini wrote:
> On 09/01/2018 18:53, Tim Chen wrote:
>> On 01/09/2018 02:39 AM, Paolo Bonzini wrote:
>>
>>> +
>>> +#define MSR_IA32_SPEC_CTRL 0x0048
>>> +#define SPEC_CTRL_FEATURE_DISABLE_IBRS (0 << 0)
>>> +#define SPEC_CTRL_FEATURE_ENABLE_IBRS
On 01/09/2018 09:58 AM, Paolo Bonzini wrote:
> On 09/01/2018 18:53, Tim Chen wrote:
>> On 01/09/2018 02:39 AM, Paolo Bonzini wrote:
>>
>>> +
>>> +#define MSR_IA32_SPEC_CTRL 0x0048
>>> +#define SPEC_CTRL_FEATURE_DISABLE_IBRS (0 << 0)
>>> +#define SPEC_CTRL_FEATURE_ENABLE_IBRS
On Tue, Jan 09, 2018 at 10:13:23AM -0800, Dave Hansen wrote:
> FWIW, I like the idea of including "SPEC_CTRL_" because it matches the
> constant to the MSR name. But I don't care that much.
Sure - just the "FEATURE_" part of the string is redundant.
--
Regards/Gruss,
Boris.
Good mailing
On Tue, Jan 09, 2018 at 10:13:23AM -0800, Dave Hansen wrote:
> FWIW, I like the idea of including "SPEC_CTRL_" because it matches the
> constant to the MSR name. But I don't care that much.
Sure - just the "FEATURE_" part of the string is redundant.
--
Regards/Gruss,
Boris.
Good mailing
On 01/06/2018 04:56 AM, Borislav Petkov wrote:
>> +#define MSR_IA32_SPEC_CTRL 0x0048
>> +#define SPEC_CTRL_FEATURE_DISABLE_IBRS (0 << 0)
>> +#define SPEC_CTRL_FEATURE_ENABLE_IBRS (1 << 0)
> s/_FEATURE//
>
> SPEC_CTRL_{ENABLE,DISABLE}_IBRS is good enough.
FWIW, I like the
On 01/06/2018 04:56 AM, Borislav Petkov wrote:
>> +#define MSR_IA32_SPEC_CTRL 0x0048
>> +#define SPEC_CTRL_FEATURE_DISABLE_IBRS (0 << 0)
>> +#define SPEC_CTRL_FEATURE_ENABLE_IBRS (1 << 0)
> s/_FEATURE//
>
> SPEC_CTRL_{ENABLE,DISABLE}_IBRS is good enough.
FWIW, I like the
On 09/01/2018 18:53, Tim Chen wrote:
> On 01/09/2018 02:39 AM, Paolo Bonzini wrote:
>
>> +
>> +#define MSR_IA32_SPEC_CTRL 0x0048
>> +#define SPEC_CTRL_FEATURE_DISABLE_IBRS (0 << 0)
>> +#define SPEC_CTRL_FEATURE_ENABLE_IBRS (1 << 0)
>
>
> Boris requested that the name for
On 09/01/2018 18:53, Tim Chen wrote:
> On 01/09/2018 02:39 AM, Paolo Bonzini wrote:
>
>> +
>> +#define MSR_IA32_SPEC_CTRL 0x0048
>> +#define SPEC_CTRL_FEATURE_DISABLE_IBRS (0 << 0)
>> +#define SPEC_CTRL_FEATURE_ENABLE_IBRS (1 << 0)
>
>
> Boris requested that the name for
On 01/09/2018 02:39 AM, Paolo Bonzini wrote:
> +
> +#define MSR_IA32_SPEC_CTRL 0x0048
> +#define SPEC_CTRL_FEATURE_DISABLE_IBRS (0 << 0)
> +#define SPEC_CTRL_FEATURE_ENABLE_IBRS(1 << 0)
Boris requested that the name for ENABLE/DISABLE to be shortened to
On 01/09/2018 02:39 AM, Paolo Bonzini wrote:
> +
> +#define MSR_IA32_SPEC_CTRL 0x0048
> +#define SPEC_CTRL_FEATURE_DISABLE_IBRS (0 << 0)
> +#define SPEC_CTRL_FEATURE_ENABLE_IBRS(1 << 0)
Boris requested that the name for ENABLE/DISABLE to be shortened to
On 06/01/2018 03:12, Tim Chen wrote:
> diff --git a/arch/x86/include/asm/msr-index.h
> b/arch/x86/include/asm/msr-index.h
> index 34c4922..f881add 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -42,6 +42,10 @@
> #define MSR_PPIN_CTL
On 06/01/2018 03:12, Tim Chen wrote:
> diff --git a/arch/x86/include/asm/msr-index.h
> b/arch/x86/include/asm/msr-index.h
> index 34c4922..f881add 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -42,6 +42,10 @@
> #define MSR_PPIN_CTL
On 06/01/2018 03:12, Tim Chen wrote:
> cpuid ax=0x7, return rdx bit 26 to indicate presence of this feature
> IA32_SPEC_CTRL (0x48)
> IA32_SPEC_CTRL, bit0 – Indirect Branch Restricted Speculation (IBRS)
>
> If IBRS is set, near returns and near indirect jumps/calls will not allow
> their
On 06/01/2018 03:12, Tim Chen wrote:
> cpuid ax=0x7, return rdx bit 26 to indicate presence of this feature
> IA32_SPEC_CTRL (0x48)
> IA32_SPEC_CTRL, bit0 – Indirect Branch Restricted Speculation (IBRS)
>
> If IBRS is set, near returns and near indirect jumps/calls will not allow
> their
On Sun, Jan 07, 2018 at 09:14:57AM -0800, Tim Chen wrote:
> RSB is return stack buffer, basically speculation addresses for return
> statement.
I had a very good idea what it was but maybe other readers might not. So
please write out abbreviations on their first use.
--
Regards/Gruss,
On Sun, Jan 07, 2018 at 09:14:57AM -0800, Tim Chen wrote:
> RSB is return stack buffer, basically speculation addresses for return
> statement.
I had a very good idea what it was but maybe other readers might not. So
please write out abbreviations on their first use.
--
Regards/Gruss,
On 01/06/2018 04:56 AM, Borislav Petkov wrote:
> On Fri, Jan 05, 2018 at 06:12:16PM -0800, Tim Chen wrote:
>
> <--- This needs an introductory sentence here.
>
>> cpuid ax=0x7, return rdx bit 26 to indicate presence of this feature
>
> You can write that as CPUID(7).RDX[26].
>
>>
On 01/06/2018 04:56 AM, Borislav Petkov wrote:
> On Fri, Jan 05, 2018 at 06:12:16PM -0800, Tim Chen wrote:
>
> <--- This needs an introductory sentence here.
>
>> cpuid ax=0x7, return rdx bit 26 to indicate presence of this feature
>
> You can write that as CPUID(7).RDX[26].
>
>>
On Fri, Jan 05, 2018 at 06:12:16PM -0800, Tim Chen wrote:
<--- This needs an introductory sentence here.
> cpuid ax=0x7, return rdx bit 26 to indicate presence of this feature
You can write that as CPUID(7).RDX[26].
> IA32_SPEC_CTRL (0x48)
> IA32_SPEC_CTRL, bit0 – Indirect Branch Restricted
On Fri, Jan 05, 2018 at 06:12:16PM -0800, Tim Chen wrote:
<--- This needs an introductory sentence here.
> cpuid ax=0x7, return rdx bit 26 to indicate presence of this feature
You can write that as CPUID(7).RDX[26].
> IA32_SPEC_CTRL (0x48)
> IA32_SPEC_CTRL, bit0 – Indirect Branch Restricted
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