On Wed, 31 Mar 2021 16:28:46 +0100,
Alexandru Elisei wrote:
>
> Hello,
>
> On 3/30/21 12:12 PM, Suzuki K Poulose wrote:
> > Hi Marc
> >
> > On 30/03/2021 11:12, Marc Zyngier wrote:
> >> Hi Suzuki,
> >>
> >> [+ Alex]
> >>
> >> On Tue, 23 Mar 2021 12:06:35 +,
> >> Suzuki K Poulose wrote:
>
Hello,
On 3/30/21 12:12 PM, Suzuki K Poulose wrote:
> Hi Marc
>
> On 30/03/2021 11:12, Marc Zyngier wrote:
>> Hi Suzuki,
>>
>> [+ Alex]
>>
>> On Tue, 23 Mar 2021 12:06:35 +,
>> Suzuki K Poulose wrote:
>>> [..]
>>
>>> #define MDCR_EL2_TTRF (1 << 19)
>>> #define MDCR_EL2_TPMS
On Tue, 30 Mar 2021 at 10:47, Greg KH wrote:
>
> On Tue, Mar 30, 2021 at 10:33:51AM -0600, Mathieu Poirier wrote:
> > On Tue, 30 Mar 2021 at 09:35, Greg KH wrote:
> > >
> > > On Tue, Mar 30, 2021 at 09:23:14AM -0600, Mathieu Poirier wrote:
> > > > On Tue, Mar 30, 2021 at 11:38:18AM +0100, Suzuki
On Tue, Mar 30, 2021 at 10:33:51AM -0600, Mathieu Poirier wrote:
> On Tue, 30 Mar 2021 at 09:35, Greg KH wrote:
> >
> > On Tue, Mar 30, 2021 at 09:23:14AM -0600, Mathieu Poirier wrote:
> > > On Tue, Mar 30, 2021 at 11:38:18AM +0100, Suzuki K Poulose wrote:
> > > > On 26/03/2021 16:55, Mathieu
On Tue, 30 Mar 2021 at 09:35, Greg KH wrote:
>
> On Tue, Mar 30, 2021 at 09:23:14AM -0600, Mathieu Poirier wrote:
> > On Tue, Mar 30, 2021 at 11:38:18AM +0100, Suzuki K Poulose wrote:
> > > On 26/03/2021 16:55, Mathieu Poirier wrote:
> > > > On Tue, Mar 23, 2021 at 12:06:35PM +, Suzuki K
On Tue, Mar 30, 2021 at 09:23:14AM -0600, Mathieu Poirier wrote:
> On Tue, Mar 30, 2021 at 11:38:18AM +0100, Suzuki K Poulose wrote:
> > On 26/03/2021 16:55, Mathieu Poirier wrote:
> > > On Tue, Mar 23, 2021 at 12:06:35PM +, Suzuki K Poulose wrote:
> > > > For a nvhe host, the EL2 must allow
On Tue, 30 Mar 2021 16:23:14 +0100,
Mathieu Poirier wrote:
>
> On Tue, Mar 30, 2021 at 11:38:18AM +0100, Suzuki K Poulose wrote:
> > On 26/03/2021 16:55, Mathieu Poirier wrote:
> > > On Tue, Mar 23, 2021 at 12:06:35PM +, Suzuki K Poulose wrote:
> > > > For a nvhe host, the EL2 must allow the
On Tue, Mar 30, 2021 at 11:38:18AM +0100, Suzuki K Poulose wrote:
> On 26/03/2021 16:55, Mathieu Poirier wrote:
> > On Tue, Mar 23, 2021 at 12:06:35PM +, Suzuki K Poulose wrote:
> > > For a nvhe host, the EL2 must allow the EL1&0 translation
> > > regime for TraceBuffer (MDCR_EL2.E2TB ==
On Tue, 30 Mar 2021 14:34:23 +0100,
Suzuki K Poulose wrote:
>
> On 30/03/2021 13:15, Marc Zyngier wrote:
> > On Tue, 30 Mar 2021 12:12:49 +0100,
> > Suzuki K Poulose wrote:
[...]
> >> May be we could do this check at kvm_arch_vcpu_load()/put() ?
> >
> > That would extend the tracing blackout
On 30/03/2021 13:15, Marc Zyngier wrote:
On Tue, 30 Mar 2021 12:12:49 +0100,
Suzuki K Poulose wrote:
Hi Marc
On 30/03/2021 11:12, Marc Zyngier wrote:
Hi Suzuki,
[+ Alex]
On Tue, 23 Mar 2021 12:06:35 +,
Suzuki K Poulose wrote:
For a nvhe host, the EL2 must allow the EL1&0
On Tue, 30 Mar 2021 12:12:49 +0100,
Suzuki K Poulose wrote:
>
> Hi Marc
>
> On 30/03/2021 11:12, Marc Zyngier wrote:
> > Hi Suzuki,
> >
> > [+ Alex]
> >
> > On Tue, 23 Mar 2021 12:06:35 +,
> > Suzuki K Poulose wrote:
> >>
> >> For a nvhe host, the EL2 must allow the EL1&0 translation
>
Hi Marc
On 30/03/2021 11:12, Marc Zyngier wrote:
Hi Suzuki,
[+ Alex]
On Tue, 23 Mar 2021 12:06:35 +,
Suzuki K Poulose wrote:
For a nvhe host, the EL2 must allow the EL1&0 translation
regime for TraceBuffer (MDCR_EL2.E2TB == 0b11). This must
be saved/restored over a trip to the guest.
On 26/03/2021 16:55, Mathieu Poirier wrote:
On Tue, Mar 23, 2021 at 12:06:35PM +, Suzuki K Poulose wrote:
For a nvhe host, the EL2 must allow the EL1&0 translation
regime for TraceBuffer (MDCR_EL2.E2TB == 0b11). This must
be saved/restored over a trip to the guest. Also, before
entering the
Hi Mathieu,
On Fri, 26 Mar 2021 16:55:50 +,
Mathieu Poirier wrote:
>
> On Tue, Mar 23, 2021 at 12:06:35PM +, Suzuki K Poulose wrote:
> > For a nvhe host, the EL2 must allow the EL1&0 translation
> > regime for TraceBuffer (MDCR_EL2.E2TB == 0b11). This must
> > be saved/restored over a
Hi Suzuki,
[+ Alex]
On Tue, 23 Mar 2021 12:06:35 +,
Suzuki K Poulose wrote:
>
> For a nvhe host, the EL2 must allow the EL1&0 translation
> regime for TraceBuffer (MDCR_EL2.E2TB == 0b11). This must
> be saved/restored over a trip to the guest. Also, before
> entering the guest, we must
On Tue, Mar 23, 2021 at 12:06:35PM +, Suzuki K Poulose wrote:
> For a nvhe host, the EL2 must allow the EL1&0 translation
> regime for TraceBuffer (MDCR_EL2.E2TB == 0b11). This must
> be saved/restored over a trip to the guest. Also, before
> entering the guest, we must flush any trace data if
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