On Wed, May 21, 2014 at 12:34:21PM +0100, Liviu Dudau wrote:
> On Wed, May 21, 2014 at 04:45:29PM +0530, Sunil Kovvuri wrote:
> > Hi Liviu,
> >
> > Sorry for the trouble.
> > I got why 'res->parent' is not set in my case.
> > Basically my SR-IOV device has fixed resources, so resources will not
>
On Wed, May 21, 2014 at 04:45:29PM +0530, Sunil Kovvuri wrote:
> Hi Liviu,
>
> Sorry for the trouble.
> I got why 'res->parent' is not set in my case.
> Basically my SR-IOV device has fixed resources, so resources will not
> be allocated/assigned and hence parent resource is not set.
> I will
Hi Liviu,
Sorry for the trouble.
I got why 'res->parent' is not set in my case.
Basically my SR-IOV device has fixed resources, so resources will not
be allocated/assigned and hence parent resource is not set.
I will move the resource claiming to host controller driver as a fixup
so that parent
Hi Liviu,
Sorry for the trouble.
I got why 'res-parent' is not set in my case.
Basically my SR-IOV device has fixed resources, so resources will not
be allocated/assigned and hence parent resource is not set.
I will move the resource claiming to host controller driver as a fixup
so that parent
On Wed, May 21, 2014 at 04:45:29PM +0530, Sunil Kovvuri wrote:
Hi Liviu,
Sorry for the trouble.
I got why 'res-parent' is not set in my case.
Basically my SR-IOV device has fixed resources, so resources will not
be allocated/assigned and hence parent resource is not set.
I will move the
On Wed, May 21, 2014 at 12:34:21PM +0100, Liviu Dudau wrote:
On Wed, May 21, 2014 at 04:45:29PM +0530, Sunil Kovvuri wrote:
Hi Liviu,
Sorry for the trouble.
I got why 'res-parent' is not set in my case.
Basically my SR-IOV device has fixed resources, so resources will not
be
On Tue, May 20, 2014 at 2:14 PM, Arnd Bergmann wrote:
> On Tuesday 20 May 2014 09:52:33 Sunil Kovvuri wrote:
>> >> In sriov_enable() (drivers/pci/iov.c)
>> >>
>> >> 296for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
>> >> 297 bars |= (1 << (i + PCI_IOV_RESOURCES));
>> >> 298
On Tuesday 20 May 2014 09:52:33 Sunil Kovvuri wrote:
> >> In sriov_enable() (drivers/pci/iov.c)
> >>
> >> 296for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
> >> 297 bars |= (1 << (i + PCI_IOV_RESOURCES));
> >> 298 res = dev->resource + PCI_IOV_RESOURCES + i;
On Tuesday 20 May 2014 09:52:33 Sunil Kovvuri wrote:
In sriov_enable() (drivers/pci/iov.c)
296for (i = 0; i PCI_SRIOV_NUM_BARS; i++) {
297 bars |= (1 (i + PCI_IOV_RESOURCES));
298 res = dev-resource + PCI_IOV_RESOURCES + i;
299
On Tue, May 20, 2014 at 2:14 PM, Arnd Bergmann a...@arndb.de wrote:
On Tuesday 20 May 2014 09:52:33 Sunil Kovvuri wrote:
In sriov_enable() (drivers/pci/iov.c)
296for (i = 0; i PCI_SRIOV_NUM_BARS; i++) {
297 bars |= (1 (i + PCI_IOV_RESOURCES));
298
On Mon, May 19, 2014 at 6:31 PM, Arnd Bergmann wrote:
> On Friday 16 May 2014 16:03:04 Sunil Kovvuri wrote:
>> When the SR-IOV capable device's driver tries to enable sriov
>> (pci_enable_sriov()) it fails to create/add PCI device for each
>> virtual function reporting "not enough MMIO resources
On Friday 16 May 2014 16:03:04 Sunil Kovvuri wrote:
> When the SR-IOV capable device's driver tries to enable sriov
> (pci_enable_sriov()) it fails to create/add PCI device for each
> virtual function reporting "not enough MMIO resources for SR-IOV".
I assume you have checked that there is
On Mon, May 19, 2014 at 6:31 PM, Arnd Bergmann a...@arndb.de wrote:
On Friday 16 May 2014 16:03:04 Sunil Kovvuri wrote:
When the SR-IOV capable device's driver tries to enable sriov
(pci_enable_sriov()) it fails to create/add PCI device for each
virtual function reporting not enough MMIO
On Friday 16 May 2014 16:03:04 Sunil Kovvuri wrote:
When the SR-IOV capable device's driver tries to enable sriov
(pci_enable_sriov()) it fails to create/add PCI device for each
virtual function reporting not enough MMIO resources for SR-IOV.
I assume you have checked that there is indeed
Hi Liviu,
Issue may not be only with SR-IOV resources.
I am not an expert with Linux PCI core. But i am trying to understand
how even for a non SR-IOV capable device's resource, gets a parent
associated with it.
When a PCI device driver calls pci_enable_device() which inturn calls
Hi Sunil,
On Fri, May 16, 2014 at 11:33:04AM +0100, Sunil Kovvuri wrote:
> Hi Liviu,
>
> I am using your ARM64 PCIe patches to write a PCIe host controller
> driver for our SOC. I am facing an issue with SR-IOV capable device.
>
> Consider an PCI Express endpoint connected to a PCI Express
>
Hi Liviu,
I am using your ARM64 PCIe patches to write a PCIe host controller
driver for our SOC. I am facing an issue with SR-IOV capable device.
Consider an PCI Express endpoint connected to a PCI Express
Root Port. The PCI Express endpoint provides PCI-SIG SR-IOV
capabilities with a single
Hi Liviu,
I am using your ARM64 PCIe patches to write a PCIe host controller
driver for our SOC. I am facing an issue with SR-IOV capable device.
Consider an PCI Express endpoint connected to a PCI Express
Root Port. The PCI Express endpoint provides PCI-SIG SR-IOV
capabilities with a single
Hi Sunil,
On Fri, May 16, 2014 at 11:33:04AM +0100, Sunil Kovvuri wrote:
Hi Liviu,
I am using your ARM64 PCIe patches to write a PCIe host controller
driver for our SOC. I am facing an issue with SR-IOV capable device.
Consider an PCI Express endpoint connected to a PCI Express
Root
Hi Liviu,
Issue may not be only with SR-IOV resources.
I am not an expert with Linux PCI core. But i am trying to understand
how even for a non SR-IOV capable device's resource, gets a parent
associated with it.
When a PCI device driver calls pci_enable_device() which inturn calls
On 24 April 2014 02:02, Tanmay Inamdar wrote:
> Hello Sandeepa,
>
> On Tue, Apr 22, 2014 at 4:50 AM, Sandeepa Prabhu
> wrote:
>> On 22 April 2014 15:41, Liviu Dudau wrote:
>>> On Tue, Apr 22, 2014 at 09:58:28AM +0100, Sandeepa Prabhu wrote:
On 14 March 2014 21:04, Liviu Dudau wrote:
Hello Sandeepa,
On Tue, Apr 22, 2014 at 4:50 AM, Sandeepa Prabhu
wrote:
> On 22 April 2014 15:41, Liviu Dudau wrote:
>> On Tue, Apr 22, 2014 at 09:58:28AM +0100, Sandeepa Prabhu wrote:
>>> On 14 March 2014 21:04, Liviu Dudau wrote:
>>> > Hi,
>>> >
>>> > This patch adds support for PCI to
Hello Sandeepa,
On Tue, Apr 22, 2014 at 4:50 AM, Sandeepa Prabhu
sandeepa.pra...@linaro.org wrote:
On 22 April 2014 15:41, Liviu Dudau liviu.du...@arm.com wrote:
On Tue, Apr 22, 2014 at 09:58:28AM +0100, Sandeepa Prabhu wrote:
On 14 March 2014 21:04, Liviu Dudau liviu.du...@arm.com wrote:
On 24 April 2014 02:02, Tanmay Inamdar tinam...@apm.com wrote:
Hello Sandeepa,
On Tue, Apr 22, 2014 at 4:50 AM, Sandeepa Prabhu
sandeepa.pra...@linaro.org wrote:
On 22 April 2014 15:41, Liviu Dudau liviu.du...@arm.com wrote:
On Tue, Apr 22, 2014 at 09:58:28AM +0100, Sandeepa Prabhu wrote:
On Tue, Apr 22, 2014 at 12:50:40PM +0100, Sandeepa Prabhu wrote:
> On 22 April 2014 15:41, Liviu Dudau wrote:
> > On Tue, Apr 22, 2014 at 09:58:28AM +0100, Sandeepa Prabhu wrote:
> >> On 14 March 2014 21:04, Liviu Dudau wrote:
> >> > Hi,
> >> >
> >> > This patch adds support for PCI to AArch64.
On 22 April 2014 15:41, Liviu Dudau wrote:
> On Tue, Apr 22, 2014 at 09:58:28AM +0100, Sandeepa Prabhu wrote:
>> On 14 March 2014 21:04, Liviu Dudau wrote:
>> > Hi,
>> >
>> > This patch adds support for PCI to AArch64. It is based on my v7 patch
>> > that adds support for creating generic host
On Tue, Apr 22, 2014 at 09:58:28AM +0100, Sandeepa Prabhu wrote:
> On 14 March 2014 21:04, Liviu Dudau wrote:
> > Hi,
> >
> > This patch adds support for PCI to AArch64. It is based on my v7 patch
> > that adds support for creating generic host bridge structure from
> > device tree. With that in
On 14 March 2014 21:04, Liviu Dudau wrote:
> Hi,
>
> This patch adds support for PCI to AArch64. It is based on my v7 patch
> that adds support for creating generic host bridge structure from
> device tree. With that in place, I was able to boot a platform that
> has PCIe host bridge support and
On 14 March 2014 21:04, Liviu Dudau liviu.du...@arm.com wrote:
Hi,
This patch adds support for PCI to AArch64. It is based on my v7 patch
that adds support for creating generic host bridge structure from
device tree. With that in place, I was able to boot a platform that
has PCIe host bridge
On Tue, Apr 22, 2014 at 09:58:28AM +0100, Sandeepa Prabhu wrote:
On 14 March 2014 21:04, Liviu Dudau liviu.du...@arm.com wrote:
Hi,
This patch adds support for PCI to AArch64. It is based on my v7 patch
that adds support for creating generic host bridge structure from
device tree. With
On 22 April 2014 15:41, Liviu Dudau liviu.du...@arm.com wrote:
On Tue, Apr 22, 2014 at 09:58:28AM +0100, Sandeepa Prabhu wrote:
On 14 March 2014 21:04, Liviu Dudau liviu.du...@arm.com wrote:
Hi,
This patch adds support for PCI to AArch64. It is based on my v7 patch
that adds support for
On Tue, Apr 22, 2014 at 12:50:40PM +0100, Sandeepa Prabhu wrote:
On 22 April 2014 15:41, Liviu Dudau liviu.du...@arm.com wrote:
On Tue, Apr 22, 2014 at 09:58:28AM +0100, Sandeepa Prabhu wrote:
On 14 March 2014 21:04, Liviu Dudau liviu.du...@arm.com wrote:
Hi,
This patch adds support
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