Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support

The code is not calling CPUID in any performance critical path, only at initialization. So any discussion about saving a few instructions is a complete waste of time. -Andi

Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support

The code is not calling CPUID in any performance critical path, only at initialization. So any discussion about saving a few instructions is a complete waste of time. -Andi

Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support

On December 15, 2016 11:20:17 AM PST, Andi Kleen wrote: > >The code is not calling CPUID in any performance critical path, only >at initialization. So any discussion about saving a few instructions >is a complete waste of time. > >-Andi NB: the chief offender is Loadlin,

Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support

On December 15, 2016 11:20:17 AM PST, Andi Kleen wrote: > >The code is not calling CPUID in any performance critical path, only >at initialization. So any discussion about saving a few instructions >is a complete waste of time. > >-Andi NB: the chief offender is Loadlin, which is still used in

Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support

On December 15, 2016 11:20:17 AM PST, Andi Kleen wrote: > >The code is not calling CPUID in any performance critical path, only >at initialization. So any discussion about saving a few instructions >is a complete waste of time. > >-Andi Sort of. The BIOS boot code is very

Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support

On December 15, 2016 11:20:17 AM PST, Andi Kleen wrote: > >The code is not calling CPUID in any performance critical path, only >at initialization. So any discussion about saving a few instructions >is a complete waste of time. > >-Andi Sort of. The BIOS boot code is very space-constrained for

Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support

On Thu, Dec 15, 2016 at 09:52:12AM -0800, h...@zytor.com wrote: > This really is only worthwhile if it ends up producing better code, > but I doubt it. Nah, the most it does is drops those ifnc lines in there on newer gccs. They will appear only on gcc-4 and earlier and

Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support

On Thu, Dec 15, 2016 at 09:52:12AM -0800, h...@zytor.com wrote: > This really is only worthwhile if it ends up producing better code, > but I doubt it. Nah, the most it does is drops those ifnc lines in there on newer gccs. They will appear only on gcc-4 and earlier and

Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support

On December 15, 2016 6:39:44 AM PST, Borislav Petkov wrote: >On Wed, Dec 14, 2016 at 12:07:54AM +0100, Boris Petkov wrote: >> Thus I was thinking of adding a build-time check for the gcc version >> but that might turn out to be more code in the end than those ugly >> ifnc clauses.

Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support

On December 15, 2016 6:39:44 AM PST, Borislav Petkov wrote: >On Wed, Dec 14, 2016 at 12:07:54AM +0100, Boris Petkov wrote: >> Thus I was thinking of adding a build-time check for the gcc version >> but that might turn out to be more code in the end than those ugly >> ifnc clauses. > >IOW,

Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support

On Wed, Dec 14, 2016 at 12:07:54AM +0100, Boris Petkov wrote: > Thus I was thinking of adding a build-time check for the gcc version > but that might turn out to be more code in the end than those ugly > ifnc clauses. IOW, something like this. I did this just to try to see whether it is doable.

Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support

On Wed, Dec 14, 2016 at 12:07:54AM +0100, Boris Petkov wrote: > Thus I was thinking of adding a build-time check for the gcc version > but that might turn out to be more code in the end than those ugly > ifnc clauses. IOW, something like this. I did this just to try to see whether it is doable.

Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support

On December 13, 2016 11:44:06 PM GMT+01:00, "H. Peter Anvin" wrote: >When compiling with -fPIC gcc treats ebx as a "fixed register". A >fixed >register can't be spilled, and so a clobber of a fixed register is a >fatal error. > >Like it or not, it's how it works. > > -hpa

Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support

On December 13, 2016 11:44:06 PM GMT+01:00, "H. Peter Anvin" wrote: >When compiling with -fPIC gcc treats ebx as a "fixed register". A >fixed >register can't be spilled, and so a clobber of a fixed register is a >fatal error. > >Like it or not, it's how it works. > > -hpa In the meantime

Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support

On 12/09/16 07:32, Kirill A. Shutemov wrote: > > Something like this? > > diff --git a/arch/x86/boot/cpuflags.c b/arch/x86/boot/cpuflags.c > index 6687ab953257..366aad972025 100644 > --- a/arch/x86/boot/cpuflags.c > +++ b/arch/x86/boot/cpuflags.c > @@ -70,16 +70,22 @@ int has_eflag(unsigned long

Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support

On 12/09/16 07:32, Kirill A. Shutemov wrote: > > Something like this? > > diff --git a/arch/x86/boot/cpuflags.c b/arch/x86/boot/cpuflags.c > index 6687ab953257..366aad972025 100644 > --- a/arch/x86/boot/cpuflags.c > +++ b/arch/x86/boot/cpuflags.c > @@ -70,16 +70,22 @@ int has_eflag(unsigned long

Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support

On 12/08/16 12:20, Borislav Petkov wrote: > On Thu, Dec 08, 2016 at 12:08:53PM -0800, Linus Torvalds wrote: >> Especially since that's some of the ugliest inline asm ever due to the >> nasty BX handling. > > Yeah, about that: why doesn't gcc handle that for us like it would > handle a clobbered

Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support

On 12/08/16 12:20, Borislav Petkov wrote: > On Thu, Dec 08, 2016 at 12:08:53PM -0800, Linus Torvalds wrote: >> Especially since that's some of the ugliest inline asm ever due to the >> nasty BX handling. > > Yeah, about that: why doesn't gcc handle that for us like it would > handle a clobbered

Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support

On Fri, Dec 09, 2016 at 06:32:33PM +0300, Kirill A. Shutemov wrote: > Something like this? > > diff --git a/arch/x86/boot/cpuflags.c b/arch/x86/boot/cpuflags.c > index 6687ab953257..366aad972025 100644 > --- a/arch/x86/boot/cpuflags.c > +++ b/arch/x86/boot/cpuflags.c > @@ -70,16 +70,22 @@ int

Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support

On Fri, Dec 09, 2016 at 06:32:33PM +0300, Kirill A. Shutemov wrote: > Something like this? > > diff --git a/arch/x86/boot/cpuflags.c b/arch/x86/boot/cpuflags.c > index 6687ab953257..366aad972025 100644 > --- a/arch/x86/boot/cpuflags.c > +++ b/arch/x86/boot/cpuflags.c > @@ -70,16 +70,22 @@ int

Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support

On Thu, Dec 08, 2016 at 09:05:05PM +0100, Borislav Petkov wrote: > On Thu, Dec 08, 2016 at 07:21:37PM +0300, Kirill A. Shutemov wrote: > > 5-level paging support is required from hardware when compiled with > > CONFIG_X86_5LEVEL=y. We may implement runtime switch support later. > > > >

Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support

On Thu, Dec 08, 2016 at 09:05:05PM +0100, Borislav Petkov wrote: > On Thu, Dec 08, 2016 at 07:21:37PM +0300, Kirill A. Shutemov wrote: > > 5-level paging support is required from hardware when compiled with > > CONFIG_X86_5LEVEL=y. We may implement runtime switch support later. > > > >

Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support

On Thu, Dec 08, 2016 at 12:08:53PM -0800, Linus Torvalds wrote: > Especially since that's some of the ugliest inline asm ever due to the > nasty BX handling. Yeah, about that: why doesn't gcc handle that for us like it would handle a clobbered register? I mean, it *should* know that BX is live

Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support

On Thu, Dec 08, 2016 at 12:08:53PM -0800, Linus Torvalds wrote: > Especially since that's some of the ugliest inline asm ever due to the > nasty BX handling. Yeah, about that: why doesn't gcc handle that for us like it would handle a clobbered register? I mean, it *should* know that BX is live

Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support

On Thu, Dec 8, 2016 at 12:05 PM, Borislav Petkov wrote: > > The cpuid() in cpuflags.c doesn't zero ecx which, if we have to be > pedantic, it should do. It calls CPUID now with the ptr value of its 4th > on 64-bit and 3rd arg on 32-bit, respectively, IINM. In fact, just do a

Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support

On Thu, Dec 8, 2016 at 12:05 PM, Borislav Petkov wrote: > > The cpuid() in cpuflags.c doesn't zero ecx which, if we have to be > pedantic, it should do. It calls CPUID now with the ptr value of its 4th > on 64-bit and 3rd arg on 32-bit, respectively, IINM. In fact, just do a single

Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support

On Thu, Dec 08, 2016 at 07:21:37PM +0300, Kirill A. Shutemov wrote: > 5-level paging support is required from hardware when compiled with > CONFIG_X86_5LEVEL=y. We may implement runtime switch support later. > > Signed-off-by: Kirill A. Shutemov ... > diff

Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support

On Thu, Dec 08, 2016 at 07:21:37PM +0300, Kirill A. Shutemov wrote: > 5-level paging support is required from hardware when compiled with > CONFIG_X86_5LEVEL=y. We may implement runtime switch support later. > > Signed-off-by: Kirill A. Shutemov ... > diff --git a/arch/x86/boot/cpuflags.c