generating bus read cycles.

Hi all, Can anyone explain that, how can (void)*reg_addr; generate a read cycle on the bus. And Is there any source which clearly explains about setup of DMA and How to do DMA transfers. Regards, Krishna Chaitanya /* * The codec register read operation requires 3 read cycles on PXA250 in order

generating bus read cycles.

Hi all, Can anyone explain that, how can (void)*reg_addr; generate a read cycle on the bus. And Is there any source which clearly explains about setup of DMA and How to do DMA transfers. Regards, Krishna Chaitanya /* * The codec register read operation requires 3 read cycles on PXA250 in order