On 02/08/2018 10:29 PM, Sunil Kovvuri wrote:
On Fri, Feb 9, 2018 at 3:27 AM, Dean Nelson wrote:
On 02/08/2018 02:34 PM, David Miller wrote:
From: Dean Nelson
Date:
The Cavium thunder nicvf driver supports rx/tx rings of up to 65536
entries per.
...
Another way to solve this could have
On Fri, Feb 9, 2018 at 3:27 AM, Dean Nelson wrote:
> On 02/08/2018 02:34 PM, David Miller wrote:
>>
>> From: Dean Nelson
>> Date:
>>
>>> The Cavium thunder nicvf driver supports rx/tx rings of up to 65536
>>> entries per.
>>> The number of entires are stored in the q_len member of struct
>>> q_de
On 02/08/2018 02:34 PM, David Miller wrote:
From: Dean Nelson
Date:
The Cavium thunder nicvf driver supports rx/tx rings of up to 65536 entries per.
The number of entires are stored in the q_len member of struct q_desc_mem. The
problem is that q_len being a u16, results in 65536 becoming 0.
I
From: Dean Nelson
Date:
> The Cavium thunder nicvf driver supports rx/tx rings of up to 65536 entries
> per.
> The number of entires are stored in the q_len member of struct q_desc_mem. The
> problem is that q_len being a u16, results in 65536 becoming 0.
>
> In getting pointers to descriptors
The Cavium thunder nicvf driver supports rx/tx rings of up to 65536 entries per.
The number of entires are stored in the q_len member of struct q_desc_mem. The
problem is that q_len being a u16, results in 65536 becoming 0.
In getting pointers to descriptors in the rings, the driver uses q_len min
5 matches
Mail list logo