On Wed, 24 Oct 2007, Chuck Ebbert wrote:
> On 10/24/2007 05:26 PM, Mikhail Kshevetskiy wrote:
> >>>
> >>> I fill something wrong here.
> >>> Is it possible to reduce the amount of timer interrupts?
> >>> Is it possible to force enable C1,C2 and C3 states when c1e disabled?
> >>>
> >> How are you
On Wed, 24 Oct 2007, Chuck Ebbert wrote:
On 10/24/2007 05:26 PM, Mikhail Kshevetskiy wrote:
I fill something wrong here.
Is it possible to reduce the amount of timer interrupts?
Is it possible to force enable C1,C2 and C3 states when c1e disabled?
How are you disabling C1E?
2007/10/25, Chuck Ebbert <[EMAIL PROTECTED]>:
> On 10/24/2007 05:26 PM, Mikhail Kshevetskiy wrote:
> >>>
> >>> I fill something wrong here.
> >>> Is it possible to reduce the amount of timer interrupts?
> >>> Is it possible to force enable C1,C2 and C3 states when c1e disabled?
> >>>
> >> How are
On Wed, 24 Oct 2007, Chuck Ebbert wrote:
> On 10/24/2007 05:26 PM, Mikhail Kshevetskiy wrote:
> >>>
> >>> I fill something wrong here.
> >>> Is it possible to reduce the amount of timer interrupts?
> >>> Is it possible to force enable C1,C2 and C3 states when c1e disabled?
> >>>
> >> How are you
On 10/24/2007 05:26 PM, Mikhail Kshevetskiy wrote:
>>>
>>> I fill something wrong here.
>>> Is it possible to reduce the amount of timer interrupts?
>>> Is it possible to force enable C1,C2 and C3 states when c1e disabled?
>>>
>> How are you disabling C1E?
>>
>>
> dirty hack, i just follow the
2007/10/19, Chuck Ebbert <[EMAIL PROTECTED]>:
> On 10/01/2007 02:15 AM, Mikhail Kshevetskiy wrote:
> > Hello,
> >
> > I have ASUS F3T notebook with dualcore AMD processor. It has c1e feature
> > enabled. I test linux-2.6.23-rc8-hrt1 kernel. Everything is work (thanks
> > to lapic disable patch),
2007/10/19, Chuck Ebbert [EMAIL PROTECTED]:
On 10/01/2007 02:15 AM, Mikhail Kshevetskiy wrote:
Hello,
I have ASUS F3T notebook with dualcore AMD processor. It has c1e feature
enabled. I test linux-2.6.23-rc8-hrt1 kernel. Everything is work (thanks
to lapic disable patch), but i have to
On 10/24/2007 05:26 PM, Mikhail Kshevetskiy wrote:
I fill something wrong here.
Is it possible to reduce the amount of timer interrupts?
Is it possible to force enable C1,C2 and C3 states when c1e disabled?
How are you disabling C1E?
dirty hack, i just follow the FreeBSD way and clear C1e
On Wed, 24 Oct 2007, Chuck Ebbert wrote:
On 10/24/2007 05:26 PM, Mikhail Kshevetskiy wrote:
I fill something wrong here.
Is it possible to reduce the amount of timer interrupts?
Is it possible to force enable C1,C2 and C3 states when c1e disabled?
How are you disabling C1E?
2007/10/25, Chuck Ebbert [EMAIL PROTECTED]:
On 10/24/2007 05:26 PM, Mikhail Kshevetskiy wrote:
I fill something wrong here.
Is it possible to reduce the amount of timer interrupts?
Is it possible to force enable C1,C2 and C3 states when c1e disabled?
How are you disabling C1E?
On 10/01/2007 02:15 AM, Mikhail Kshevetskiy wrote:
> Hello,
>
> I have ASUS F3T notebook with dualcore AMD processor. It has c1e feature
> enabled. I test linux-2.6.23-rc8-hrt1 kernel. Everything is work (thanks
> to lapic disable patch), but i have to many processor interrupts per
> seconds
On 10/01/2007 02:15 AM, Mikhail Kshevetskiy wrote:
Hello,
I have ASUS F3T notebook with dualcore AMD processor. It has c1e feature
enabled. I test linux-2.6.23-rc8-hrt1 kernel. Everything is work (thanks
to lapic disable patch), but i have to many processor interrupts per
seconds (about
On 10/01/2007 11:21 AM, Andi Kleen wrote:
>
> Also I'm not sure but I suspect non Intel HPETs have less than
> three timers. Certainly they generally miss the 64bitness.
>
nVidia C51/MCP51 chipset, AMD Turion X2:
hpet0: 3 32-bit timers, 2500 Hz
-
To unsubscribe from this list: send the
On Mon, 1 Oct 2007, Andi Kleen wrote:
> > So if the
> > number of hpet channels is greater/equal to the number of possible
> > CPUs it's perfectly fine and does not need IPI at all.
>
> That is only a stop gap then. I don't see this being
> generally true in the future. e.g. Intel announced SMT
> So if the
> number of hpet channels is greater/equal to the number of possible
> CPUs it's perfectly fine and does not need IPI at all.
That is only a stop gap then. I don't see this being
generally true in the future. e.g. Intel announced SMT will be soon
back so even a standard dual core
On Mon, 1 Oct 2007, Andi Kleen wrote:
> > There is work in progress on a patch, which allows to utilize the hpet
> > timers as per cpu timers. This should solve the problem. Be patient.
>
> Given that e.g. ICH8 only has 3 HPET timers that seems doubtful
> except for the special case of
2007/10/1, Andi Kleen <[EMAIL PROTECTED]>:
> > No, it boot and work normally. The only thing i bother, is the additional
>
> Ok you want an additional feature; not a bug fixed.
>
> Please make that always clear.
>
> > 260 timer interrupts per seconds.
> > Here is short result:
> >
> > c1e enabled:
2007/10/1, Thomas Gleixner <[EMAIL PROTECTED]>:
> On Mon, 1 Oct 2007, Mikhail Kshevetskiy wrote:
> > No, it boot and work normally. The only thing i bother, is the
> > additional 260 timer interrupts per seconds.
> > Here is short result:
> >
> > c1e enabled:
> > -- power consumption about 23
> There is work in progress on a patch, which allows to utilize the hpet
> timers as per cpu timers. This should solve the problem. Be patient.
Given that e.g. ICH8 only has 3 HPET timers that seems doubtful
except for the special case of single-socket non hyper threaded dual core.
You'll
On Mon, 1 Oct 2007, Mikhail Kshevetskiy wrote:
> No, it boot and work normally. The only thing i bother, is the
> additional 260 timer interrupts per seconds.
> Here is short result:
>
> c1e enabled:
> -- power consumption about 23 watts
> -- there is only C1 power state enabled
> -- there
On Mon, 1 Oct 2007 15:09:53 +0200
> There is normally a threshold above which you don't save significantly
> more power by doing less timer interrupts. You can test this
> by doing the CONFIG_HZ=100 above.
however the point you're describing tends to more be around 25ms to
50ms HZ=100 is
> No, it boot and work normally. The only thing i bother, is the additional
Ok you want an additional feature; not a bug fixed.
Please make that always clear.
> 260 timer interrupts per seconds.
> Here is short result:
>
> c1e enabled:
> -- power consumption about 23 watts
> -- there is
01 Oct 2007 11:33:48 +0200, Andi Kleen <[EMAIL PROTECTED]>:
> Mikhail Kshevetskiy <[EMAIL PROTECTED]> writes:
> >
> > The same situation can be observed for linux-2.6.22.
>
> You're saying 2.6.22/x86-64 without any patches doesn't boot out of the box
> with C1E enabled? If yes what are the exact
Mikhail Kshevetskiy <[EMAIL PROTECTED]> writes:
>
> The same situation can be observed for linux-2.6.22.
You're saying 2.6.22/x86-64 without any patches doesn't boot out of the box
with C1E enabled? If yes what are the exact symptoms?
-Andi
-
To unsubscribe from this list: send the line
Mikhail Kshevetskiy [EMAIL PROTECTED] writes:
The same situation can be observed for linux-2.6.22.
You're saying 2.6.22/x86-64 without any patches doesn't boot out of the box
with C1E enabled? If yes what are the exact symptoms?
-Andi
-
To unsubscribe from this list: send the line
01 Oct 2007 11:33:48 +0200, Andi Kleen [EMAIL PROTECTED]:
Mikhail Kshevetskiy [EMAIL PROTECTED] writes:
The same situation can be observed for linux-2.6.22.
You're saying 2.6.22/x86-64 without any patches doesn't boot out of the box
with C1E enabled? If yes what are the exact symptoms?
No, it boot and work normally. The only thing i bother, is the additional
Ok you want an additional feature; not a bug fixed.
Please make that always clear.
260 timer interrupts per seconds.
Here is short result:
c1e enabled:
-- power consumption about 23 watts
-- there is only C1
On Mon, 1 Oct 2007 15:09:53 +0200
There is normally a threshold above which you don't save significantly
more power by doing less timer interrupts. You can test this
by doing the CONFIG_HZ=100 above.
however the point you're describing tends to more be around 25ms to
50ms HZ=100 is only
On Mon, 1 Oct 2007, Mikhail Kshevetskiy wrote:
No, it boot and work normally. The only thing i bother, is the
additional 260 timer interrupts per seconds.
Here is short result:
c1e enabled:
-- power consumption about 23 watts
-- there is only C1 power state enabled
-- there are
There is work in progress on a patch, which allows to utilize the hpet
timers as per cpu timers. This should solve the problem. Be patient.
Given that e.g. ICH8 only has 3 HPET timers that seems doubtful
except for the special case of single-socket non hyper threaded dual core.
You'll probably
2007/10/1, Thomas Gleixner [EMAIL PROTECTED]:
On Mon, 1 Oct 2007, Mikhail Kshevetskiy wrote:
No, it boot and work normally. The only thing i bother, is the
additional 260 timer interrupts per seconds.
Here is short result:
c1e enabled:
-- power consumption about 23 watts
--
2007/10/1, Andi Kleen [EMAIL PROTECTED]:
No, it boot and work normally. The only thing i bother, is the additional
Ok you want an additional feature; not a bug fixed.
Please make that always clear.
260 timer interrupts per seconds.
Here is short result:
c1e enabled:
-- power
On Mon, 1 Oct 2007, Andi Kleen wrote:
There is work in progress on a patch, which allows to utilize the hpet
timers as per cpu timers. This should solve the problem. Be patient.
Given that e.g. ICH8 only has 3 HPET timers that seems doubtful
except for the special case of single-socket non
So if the
number of hpet channels is greater/equal to the number of possible
CPUs it's perfectly fine and does not need IPI at all.
That is only a stop gap then. I don't see this being
generally true in the future. e.g. Intel announced SMT will be soon
back so even a standard dual core would
On Mon, 1 Oct 2007, Andi Kleen wrote:
So if the
number of hpet channels is greater/equal to the number of possible
CPUs it's perfectly fine and does not need IPI at all.
That is only a stop gap then. I don't see this being
generally true in the future. e.g. Intel announced SMT will be
On 10/01/2007 11:21 AM, Andi Kleen wrote:
Also I'm not sure but I suspect non Intel HPETs have less than
three timers. Certainly they generally miss the 64bitness.
nVidia C51/MCP51 chipset, AMD Turion X2:
hpet0: 3 32-bit timers, 2500 Hz
-
To unsubscribe from this list: send the line
36 matches
Mail list logo
