[PATCH v2 12/22] ARM: LPAE: define ARCH_LOW_ADDRESS_LIMIT for bootmem

This patch adds an architecture defined override for ARCH_LOW_ADDRESS_LIMIT. On PAE systems, the absence of this override causes bootmem to incorrectly limit itself to 32-bit addressable physical memory. Signed-off-by: Cyril Chemparathy cy...@ti.com Signed-off-by: Vitaly Andrianov vita...@ti.com

[PATCH v2 10/22] ARM: LPAE: use phys_addr_t in switch_mm()

This patch modifies the switch_mm() processor functions to use phys_addr_t. On LPAE systems, we now honor the upper 32-bits of the physical address that is being passed in, and program these into TTBR as expected. Signed-off-by: Cyril Chemparathy cy...@ti.com Signed-off-by: Vitaly Andrianov

[RFC v2 20/22] ARM: keystone: introducing TI Keystone platform

Texas Instruments Keystone family of multicore devices now includes an upcoming slew of Cortex A15 based devices. This patch adds basic definitions for a new Keystone sub-architecture in ARM. Subsequent patches in this series will extend support to include SMP and take advantage of the large

[PATCH v2 05/22] ARM: LPAE: support 64-bit virt_to_phys patching

This patch adds support for 64-bit physical addresses in virt_to_phys() patching. This does not do real 64-bit add/sub, but instead patches in the upper 32-bits of the phys_offset directly into the output of virt_to_phys. There is no corresponding change on the phys_to_virt() side, because

[PATCH v2 19/22] ARM: recreate kernel mappings in early_paging_init()

This patch adds a step in the init sequence, in order to recreate the kernel code/data page table mappings prior to full paging initialization. This is necessary on LPAE systems that run out of a physical address space outside the 4G limit. On these systems, this implementation provides a

[PATCH v2 15/22] ARM: mm: use physical addresses in highmem sanity checks

This patch modifies the highmem sanity checking code to use physical addresses instead. This change eliminates the wrap-around problems associated with the original virtual address based checks, and this simplifies the code a bit. The one constraint imposed here is that low physical memory must

[PATCH v2 01/22] ARM: add mechanism for late code patching

The original phys_to_virt/virt_to_phys patching implementation relied on early patching prior to MMU initialization. On PAE systems running out of 4G address space, this would have entailed an additional round of patching after switching over to the high address space. The approach implemented

[PATCH v2 04/22] ARM: LPAE: use phys_addr_t on virt -- phys conversion

This patch fixes up the types used when converting back and forth between physical and virtual addresses. Signed-off-by: Vitaly Andrianov vita...@ti.com Signed-off-by: Cyril Chemparathy cy...@ti.com --- arch/arm/include/asm/memory.h | 26 ++ 1 file changed, 18

[PATCH v2 13/22] ARM: LPAE: factor out T1SZ and TTBR1 computations

This patch moves the TTBR1 offset calculation and the T1SZ calculation out of the TTB setup assembly code. This should not affect functionality in any way, but improves code readability as well as readability of subsequent patches in this series. Signed-off-by: Cyril Chemparathy cy...@ti.com

[PATCH v2 07/22] ARM: LPAE: use phys_addr_t in alloc_init_pud()

From: Vitaly Andrianov vita...@ti.com This patch fixes the alloc_init_pud() function to use phys_addr_t instead of unsigned long when passing in the phys argument. This is an extension to commit 97092e0c56830457af0639f6bd904537a150ea4a (ARM: pgtable: use phys_addr_t for physical addresses),

[PATCH v2 03/22] ARM: use late patch framework for phys-virt patching

This patch replaces the original physical offset patching implementation with one that uses the newly added patching framework. In the process, we now unconditionally initialize the __pv_phys_offset and __pv_offset globals in the head.S code. Signed-off-by: Cyril Chemparathy cy...@ti.com ---

[PATCH v2 00/22] Introducing the TI Keystone platform

This series is a follow on to the series posted earlier (archived at [1]). Patches 01/22 .. 09/22 of this series have been pretty intensively reviewed; thanks to all who helped. We've modified per feedback, and these should be in reasonable shape. Patches 10/22 .. 19/22 of this series have not

[RFC v2 22/22] ARM: keystone: add switch over to high physical address range

Keystone platforms have their physical memory mapped at an address outside the 32-bit physical range. A Keystone machine with 16G of RAM would find its memory at 0x08 - 0x0b. For boot purposes, the interconnect supports a limited alias of some of this memory within the 32-bit

[PATCH v2 16/22] ARM: mm: cleanup checks for membank overlap with vmalloc area

On Keystone platforms, physical memory is entirely outside the 32-bit addressible range. Therefore, the (bank-start ULONG_MAX) check below marks the entire system memory as highmem, and this causes unpleasentness all over. This patch eliminates the extra bank start check (against ULONG_MAX) by

[PATCH v2 11/22] ARM: LPAE: use 64-bit accessors for TTBR registers

This patch adds TTBR accessor macros, and modifies cpu_get_pgd() and the LPAE version of cpu_set_reserved_ttbr0() to use these instead. In the process, we also fix these functions to correctly handle cases where the physical address lies beyond the 4G limit of 32-bit addressing. Signed-off-by:

[PATCH v2 02/22] ARM: add self test for runtime patch mechanism

This patch adds basic sanity tests to ensure that the instruction patching results in valid instruction encodings. This is done by verifying the output of the patch process against a vector of assembler generated instructions at init time. Signed-off-by: Cyril Chemparathy cy...@ti.com ---

[PATCH v2 08/22] ARM: LPAE: use phys_addr_t in free_memmap()

From: Vitaly Andrianov vita...@ti.com The free_memmap() was mistakenly using unsigned long type to represent physical addresses. This breaks on PAE systems where memory could be placed above the 32-bit addressible limit. This patch fixes this function to properly use phys_addr_t instead.

[PATCH v2 18/22] ARM: add virt_to_idmap for interconnect aliasing

From: Vitaly Andrianov vita...@ti.com On some PAE systems (e.g. TI Keystone), memory is above the 32-bit addressible limit, and the interconnect provides an aliased view of parts of physical memory in the 32-bit addressible space. This alias is strictly for boot time usage, and is not otherwise

[PATCH v2 06/22] ARM: LPAE: use signed arithmetic for mask definitions

This patch applies to PAGE_MASK, PMD_MASK, and PGDIR_MASK, where forcing unsigned long math truncates the mask at the 32-bits. This clearly does bad things on PAE systems. This patch fixes this problem by defining these masks as signed quantities. We then rely on sign extension to do the right

[RFC v2 21/22] ARM: keystone: enable SMP on Keystone machines

This patch adds basic SMP support for Keystone machines. Nothing very fancy here, just enough to get 4 CPUs booted up. This does not include support for hotplug, etc. Signed-off-by: Vitaly Andrianov vita...@ti.com Signed-off-by: Cyril Chemparathy cy...@ti.com --- arch/arm/Kconfig

[PATCH v2 09/22] ARM: LPAE: use phys_addr_t for initrd location and size

From: Vitaly Andrianov vita...@ti.com This patch fixes the initrd setup code to use phys_addr_t instead of assuming 32-bit addressing. Without this we cannot boot on systems where initrd is located above the 4G physical address limit. Signed-off-by: Vitaly Andrianov vita...@ti.com

[PATCH 2/3 V1] block: Fix not tracing all device plug-operation.

If process handled two or more devices,there will not be trace some devices plug-operation. V0--V1 Fix a bug when insert a req to plug-list which already had the same request-queue, it should used list_add not list_add_tail. Signed-off-by: Jianpeng Ma majianp...@gmail.com Signed-off-by: Jens

Re: [PATCH] [PATCH V4]Extcon: adc_jack: adc-jack driver to support 3.5 pi or simliar devices

Hello Jonathan, Please refer the latest patch. Thanks, On Fri, 2012-08-10 at 22:01 +0100, Jonathan Cameron wrote: On 08/08/2012 02:04 AM, anish kumar wrote: From: anish kumar anish198519851...@gmail.com External connector devices that decides connection information based on ADC values

Re: [PATCH 1/6] regulator: core: Add checking n_voltages if using list_voltage() to read voltage regulators

2012/8/10 Mark Brown broo...@opensource.wolfsonmicro.com: On Fri, Aug 10, 2012 at 08:27:32PM +0800, Axel Lin wrote: 2012/8/10 Mark Brown broo...@opensource.wolfsonmicro.com: We should be failing to register these regulators in the first place, or at least complaining extremely loudly about

Re: [PATCH 2/2] ARM: local timers: add timer support using IO mapped register

On 8/10/2012 5:58 PM, Rohit Vaswani wrote: The current arch_timer only support accessing through CP15 interface. Add support for ARM processors that only support IO mapped register interface It looks like this patch attempts to address both (a) non-percpu arch timers, and (b) memory mapped

[RFC PATCH][RESEND] Fusion MPT: disable pci device when mpt map resoures failed

when probe a pci device, first we enable it, and disable it when some error happened in the following process, because the power state of the device is set to D0, and if MSI is disabled, we will allocate irq and register gsi for this device in the enable process. In function

[BUGFIX PATCH][RESEND] kexec iosapic: kexec oops when iosapic was removed

Hi, all We are working on a node hot-plug project, and IOAPIC is one of these devices to be removed. but after IOSAPIC was removed, we use kexec to start a new kernel, oops happended. I reviewed the code and find out: iosapic_remove iosapic_free memset(iosapic_lists[index], 0,

Re: [PATCH v5 05/12] KVM: reorganize hva_to_pfn

On 08/11/2012 01:51 AM, Marcelo Tosatti wrote: On Tue, Aug 07, 2012 at 05:51:05PM +0800, Xiao Guangrong wrote: We do too many things in hva_to_pfn, this patch reorganize the code, let it be better readable Signed-off-by: Xiao Guangrong xiaoguangr...@linux.vnet.ibm.com ---

Re: [PATCH v5 11/12] KVM: x86: introduce set_mmio_exit_info

On 08/11/2012 02:03 AM, Marcelo Tosatti wrote: int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr, void *val, unsigned int bytes, struct x86_exception *exception, @@ -3870,14 +3881,10 @@ int emulator_read_write(struct

Re: [PATCH v5 00/12] KVM: introduce readonly memslot

On 08/11/2012 02:14 AM, Marcelo Tosatti wrote: On Tue, Aug 07, 2012 at 05:47:15PM +0800, Xiao Guangrong wrote: Changelog: - introduce KVM_PFN_ERR_RO_FAULT instead of dummy page - introduce KVM_HVA_ERR_BAD and optimize error hva indicators The test case can be found at:

Re: Upgraded from 3.4 to 3.5.1 kernel: machine does not boot

On Fri, Aug 10, 2012 at 7:07 PM, Justin Piszcz Hi, Found the root cause, the 3.5.1 kernel cannot mount my ext4 filesystem (60TB). The 3.4 kernel works fine. This is proven by commenting out the filesystem in /etc/fstab with 3.5.1, and all is OK. -- Hi again, I tested with

Re: xtensa port maintenance

Chris Zankel wrote: I have set up a tree on github for now, and will work close with Max to get his changes to Stephen's linux-next tree and eventually Linus' tree. I think it's fine to add Max as a second maintainer [...] Thanks for helping! Pete Delaney wrote: I'm afraid that doing it

Re: [PATCH v2 06/11] memcg: kmem controller infrastructure

On Thu, Aug 09 2012, Glauber Costa wrote: This patch introduces infrastructure for tracking kernel memory pages to a given memcg. This will happen whenever the caller includes the flag __GFP_KMEMCG flag, and the task belong to a memcg other than the root. In memcontrol.h those functions are

Re: [PATCH v5 02/12] dm: Use bioset's front_pad for dm_rq_clone_bio_info

Hi Kent, Tejun On 9 August 2012 09:57, Kent Overstreet koverstr...@google.com wrote: Also, how was this tested? Well, AFAICT the only request based dm target is multipath, and from the documentation I've seen it doesn't appear to work without multipath hardware, or at least I haven't seen it

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