On 2014-01-06 17:22, Mark Rutland wrote:
Hi,
Apologies for the late reply, I wasn't able to access my mail much over
the Christmas break.
The patch is already applied to both the next branch of Felipe Balbi's
usb/next branch and merged from there into Greg Kroah-Hartman's
usb/usb-next
On Tue, Jan 7, 2014 at 5:53 PM, Joerg Roedel j...@8bytes.org wrote:
On Tue, Jan 07, 2014 at 11:47:26PM +0100, Joerg Roedel wrote:
The DRM driver for MSM depends on symbols from the MSM
IOMMU driver. Add this dependency to the Kconfig file.
Fixes this comile error:
Kernel:
Am Dienstag, 7. Januar 2014, 16:51:37 schrieb Alan Cox:
modem status command, but this DV bit is not set. With this patch the
modem
and the whole mux is working fine. Another way makeing all this work is
setting the carrier_raised function to NULL. The tty code assumes that
On Wed, Jan 08, 2014 at 12:45:34PM +, Peter Zijlstra wrote:
On Wed, Jan 08, 2014 at 12:35:34PM +, Morten Rasmussen wrote:
Currently we detect overload by sg.nr_running = sg.capacity, which can
be very misleading because while a cpu might have a task running 'now'
it might be 99%
On Tue, 24 Dec 2013 01:18:03 +0100, Peter Wu wrote:
On Monday 23 December 2013 10:37:21 Alex Williamson wrote:
On Mon, 2013-12-23 at 16:49 +0100, Peter Wu wrote:
[..]
There is still one thing I do not fully understand, how should
dev_set_drvdata and dev_get_drvdata be used? For the
On Tue, Jan 07, 2014 at 07:12:58PM +0100, Oleg Nesterov wrote:
Hello.
I tried to audit the users of thread_group_empty() (we need
to change it) and found rcu_my_thread_group_empty() which
looks wrong.
The patches look simple, but I am not sure it is fine to use
rcu_lock_acquire()
The erratum-773769 occurs on Arm Coretex-A15 (rev r2p0),
when L2 Data Ram latency is set to 4 cycles or more; or
when ACP is in use, or with L2 Data RAM slice configured.
Therefore, the effective latency as calculated in Table 7-2 of
Cotex-A15 (rev r2p0) trm should be 3 cycles or less.
On
are available in the git repository at:
git://git.linaro.org/people/ljones/mfd.git tags/ib-asoc-3.14.2
for you to fetch changes up to 9146070089cca0fa5c396f1a4d0b96d675004c04:
Pulled, thanks.
drivers/mfd/twl-core.c | 190
On Wed, Jan 08, 2014 at 01:27:39PM +, Morten Rasmussen wrote:
On Wed, Jan 08, 2014 at 12:45:34PM +, Peter Zijlstra wrote:
On Wed, Jan 08, 2014 at 12:35:34PM +, Morten Rasmussen wrote:
Currently we detect overload by sg.nr_running = sg.capacity, which can
be very misleading
On Wed, Jan 08, 2014 at 01:04:07PM +, Peter Zijlstra wrote:
On Wed, Jan 08, 2014 at 12:52:28PM +, Morten Rasmussen wrote:
If I remember correctly, Alex used the rq runnable_avg_sum (in rq-avg)
for this. It is the most obvious choice, but it takes ages to reach
100%.
#define
On Tuesday, January 07, 2014 09:27:17 PM David E. Box wrote:
On Wed, Jan 08, 2014 at 01:11:22AM +0100, Rafael J. Wysocki wrote:
Well, I personally think that this code should go into arch/x86/ as library
code
needed to access IOSF Sideband on some platforms.
I don't disagree. However
On Wed, Jan 08, 2014 at 08:23:49AM -0500, Rob Clark wrote:
On Tue, Jan 7, 2014 at 5:53 PM, Joerg Roedel j...@8bytes.org wrote:
On Tue, Jan 07, 2014 at 11:47:26PM +0100, Joerg Roedel wrote:
The DRM driver for MSM depends on symbols from the MSM
IOMMU driver. Add this dependency to the
On 2013-12-19 10:23, Sascha Hauer wrote:
No need to allocate the framebuffer from the atomic pool, we are not
in interrupt context. Adding GFP_KERNEL to the framebuffer allocation
allows to use the much bigger CMA pool to allocate the framebuffer.
Signed-off-by: Sascha Hauer
On Wednesday 08 January 2014 13:51:17 Thierry Reding wrote:
When devices are probed from the device tree, any interrupts that they
reference are resolved at device creation time. This causes problems if
the interrupt provider hasn't been registered yet at that time, which
results in the
On Mon, Jan 06, 2014 at 01:40:51PM -0700, Stephen Warren wrote:
On 12/24/2013 06:32 AM, Peter De Schrijver wrote:
[...]
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
+ efuse@7000F800 {
fuse might be a better node name; efuse is presumably the name of
the
Am Wed, 8 Jan 2014 12:08:04 +0800
schrieb Jianguo Wu wujian...@huawei.com:
For some archs, like arm64, would use memblock.memory after system
booting, so we can not simply released to the buddy allocator, maybe
need !defined(CONFIG_ARCH_DISCARD_MEMBLOCK).
Oh, I see. I have added some ifdefs
On Tue, 2014-01-07 at 16:25 +0100, Florian Westphal wrote:
Eric Dumazet eric.duma...@gmail.com wrote:
diff --git a/net/netfilter/nf_conntrack_core.c
b/net/netfilter/nf_conntrack_core.c
index 43549eb..7a34bb2 100644
--- a/net/netfilter/nf_conntrack_core.c
+++
On Wed, Jan 08, 2014 at 01:23:04PM +, Andreas Larsson wrote:
On 2014-01-06 17:22, Mark Rutland wrote:
Hi,
Apologies for the late reply, I wasn't able to access my mail much over
the Christmas break.
The patch is already applied to both the next branch of Felipe Balbi's
usb/next
On Wed, 2014-01-08 at 08:57 +0100, Alexander Gordeev wrote:
Signed-off-by: Alexander Gordeev agord...@redhat.com
---
drivers/vfio/pci/vfio_pci_intrs.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/vfio/pci/vfio_pci_intrs.c
On Wed, Jan 08, 2014 at 01:32:57PM +, Peter Zijlstra wrote:
On Wed, Jan 08, 2014 at 01:27:39PM +, Morten Rasmussen wrote:
On Wed, Jan 08, 2014 at 12:45:34PM +, Peter Zijlstra wrote:
On Wed, Jan 08, 2014 at 12:35:34PM +, Morten Rasmussen wrote:
Currently we detect
On Wed, 2014-01-08 at 17:17 +0400, Andrey Vagin wrote:
Lets look at destroy_conntrack:
hlist_nulls_del_rcu(ct-tuplehash[IP_CT_DIR_ORIGINAL].hnnode);
...
nf_conntrack_free(ct)
kmem_cache_free(net-ct.nf_conntrack_cachep, ct);
net-ct.nf_conntrack_cachep is created with
Version 4:
Tended to Brian's previous review comments
- Checkpatch acceptance
- MODULE_DEVICE_TABLE() name slip correction
- Timeout issue(s) resolved
- Potential infinite loop mitigated
- Code clarity suggests heeded
- Duplication with MTD core code removed
-
This is a new driver. It's used to communicate with a special type of
optimised Serial Flash Controller called the FSM. The FSM uses a subset
of the SPI protocol to communicate with supported NOR-Flash devices.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
drivers/mtd/devices/Kconfig |
It's important for us to determine which device was used to boot from in
order to make some correct decisions surrounding Power Management. On
each of the platforms which support the FSM this is communicated via
a set of mode pins held in the system configuration area. This patch
determine the
Supply a lookup table of all the devices we intend to support. This table
is used to store device information such as; a human readable device name,
their JEDEC ID (plus the extended version), sector size and amount, a bit
store of a device's capabilities, its maximum running frequency and
When we write data to the FIFO the FSM Controller subsequently writes
that data out to the Serial Flash chip.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
drivers/mtd/devices/st_spi_fsm.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/mtd/devices/st_spi_fsm.c
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
drivers/mtd/devices/st_spi_fsm.c | 36
1 file changed, 36 insertions(+)
diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c
index 5f291dc..1b0fa67 100644
---
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
drivers/mtd/devices/st_spi_fsm.c | 82 +++-
1 file changed, 81 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c
index 1b0fa67..92071fa 100644
---
The N25Qxxx Serial Flash devices required different sequence
configurations depending on whether they're running in 24bit (3Byte)
or 32bit (4Byte) mode. We provide those here.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
drivers/mtd/devices/st_spi_fsm.c | 53
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
drivers/mtd/devices/st_spi_fsm.c | 47
1 file changed, 43 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c
index 88017d8..ddfff35 100644
---
On 08/01/14 02:12, Eric Dumazet wrote:
On Wed, 2014-01-08 at 00:10 +, Zoltan Kiss wrote:
+ if (skb_shinfo(skb)-frag_list) {
+ nskb = skb_shinfo(skb)-frag_list;
+ xenvif_fill_frags(vif, nskb, INVALID_PENDING_IDX);
+
When a read is issued by userspace the MFD framework calls back into
the driver to conduct the actual command issue and data extraction.
Here we provide the routines which do exactly that.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
drivers/mtd/devices/st_spi_fsm.c | 99
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
drivers/mtd/devices/st_spi_fsm.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c
index eac23df..5f291dc 100644
--- a/drivers/mtd/devices/st_spi_fsm.c
When an erase is requested by userspace the MTD framework calls back
into the driver to conduct the actual command issue. Here we provide the
routines which do exactly that. We can choose to either do an entire chip
erase or by sector.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
When a write is requested by userspace the MFD framework calls back
into the driver to conduct the actual command issue and data send.
Here we provide the routines which do exactly that.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
drivers/mtd/devices/st_spi_fsm.c | 150
Until now the dynamically configurable message sequences for read, write
and enable 32bit addressing have been global. Brian makes a good point
why this should not be the case. If there are ever two FSM's located on
the same platform, we could be potentially introducing a race condition
on
Here we add the necessary device nodes required for successful device
probing and Pinctrl setup for the FSM.
Acked-by: Srinivas Kandagatla srinivas.kandaga...@st.com
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
arch/arm/boot/dts/stih416-b2105.dts| 14 ++
This patch allows us to prepare some of the message sequences which will
be required to talk to the S25FLxxx family of Serial Flash devices. It
also allows us to do some required extra operations after any busy wait
failures.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
When we write data to the Serial Flash chip we'll wait a predetermined
period of time before giving up. During that period of time we poll the
status register until completion.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
drivers/mtd/devices/st_spi_fsm.c | 65
Most Serial Flash chips support 24bit addressing as a default but more
recent incarnations can support 32bit. Based on information provided
though platform specific data and capabilities we can determine whether
or not our current chip can. This patch provides a means to setup the
FSM message
Most chips require a predefined set of FSM message sequences for read,
write and erase operations. This patch provides a way to set them up,
which it will do so if a chip specific initialisation routine isn't
been provided.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
On Wed, 2014-01-08 at 13:49 +, Zoltan Kiss wrote:
On 08/01/14 02:12, Eric Dumazet wrote:
On Wed, 2014-01-08 at 00:10 +, Zoltan Kiss wrote:
+ if (skb_shinfo(skb)-frag_list) {
+ nskb = skb_shinfo(skb)-frag_list;
+ xenvif_fill_frags(vif,
The FSM Serial Flash Controller is driven by issuing a standard set of
register writes we call a message sequence. This patch supplies a method
to prepare the message sequence responsible for updating a chip's VCR.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
Hi Andrew,
the whole thread started here: http://lkml.org/lkml/2014/1/6/217
I guess it makes sense to revert part of the already merged commit with
the following patch. If the BUG_ON triggers again then we should rather
find out why page_address_in_vma fails on anon_vma or f_mapping checks
and not
Adding LKML to the list as this -stable snifftest has identified an
upstream regression.
On Wed, Jan 08, 2014 at 10:43:40AM +, Mel Gorman wrote:
On Tue, Jan 07, 2014 at 08:30:12PM +, Mel Gorman wrote:
On Tue, Jan 07, 2014 at 10:54:40AM -0800, Greg KH wrote:
On Tue, Jan 07, 2014 at
On Wed 08-01-14 21:10:29, Bob Liu wrote:
[...]
From 2d61421f26a3b63b4670d71b7adc67e2191b6157 Mon Sep 17 00:00:00 2001
From: Michal Hocko mho...@suse.cz
Date: Wed, 8 Jan 2014 10:57:41 +0100
Subject: [PATCH] mm: new_vma_page cannot see NULL vma for hugetlb pages
11c731e81bb0
The FSM Serial Flash Controller is driven by issuing a standard set of
register writes we call a message sequence. This patch supplies a method
to prepare read/write FSM message sequence(s) based on chip capability
and configuration.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
In the FSM driver we handle chip differences by providing the possibility
of calling back into a chip specific initialisation routine. In this patch
we provide one for the N25Qxxx series, which endeavours to setup things
like the read, write and erase sequences, as they differ from the
default. We
Message sequences can vary depending on how many pads (lines) are
required to address the chip (mode dummy), how many data pads (lines)
are required to write out to the chip which will determine speed
amongst other things which are detailed by the SFDP specification. We
are able to use multiple
Cc: devicet...@vger.kernel.org
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
Documentation/devicetree/bindings/mtd/st-fsm.txt | 26
1 file changed, 26 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/st-fsm.txt
diff --git
The FSM hardware works by setting a predetermined sequence of register
writes. Rather than open coding them inside each functional block we're
going to define them in a series of formatted 'sequence structures'.
This patch provides the framework which shall be used for every action.
Firstly we search for our preference read/write configuration based on a
given chip's capabilities. Then we actually set up the message sequence
accordingly.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
drivers/mtd/devices/st_spi_fsm.c | 17 +
1 file changed, 17
Based on information we can obtain though platform specific data and/or
chip capabilities we are able to determine whether or not we can handle
a SoC reset or not. To find out why this is important please read the
comment provided in the patch.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
Once we start supporting devices it will be handy go detect them
dynamically. This will be done using the chip's unique JEDEC ID. This
patch allows us to extract a device's JEDEC ID using the a predefined
FSM register write sequence.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
When invoked the driver will attempt to read any available data from
the FSM's data register. Any data collected from this FIFO would have
originated from the flash chip.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
drivers/mtd/devices/st_spi_fsm.c | 26 ++
1 file
On 01/07/2014 02:00 PM, Shuah Khan wrote:
On 01/07/2014 12:16 PM, Greg Kroah-Hartman wrote:
On Tue, Jan 07, 2014 at 12:07:14PM -0700, Shuah Khan wrote:
On 01/06/2014 03:36 PM, Greg Kroah-Hartman wrote:
This is the start of the stable review cycle for the 3.12.7 release.
There are 144 patches
On 2013-12-15 22:40, Olaf Hering wrote:
Documentation/fb/modedb.txt states that video=option should be
considered a global option. But video_setup and fb_get_options are not
coded that way. Instead its required to boot with video=driver:option to
set a given option in drvier. This is
All supported platforms are able to pass specific configurations via
the Device Tree on boot. Here we add a function which is to be called
during the probing process which will extract them, or make other
assumptions based on capabilities provided.
Signed-off-by: Lee Jones lee.jo...@linaro.org
Hi James,
On 7 January 2014 22:57, James Smart james.sm...@emulex.com wrote:
Sergey,
The Thor chipset is a bit old - a 4Gig adapter. Most of our performance
improvements, including parallelization, have gone into the 8G and 16G
adapters. But you still should have seen significantly beyond
The FSM Serial Flash Controller is driven by issuing a standard set of
register writes we call a message sequence. This patch supplies a method
to prepare the message sequence responsible for setting 32bit addressing
mode on the Flash chip.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
JEDEC have helped to standardise a great deal of the commands which
can be issued to a Serial Flash devices. Many of the Serial Flash
Discoverable Parameters (SFDP) commands are generic across devices.
This patch provides a shared point where these commands can be
defined.
Suggested-by: Mark
Here we provide a means to traverse though all supplied FSM message
sequence configurations and pick one based on our chip's capabilities.
The first one we match will be the preferred one, as they are
presented in order of preference.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
The FSM Serial Flash Controller is driven by issuing a standard set of
register writes we call a message sequence. This patch supplies a method
to prepare the message sequence responsible for erasing a single sector.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
Flash chip commands are issued using a set of predefined opcodes. These
are mostly the same for all flash devices, but do differ on occasion.
This patch supplies the majority of the key ones which will be used in
this driver.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
Using previously added infrastructure we can now extract a device's JEDEC
ID, compare it to a list of known and supported devices and make assumptions
based on known characteristics of a given chip.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
drivers/mtd/devices/st_spi_fsm.c | 27
This patch uses default values to initialise a connected flash chip. This
includes; a device soft reset, setting of a safe working frequency, a
switch into Fast Sequencing Mode, configuring of timing data and a purge
of the FIFO.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
On Tue, Jan 07, 2014 at 08:37:23PM +0200, Sergey Meirovich wrote:
Actually my initial report (14.67Mb/sec 3755.41 Requests/sec) was about ext4
However I have tried XFS as well. It was a bit slower than ext4 on all
occasions.
I wasn't trying to say XFS fixes your problem, but that we could
On 2014-01-07 22:25, Ivaylo Dimitrov wrote:
Besides compiling DSS driver with DEBUG enabled and providing the log
(yeah, I know I should've done it already and have the logs included in
this mail, but... :) ), is there anything else I can do to find the
culprit for those errors.
You could
On Wed, Jan 08, 2014 at 02:17:13AM +0100, Jan Kara wrote:
Well, I was specifically worried about i_mutex locking. In particular:
Before we report appending IO completion we need to update i_size.
To update i_size we need to grab i_mutex.
Now this is unpleasant because inode_dio_wait()
Here we provide the FSM's register addresses, register bit names/offsets
and some commands which will prove useful as we start bulk the FMS's
driver out with functionality.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
drivers/mtd/devices/st_spi_fsm.c | 172
Eric Dumazet eric.duma...@gmail.com wrote:
This will also set up a null-binding when no matching SNAT/DNAT/MASQERUADE
rule existed.
The manipulations of the skb-nfct-ext nat area are performed without
a lock. Concurrent access is supposedly impossible as the conntrack
should not
On 1/8/14, Long Wind longwind2...@gmail.com wrote:
I have asked Debian users, they don't seem to know
kernel 2.4/2.6 fail to boot on my PC
probably because it can't detect my memory
so I have to tell kernel memory map
the following is copied from kernel-parameters.txt:
memmap=exactmap
On Wed, 8 Jan 2014 22:03:22 +0900
Kusanagi Kouichi sl...@ac.auone-net.jp wrote:
make O=foo fails with following error:
.../Makefile:221: features.mk: No such file or directory
make[1]: *** No rule to make target `features.mk'. Stop.
make: *** [sub-make] Error 2
Signed-off-by: Kusanagi
On 08/01/14 01:29, David Miller wrote:
+static inline int tx_dealloc_work_todo(struct xenvif *vif)
Make this return bool.
Done, also in the last patch.
+ wait_event_interruptible(vif-dealloc_wq,
+ tx_dealloc_work_todo(vif) ||
+
On Tuesday 07 January 2014 11:06 PM, Sekhar Nori wrote:
On Tuesday 07 January 2014 11:22 PM, Santosh Shilimkar wrote:
Sekhar,
On Tuesday 24 December 2013 06:41 AM, Grygorii Strashko wrote:
This series is intended to update Davinci GPIO driver and reuse
it for Keystone SoCs, because Keystone
On 08/01/14 13:54, Eric Dumazet wrote:
On Wed, 2014-01-08 at 13:49 +, Zoltan Kiss wrote:
On 08/01/14 02:12, Eric Dumazet wrote:
On Wed, 2014-01-08 at 00:10 +, Zoltan Kiss wrote:
+ if (skb_shinfo(skb)-frag_list) {
+ nskb =
On Wed, Jan 08, 2014 at 05:56:21AM -0800, Guenter Roeck wrote:
On 01/07/2014 02:00 PM, Shuah Khan wrote:
On 01/07/2014 12:16 PM, Greg Kroah-Hartman wrote:
On Tue, Jan 07, 2014 at 12:07:14PM -0700, Shuah Khan wrote:
On 01/06/2014 03:36 PM, Greg Kroah-Hartman wrote:
This is the start of the
On 01/07/2014 08:59 PM, Peter Zijlstra wrote:
On Tue, Jan 07, 2014 at 12:55:18PM +, Morten Rasmussen wrote:
My understanding is that should_we_balance() decides which cpu is
eligible for doing the load balancing for a given domain (and the
domains above). That is, only one cpu in a group
Pavel Machek wrote:
I'm not nacking this, just stating my view.
And I believe Andrew clearly stated his view, on the very topic you
asked him on.
I believe Andrew's view:
On Sat, 2013-12-28 at 12:08 -0800, Andrew Morton wrote:
On Sat, 28 Dec 2013 11:53:25 -0800 Joe
On Tue, Dec 24, 2013 at 12:39:45AM +, Stephen Boyd wrote:
From: Rohit Vaswani rvasw...@codeaurora.org
Scorpion and Krait don't use the spin-table enable-method.
Instead they rely on mmio register accesses to enable power and
clocks to bring CPUs out of reset. Document their
Arnd, Olof, Kevin,
A little cleanup pull-request for 3.14 that goes on top of the previous
AT91 cleanup material.
The thing to note from this pull-request is the beginning of board file removal
thank to the conversion to DT. We are still waiting for more feedback from
board maintainer to
On Tue, Dec 24, 2013 at 12:39:46AM +, Stephen Boyd wrote:
The kpss acc binding describes the clock, reset, and power domain
controller for a Krait CPU.
Cc: devicet...@vger.kernel.org
Signed-off-by: Stephen Boyd sb...@codeaurora.org
---
.../devicetree/bindings/arm/msm/qcom,kpss-acc.txt
Add the sunxi NAND Flash Controller dt bindings documentation.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
.../devicetree/bindings/mtd/sunxi-nand.txt | 71
1 file changed, 71 insertions(+)
create mode 100644
**Sorry for the duplicate mail, I forgot to force plain-text mode in
gmail or the mailing list rejects the mails. Sigh, I need to buy my
own email server at this rate to even deal with the mailing lists and
proper etiquette (no quoteS) :(
Ah, I forgot there was that third mode(no dma and no pdc).
Define the NAND pinctrl configs.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm/boot/dts/sun7i-a20.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index c00a577..34b1948
Add a function to retrieve NAND timings from a given DT node.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/of/of_mtd.c| 47 +++
include/linux/of_mtd.h |9 +
2 files changed, 56 insertions(+)
diff --git
Hello,
This series add the sunxi NFC support with up to 8 NAND chip connected.
I'm still in the early stages drivers development and some key features are
missing, but it's usable (I tested it on the cubietruck board).
Here's what's missing:
- HW ECC support
- DMA support
- HW randomization
Define a struct containing the standard NAND timings as described in NAND
datasheets.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
include/linux/mtd/nand.h | 44
1 file changed, 44 insertions(+)
diff --git a/include/linux/mtd/nand.h
The Hynix nand flashes store their ECC requirements in byte 4 of its id
(returned on READ ID command).
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/mtd/nand/nand_base.c | 37 +
1 file changed, 37 insertions(+)
diff --git
On Wed, Jan 08, 2014 at 02:25:41PM +, Mark Rutland wrote:
On Tue, Dec 24, 2013 at 12:39:46AM +, Stephen Boyd wrote:
The kpss acc binding describes the clock, reset, and power domain
controller for a Krait CPU.
Cc: devicet...@vger.kernel.org
Signed-off-by: Stephen Boyd
On Tue, Dec 24, 2013 at 12:39:47AM +, Stephen Boyd wrote:
The saw2 binding describes the SPM/AVS wrapper hardware used to
control the regulator supplying voltage to the Krait CPUs.
Cc: devicet...@vger.kernel.org
Signed-off-by: Stephen Boyd sb...@codeaurora.org
---
On Wed, Jan 08, 2014 at 01:33:11PM +, Vivek Gautam wrote:
The erratum-773769 occurs on Arm Coretex-A15 (rev r2p0),
when L2 Data Ram latency is set to 4 cycles or more; or
when ACP is in use, or with L2 Data RAM slice configured.
Therefore, the effective latency as calculated in Table 7-2
Add a NAND timing properties to NAND dt doc.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
Documentation/devicetree/bindings/mtd/nand.txt | 34
1 file changed, 34 insertions(+)
diff --git a/Documentation/devicetree/bindings/mtd/nand.txt
Add the sunxi NAND Flash Controller driver.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/mtd/nand/Kconfig |6 +
drivers/mtd/nand/Makefile|1 +
drivers/mtd/nand/sunxi_nfc.c | 700 ++
3 files changed, 707 insertions(+)
As the cover page wrote, this was *not* meant to be a good code
because I wanted to get design feedback. I have asked that before,
too, and you claimed to send some code representing the idea. I have
just done that. I find it weird to get design feedback _after_ doing
all the coding.
Anyway, if
On Tue, Jan 7, 2014 at 2:11 PM, Linus Walleij linus.wall...@linaro.org wrote:
On Mon, Dec 23, 2013 at 5:08 PM, Laszlo Papp lp...@kde.org wrote:
MAX6650/MAX6651 chip is a multi-function device with I2C busses. The
chip includes fan-speed regulators and monitors, GPIO, and alarm.
This patch is
On Wed, Jan 08, 2014 at 11:21:21AM +0800, Jason Wang wrote:
On 01/07/2014 09:17 PM, Neil Horman wrote:
On Tue, Jan 07, 2014 at 11:42:24AM +0800, Jason Wang wrote:
On 01/06/2014 08:42 PM, Neil Horman wrote:
On Mon, Jan 06, 2014 at 11:21:07AM +0800, Jason Wang wrote:
Currently, the tx queue
On 01/08/2014 03:32 PM, Hannes Reinecke wrote:
On 12/24/2013 04:35 AM, Chen Gang wrote:
On 12/23/2013 02:51 PM, Nicholas A. Bellinger wrote:
On Sun, 2013-12-22 at 17:17 +0800, Chen Gang wrote:
On 12/22/2013 10:56 AM, Nicholas A. Bellinger wrote:
Hi Chen,
On Sat, 2013-12-21 at 10:08 +0800,
On Wed, Jan 08, 2014 at 09:24:22AM +0800, Dave Young wrote:
On 01/07/14 at 09:37am, Vivek Goyal wrote:
On Tue, Jan 07, 2014 at 10:34:06AM +0800, Dave Young wrote:
Hi, all
I have a question in mind: can we copy and prepare kexec kernel while
normal booting?
Just like below
Hi Christoph,
On 8 January 2014 16:03, Christoph Hellwig h...@infradead.org wrote:
On Tue, Jan 07, 2014 at 08:37:23PM +0200, Sergey Meirovich wrote:
Actually my initial report (14.67Mb/sec 3755.41 Requests/sec) was about ext4
However I have tried XFS as well. It was a bit slower than ext4 on
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