On Thu, Sep 25, 2014 at 07:07:31PM +0300, Octavian Purdila wrote:
> +static void dln2_rx_transfer(struct dln2_dev *dln2, struct urb *urb,
> + u16 handle, u16 rx_slot)
> +{
> + struct dln2_mod_rx_slots *rxs = >mod_rx_slots[handle];
> + struct dln2_rx_context *rxc;
Commit-ID: 0e6d3112a4e95d55cf6dca88f298d5f4b8f29bd1
Gitweb: http://git.kernel.org/tip/0e6d3112a4e95d55cf6dca88f298d5f4b8f29bd1
Author: Ben Hutchings
AuthorDate: Sun, 7 Sep 2014 21:05:05 +0100
Committer: Thomas Gleixner
CommitDate: Wed, 8 Oct 2014 11:17:42 +0200
x86: Reject x32
Commit-ID: 2dee5c43da3a981489a4f18972827139afcbee82
Gitweb: http://git.kernel.org/tip/2dee5c43da3a981489a4f18972827139afcbee82
Author: Andi Kleen
AuthorDate: Wed, 24 Sep 2014 06:32:19 +0200
Committer: Thomas Gleixner
CommitDate: Wed, 8 Oct 2014 11:18:49 +0200
x86: Fix section conflict
On Wed, Oct 08, 2014 at 04:06:12AM +0100, zhangzhiqiang wrote:
> hi all,
>
>
> ref-cycles event is specially to Intel core, but can still used in arm
> architecture
> with the wrong return value with 3.10 stable. for instance:
>
> perf stat -e
These probably should have been sent to devicet...@vger.kernel.org. Use
the maintainer.pl script.
regards,
dan carpenter
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To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
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On Wed, Oct 8, 2014 at 10:05 AM, Lee Jones wrote:
> With the influx of new same-chip devices, I think the MFD subsystem is
> fast becoming overloaded. I think all of the PMIC handling should in
> fact either live in Regulators or have its own subsystem.
You have a valid point, and it's been
2014-10-06 23:22 GMT+02:00 Lee Jones :
> On Thu, 25 Sep 2014, Johannes Pointner wrote:
>
>> Add documentation for compatible property of subnodes.
>>
>> Signed-off-by: Johannes Pointner
>> ---
>> Documentation/devicetree/bindings/regulator/tps65217.txt | 7 ++-
>>
We could use setns to join the current ns,
which did a lot of unnecessary work.
This patch will check this senario and
return 0 directly.
Signed-off-by: Chen Hanxiao
---
kernel/nsproxy.c | 28
1 file changed, 28 insertions(+)
diff --git a/kernel/nsproxy.c
On Wed, Oct 08, 2014 at 08:44:28AM +0100, Robert Richter wrote:
> Liviu, Bjorn,
>
> On 30.09.14 17:54:31, Liviu Dudau wrote:
> > On Tue, Sep 30, 2014 at 05:18:05PM +0100, Bjorn Helgaas wrote:
> > > OK, I rebuilt pci/host-generic from scratch. It consists of your v13
> > > patches + Arnd's build
On Wed, Oct 08, 2014 at 08:54:58AM +, David Laight wrote:
> Hmmm... in that case you may not want the compiler to convert the bit value
> to a 'bool' at all.
>
> Passing 'id_entry->driver_data' through (that doesn't look like a field name
> for
> 'quirk flags) would generate better code.
>
On Tue, 2014-10-07 at 10:26 -0700, Dmitry Torokhov wrote:
> Hi Ivan,
>
> On Tue, Oct 07, 2014 at 12:50:46PM +0300, Ivan T. Ivanov wrote:
> > @@ -527,10 +538,55 @@ static int pmic8xxx_kp_probe(struct platform_device
> > *pdev)
> >
> > +
> > + kp->row_hold = devm_regmap_field_alloc(kp->dev,
From: Hannes Frederic Sowa
> I think David's concern was whether if 0 == false in all situations. It
> is pretty clear that static memory is initialized to 0.
I'm not 100% sure about that.
static pointers may be required to be initialised to NULL.
If NULL isn't the 'all 0 bit pattern' then the
Hi,
David Laight wrote:
> From: Lothar Waßmann
> > David Laight wrote:
> > > From: Eric Dumazet
> > > > On Tue, 2014-10-07 at 15:19 +0200, Lothar Wamann wrote:
> > > > > commit 1b7bde6d659d ("net: fec: implement rx_copybreak to improve rx
> > > > > performance")
> > > > > introduced a regression
I ran into a problem on a Sandybridge i5-2500s whilst measuring the
performance of GTT write-combining access. I found subsequent runs were
about 10-40x slower than the first. For example,
igt/gem_gtt_speed:
Time to read 16k through a GTT map: 325.285µs
Time to write 16k through a
Hi,
Apologies for taking so long - I've added this into the -nmw tree now.
Thanks,
Steve.
On 03/10/14 19:15, Fabian Frederick wrote:
use macro definition
Signed-off-by: Fabian Frederick
---
fs/gfs2/glock.c | 4 ++--
fs/gfs2/glops.c | 2 +-
fs/gfs2/trans.c | 2 +-
3 files changed, 4
From: Ian Munsie
__spu_trap_data_seg() currently contains code to determine the VSID and ESID
required for a particular EA and mm struct.
This code is generically useful for other co-processors. This moves the code of
the cell platform so it can be used by other powerpc code. It also adds 1TB
From: Ian Munsie
Currently spu_handle_mm_fault() is in the cell platform.
This code is generically useful for other non-cell co-processors on powerpc.
This patch moves this function out of the cell platform into arch/powerpc/mm so
that others may use it.
Signed-off-by: Ian Munsie
From: Ian Munsie
This moves spu_flush_all_slbs() into a generic call copro_flush_all_slbs().
This will be useful when we add cxl which also needs a similar SLB flush call.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/copro.h | 6 ++
From: Ian Munsie
This adds hooks into the core powerpc mm code for cxl.
The core powerpc code sometimes uses local tlbie. Unfortunately this won't
work with the current cxl driver as it relies on snooping tlbie broadcasts.
The cxl hardware can have TLB entries invalidated via MMIO but this is
On 08/10/14 08:48, Chen, Alvin wrote:
Now, we have another board which can support 4 slave spi per master, but not
only Galileo. Since that board is not public, after discussing with team, we
decide to make the
upstream code to support '1'.
I will change it back to
.num_chipselect = 1,
Hi
From: Ian Munsie
This adds a header file for use by userspace programs wanting to interact with
the kernel cxl driver. It defines structs and magic numbers required for
userspace to interact with devices in /dev/cxl/afuM.N.
Further documentation on this interface is added in a subsequent patch
The parent should be spdif_8ch_pre not spdif_8ch_src, which doesn't
exist and looks to be a typo. The TRM also confirms this.
Signed-off-by: Sonny Rao
---
drivers/clk/rockchip/clk-rk3288.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
From: Ian Munsie
This adds the base cxl support that cannot be built as a module. Specifically
it adds the cxl callbacks that are called from the core powerpc mm code which
must always exist irrespective of if the cxl module is loaded or not. This is
similar to how cell works with
From: Ian Munsie
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
drivers/misc/cxl/Kconfig | 17 +
drivers/misc/cxl/Makefile | 2 ++
2 files changed, 19 insertions(+)
diff --git a/drivers/misc/cxl/Kconfig b/drivers/misc/cxl/Kconfig
index 5cdd319..a990b39 100644
From: Ian Munsie
This is the core of the cxl driver.
It adds support for using cxl cards in the powernv environment only (ie POWER8
bare metal). It allows access to cxl accelerators by userspace using the
/dev/cxl/afuM.N char devices.
The kernel driver has no knowledge of the function
On Tue, Oct 7, 2014 at 10:28 PM, Doug Anderson wrote:
> For pinctrl the "default" state is applied to pins before the driver's
> probe function is called. This is normally a sensible thing to do,
> but in some cases can cause problems. That's because the pins will
> change state before the
From: Ian Munsie
This documentation gives an overview of the hardware architecture, userspace
APIs via /dev/cxl/afuM.N and the syfs files. It also adds a MAINTAINERS file
entry for cxl.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
Documentation/ABI/testing/sysfs-class-cxl |
From: Ian Munsie
This new header adds callbacks and structs needed by the rest of the kernel to
hook into the cxl infrastructure.
This adds the cxl_ctx_in_use() function for use in the mm code to see if any
cxl contexts are currently in use. This is used by the tlbie() to determine if
it can do
From: Ian Munsie
This adds a new function hash_page_mm() based on the existing hash_page().
This version allows any struct mm to be passed in, rather than assuming
current. This is useful for servicing co-processor faults which are not in the
context of the current running process.
We need to
From: Ian Munsie
This adds a number of functions for allocating IRQs under powernv PCIe for cxl.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/pnv-pci.h| 31 ++
arch/powerpc/platforms/powernv/pci-ioda.c | 154 ++
On Wed, Oct 08, 2014 at 10:03:57AM +0900, Jingoo Han wrote:
> On Tuesday, October 07, 2014 2:01 PM, Gyungoh Yoo wrote:
> >
>
> If possible, please add more detailed commit message for this patch.
>
> > Signed-off-by: Gyungoh Yoo
> > ---
> > drivers/video/backlight/Kconfig | 10 +
From: Ian Munsie
Some of the MSI IRQ code in pnv_pci_ioda_msi_setup() is generically useful so
split it out.
This will be used by some of the cxl PCIe code later.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/platforms/powernv/pci-ioda.c | 42
On Wed, Oct 08, 2014 at 09:57:43AM +0800, Axel Lin wrote:
> The module version is unlikely to be updated, use kernel version should be
> enough.
>
> Signed-off-by: Axel Lin
> ---
> Hi Gyungoh,
> Seems you have added MODULE_VERSION for the sky81452 serial patches.
> Do you really need that and
From: Ian Munsie
Export mmu_kernel_ssize and mmu_linear_psize. These are needed by the cxl
driver which has it's own MMU. To setup the MMU cxl needs access to these.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/mm/hash_utils_64.c | 2 ++
1 file changed, 2
From: Ian Munsie
Currently msi_bitmap_alloc_hwirqs() will round up any IRQ allocation requests
to the nearest power of 2. eg. ask for 5 IRQs and you'll get 8. This wastes a
lot of IRQs which can be a scarce resource.
For cxl we may require multiple IRQs for every context that is attached to the
From: Sergei Shtylyov
> On 10/07/2014 05:19 PM, Lothar Wamann wrote:
>
> > commit 1b7bde6d659d ("net: fec: implement rx_copybreak to improve rx
> > performance")
> > introduced a regression for i.MX28. The swap_buffer() function doing
> > the endian conversion of the received data on i.MX28 may
This is the latest version of the cxl driver. Change log below:
v4:
- Updates based on comments from mpe (offline and online).
- Refactor the sstp lock to be an entry lock.
- Fixed error paths on new status_mutex in start_work
- added some missing include files
- moved associating pid/mm
From: Ian Munsie
This adds the OPAL call to change a PHB into cxl mode.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/opal.h| 2 ++
arch/powerpc/platforms/powernv/opal-wrappers.S | 1 +
2 files changed, 3 insertions(+)
diff --git
On Tue, Oct 07, 2014 at 01:52:21PM +0100, Mark Brown wrote:
> On Tue, Oct 07, 2014 at 02:11:07PM +0900, Gyungoh Yoo wrote:
> > Signed-off-by: Gyungoh Yoo
>
> Several problems here:
>
> - I don't have patches 1-6 or the cover letter for this series - what
>are the dependencies?
> - I can't
As of now, a miscdevice driver has to provide an implementation of
the open() file operation if it wants to have misc_open() assign a
pointer to struct miscdevice to file->private_data for other file
operations to use (given the user calls open()).
This leads to situations where a miscdevice
Hi Morten,
Sorry for late jumping in.
The problem seems to be self-evident. But for the implementation to be
equally attractive it needs to account for every freq change for every task,
or anything less than that makes it less attractive.
But this should be very hard. Intel Architecture has
On 07.10.14 16:01:49, Liviu Dudau wrote:
> On Tue, Oct 07, 2014 at 03:27:44PM +0100, Robert Richter wrote:
> > On 24.09.14 18:06:04, Arnd Bergmann wrote:
> > > > + compatible = "cavium,thunder-pcie";
> > > > + device_type = "pci";
> > > > + msi-parent =
From: Lothar Waßmann
> David Laight wrote:
> > From: Eric Dumazet
> > > On Tue, 2014-10-07 at 15:19 +0200, Lothar Wamann wrote:
> > > > commit 1b7bde6d659d ("net: fec: implement rx_copybreak to improve rx
> > > > performance")
> > > > introduced a regression for i.MX28. The swap_buffer() function
Hi all,
recently Linux 3.14 has been released and I find the networking has
added udp gro and vxlan gro funtion, then I use the redhat 7.0(there is also
add this funtion)
to test, I use kernel vxlan module and create a vxlan device then attach the
device to ovs bridge , the configure
Hello Doug,
On 10/07/2014 07:48 PM, Doug Anderson wrote:
>
> I don't have all the right patches to test this right now. Hopefully
> you can point me at what we're using right now. I'd expect that this
> will need the patches that Chanwoo and Javier are working on, so I've
> added them to this.
On Mon, 29 Sep 2014, Bjorn Andersson wrote:
> Driver for the Resource Power Manager (RPM) found in Qualcomm 8974 based
> devices.
> The driver exposes resources that child drivers can operate on; to
> implementing regulator, clock and bus frequency drivers.
>
> Signed-off-by: Bjorn Andersson
>
On Tue, Oct 07, 2014 at 11:26:11PM -0700, Mike Turquette wrote:
> +struct capacity_ops {
> + unsigned long (*get_capacity)(int cpu);
> + spinlock_t lock;
> +};
Yeah, fail there. Ops vectors should not contain serialization, that
simply doesn't work. It means you cannot switch the entire
On Wed, Oct 08, 2014 at 03:43:11PM +0900, Yasuaki Ishimatsu wrote:
> diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
> index bfa3c86..fb7dc3f 100644
> --- a/kernel/sched/fair.c
> +++ b/kernel/sched/fair.c
> @@ -1496,18 +1496,26 @@ static void update_task_scan_period(struct
> task_struct
From: Jaiprakash Singh
IFC IO accressor are set at run time based
on IFC IP registers endianness.IFC node in
DTS file contains information about
endianness.
Signed-off-by: Jaiprakash Singh
---
.../bindings/memory-controllers/fsl/ifc.txt|2 +
drivers/memory/fsl_ifc.c
On 8 October 2014 13:41, Thomas Petazzoni
wrote:
> On Wed, 8 Oct 2014 13:24:30 +0530, Viresh Kumar wrote:
>> On 8 October 2014 13:18, Mike Turquette wrote:
>> > This series is partially in response to a discussion around DT bindings
>> > for CPUfreq drivers [0], but it is also needed for
Hi Oussama,
On 10/07/2014 02:02 PM, Oussama Ghorbel wrote:
> The USB OTG port does not work since v3.16 on omap platform.
> This is a regression introduced by the commit
> eb82a3d846fa (phy: omap-usb2: Balance pm_runtime_enable() on probe failure
> and remove).
> This because the call to
Commit-ID: 3f63572187f5ae6a0a9e5ebee88b57e6f71c3cd4
Gitweb: http://git.kernel.org/tip/3f63572187f5ae6a0a9e5ebee88b57e6f71c3cd4
Author: Jan Beulich
AuthorDate: Wed, 24 Sep 2014 08:37:00 +0100
Committer: Thomas Gleixner
CommitDate: Wed, 8 Oct 2014 10:05:49 +0200
x86: Improve
On Tue, Oct 07, 2014 at 10:27:00PM -0700, Scott Branden wrote:
> +static void __init bcm_cygnus_init(void)
> +{
> + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
> +
> + l2x0_of_init(0, ~0UL);
Please don't explicitly call l2x0 initialisation. Instead, set the
Commit-ID: aece118e487a744eafcdd0c77fe32b55ee2092a1
Gitweb: http://git.kernel.org/tip/aece118e487a744eafcdd0c77fe32b55ee2092a1
Author: Bryan O'Donoghue
AuthorDate: Tue, 7 Oct 2014 01:19:49 +0100
Committer: Thomas Gleixner
CommitDate: Wed, 8 Oct 2014 10:07:46 +0200
x86: Add
Commit-ID: 2075244f9b871f18a007935c73d2ab49d4fb43e0
Gitweb: http://git.kernel.org/tip/2075244f9b871f18a007935c73d2ab49d4fb43e0
Author: Bryan O'Donoghue
AuthorDate: Tue, 7 Oct 2014 01:19:48 +0100
Committer: Thomas Gleixner
CommitDate: Wed, 8 Oct 2014 10:07:46 +0200
x86: Quark: Comment
Dear Viresh Kumar,
On Wed, 8 Oct 2014 13:24:30 +0530, Viresh Kumar wrote:
> On 8 October 2014 13:18, Mike Turquette wrote:
> > This series is partially in response to a discussion around DT bindings
> > for CPUfreq drivers [0], but it is also needed for on-going work to
> > integrate CPUfreq
Commit-ID: 82ef36449d311a29b20f82fdce0de856057fa691
Gitweb: http://git.kernel.org/tip/82ef36449d311a29b20f82fdce0de856057fa691
Author: Jan Beulich
AuthorDate: Wed, 24 Sep 2014 08:41:30 +0100
Committer: Thomas Gleixner
CommitDate: Wed, 8 Oct 2014 10:05:50 +0200
x86: Unwind-annotate
Commit-ID: 5f1d919a8ca15f450c749227bc5e2e18f3cbfdb4
Gitweb: http://git.kernel.org/tip/5f1d919a8ca15f450c749227bc5e2e18f3cbfdb4
Author: Jan Beulich
AuthorDate: Wed, 24 Sep 2014 08:40:14 +0100
Committer: Thomas Gleixner
CommitDate: Wed, 8 Oct 2014 10:05:49 +0200
x86: Improve
On Wed, Oct 08, 2014 at 12:37:40PM +0530, Preeti U Murthy wrote:
> There are two masks associated with cpusets. The cpus/mems_allowed
> and effective_cpus/mems. On the legacy hierarchy both these masks
> are consistent with each other. This is the intersection of their
> value and the currently
To all those CC'ed,
> The Baytrail-T platform firmware has defined two customized operation
> regions for PMIC chip Crystal Cove - one is for power resource handling
> and one is for thermal: sensor temperature reporting, trip point setting,
> etc. This patch adds support for them on top of the
On Tue, Oct 07, 2014 at 09:50:46PM +0200, Oleg Nesterov wrote:
> And note that another caller of task_preempt_count(), set_cpu(), is
> fine but it doesn't really need this helper.
>
> And afaics we do not need ->saved_preempt_count at all, the trivial
> patch below makes it unnecessary, we can
We can get into an infinite loop if the I2S_CLR register fails to
clear due to a missing break statement, so add that.
Signed-off-by: Sonny Rao
---
sound/soc/rockchip/rockchip_i2s.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/sound/soc/rockchip/rockchip_i2s.c
There are two SPI controllers exported by PCI subsystem for Intel Quark X1000.
The SPI memory mapped I/O registers supported by Quark are different from
the current implementation, and Quark only supports the registers of 'SSCR0',
'SSCR1', 'SSSR', 'SSDR', and 'DDS_RATE'. This patch is to enable
There are several registers for SPI, and the registers of 'SSCR0' and 'SSCR1'
are accessed frequently. This path is to introduce helper functions to
simplify the accessing of 'SSCR0' and 'SSCR1'.
Reviewed-by: Andy Shevchenko
Acked-by: Mika Westerberg
Signed-off-by: Weike Chen
---
Hi,
Intel Quark X1000 consists of two SPI controllers which can be PCI enumerated.
SPI-PXA2XX PCI layer doesn't support it. Thus, we add support for Intel Quark
X1000 SPI as well.
---
v3:
[PATCH 1/2]
* Improve the commit message.
* A couple of minor fixes.
[PATCH 2/2]
* Set '.num_chipselect' to
On Tuesday 07 October 2014 22:27:03 Scott Branden wrote:
> From: Jonathan Richardson
>
> Tested-by: Jonathan Richardson
> Reviewed-by: JD (Jiandong) Zheng
> Signed-off-by: Scott Branden
Do you actually need a separate defconfig?
If possible, just add your drivers to multi_v7_defconfig,
On Tuesday 07 October 2014 22:27:02 Scott Branden wrote:
> diff --git a/Documentation/devicetree/bindings/arm/cygnus.txt
> b/Documentation/devicetree/bindings/arm/cygnus.txt
> new file mode 100644
> index 000..a210377
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/cygnus.txt
>
YOU HAVE WON $2,100,000.00.doc
Description: MS-Word document
On Tuesday 07 October 2014 22:27:00 Scott Branden wrote:
> From: Jonathan Richardson
>
> Adds initial support for the Cygnus SoC based on Broadcom’s iProc series.
>
> Reviewed-by: Ray Jui
> Reviewed-by: Desmond Liu
> Reviewed-by: JD (Jiandong) Zheng
> Tested-by: Jonathan Richardson
>
On 8 October 2014 13:18, Mike Turquette wrote:
> This series is partially in response to a discussion around DT bindings
> for CPUfreq drivers [0], but it is also needed for on-going work to
> integrate CPUfreq with the scheduler. In particular a scheduler-driven
> cpu frequency scaling policy
bus_add_device() should be called before devtmpfs_create_node(), so when
userland application opens device from devtmpfs, it wouldn't get ENODEV
from kernel, because device_add() wasn't completed.
Signed-off-by: Sergey Klyaus
---
drivers/base/core.c | 40
Hi Linus,
here is the bulk of GPIO changes for the v3.18 cycle.
When I tested to pull this into your tree I found two conflicts that
also appeared in linux-next, one in the qualcomm driver which
is trivial and one in the gpiolib.c which is also kind of trivial (lower
hunk is the correct one).
Hi Linus,
The following changes since commit 2ce7598c9a453e0acd0e07be7be3f5eb39608ebd:
Linux 3.17-rc4 (2014-09-07 16:09:43 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/geert/linux-m68k.git for-linus
for you to fetch changes up to
The CPUfreq core does not differentiate between .target & .target_index
callbacks that may sleep or block and callbacks that are fast and return
immediately. To date this has not mattered much since the typical
CPUfreq governor calls the .target callback from process context via a
workqueue.
When
This series is partially in response to a discussion around DT bindings
for CPUfreq drivers [0], but it is also needed for on-going work to
integrate CPUfreq with the scheduler. In particular a scheduler-driven
cpu frequency scaling policy would be well served to know if the
underlying CPUfreq
There are cases for CPUfreq driver flags to be exposed outside of the
CPUfreq core code. In particular the CPUFREQ_NO_SLEEP flag can be used
by CPUfreq governors to optimize when and how they call that drivers
.target callback. In fact this knowledge is a requirement for the
on-going work to
>
> On 29/09/14 15:22, Weike Chen wrote:
> > + .num_chipselect = 4,
>
> How is this right ?
>
> There's only one physical chip-select line per SPI master...
>
> It's a 1:1 mapping.
>
Now, we have another board which can support 4 slave spi per master, but not
only Galileo. Since
On Wed, Oct 08, 2014 at 09:44:05AM +0200, Thierry Reding wrote:
> On Tue, Oct 07, 2014 at 03:57:58PM +0530, Vidya Sagar wrote:
[...]
> > +static inline void rp_writel(struct tegra_pcie_port *port, u32 value,
> > +unsigned long offset)
> > +{
> >
On Tue, Oct 07, 2014 at 08:44:05AM -0700, Stephen Warren wrote:
> On 10/07/2014 03:27 AM, Vidya Sagar wrote:
> > Enables root port to advertise its ASPM-L1 capability
> > resulting in possible link entry to L1 when an ASPM-L1 capable
> > device is connected
> > Enables per-controller & per-TMS
Liviu, Bjorn,
On 30.09.14 17:54:31, Liviu Dudau wrote:
> On Tue, Sep 30, 2014 at 05:18:05PM +0100, Bjorn Helgaas wrote:
> > OK, I rebuilt pci/host-generic from scratch. It consists of your v13
> > patches + Arnd's build fix for pci_pio_to_address() in !CONFIG_OF configs.
>
> Something went
On Tue, Oct 07, 2014 at 03:57:58PM +0530, Vidya Sagar wrote:
> Enables root port to advertise its ASPM-L1 capability
> resulting in possible link entry to L1 when an ASPM-L1 capable
> device is connected
> Enables per-controller & per-TMS clock clamping by default
> Enabling above features
This is a bug fix for using physical arch timers when
the arch_timer_use_virtual boolean is false. It restores the
arch_counter_get_cntpct() function after removal in
0d651e4e "clocksource: arch_timer: use virtual counters"
We need this on certain ARMv7 systems which are architected like this:
From: Doug Anderson
Some 32-bit (ARMv7) systems are architected like this:
* The firmware doesn't know and doesn't care about hypervisor mode and
we don't want to add the complexity of hypervisor there.
* The firmware isn't involved in SMP bringup or resume.
* The ARCH timer come up with an
On Tue, Oct 07, 2014 at 05:00:07PM -0400, Boris Ostrovsky wrote:
> Commit 3dcf63677d4e ("xen/balloon: cancel ballooning if adding new
> memory failed") makes reserve_additional_memory() return BP_ECANCELED
> when an error is encountered. This error, however, is ignored by the
> caller
Dear Dmitry,
在 2014年10月08日 07:39, Dmitry Torokhov 写道:
Hi Caesar,
On Sun, Sep 28, 2014 at 06:38:09PM +0800, Caesar Wang wrote:
Thermal is TS-ADC Controller module supports
user-defined mode and automatic mode.
User-defined mode refers,TSADC all the control signals entirely by
software writing
On Tuesday 30 September 2014 12:41:46 Tomi Valkeinen wrote:
> Hi,
>
> On 09/09/14 14:46, Maarten ter Huurne wrote:
> > This font is suitable for framebuffer consoles on devices with a
> > 320x240 screen, to get a reasonable number of characters (53x24) that
> > are still at a readable size.
> >
On Tue, Oct 07, 2014 at 05:07:36PM -0600, David Ahern wrote:
>
> 32-bit perf binaries are not able to set filters on 64-bit kernels.
>
>$ perf record -e net:netif_receive_skb --filter 'name == "eth1"
>Error: failed to set filter with 25 (Inappropriate ioctl for device)
>
> The reason
On Wed, Oct 8, 2014 at 4:09 PM, Muthu Mani wrote:
>> -Original Message-
>> From: Alexandre Courbot [mailto:gnu...@gmail.com]
>> Sent: Tuesday, October 07, 2014 3:34 PM
>> To: Muthu Mani
>> Cc: Samuel Ortiz; Lee Jones; Wolfram Sang; Linus Walleij; Greg Kroah-
>> Hartman;
On 7 October 2014 22:15, wrote:
> Vincent Guittot writes:
>
>> From: Morten Rasmussen
>>
>> Adds usage contribution tracking for group entities. Unlike
>> se->avg.load_avg_contrib, se->avg.utilization_avg_contrib for group
>> entities is the sum of se->avg.utilization_avg_contrib for all
On Tue, 7 Oct 2014, Dave Hansen wrote:
> Does this break slub's __cmpxchg_double_slab trick? I thought it
> required page->freelist and page->counters to be doubleword-aligned.
Sure that would be required for it to work.
> It's not like we really require this optimization when we're debugging,
> -Original Message-
> From: Alexandre Courbot [mailto:gnu...@gmail.com]
> Sent: Tuesday, October 07, 2014 3:34 PM
> To: Muthu Mani
> Cc: Samuel Ortiz; Lee Jones; Wolfram Sang; Linus Walleij; Greg Kroah-
> Hartman; linux-...@vger.kernel.org; linux-g...@vger.kernel.org; linux-
>
On 2014-10-07 at 18:17:16 +0200, Dmitry Torokhov
wrote:
> On Tue, Oct 07, 2014 at 03:33:22PM +0200, Tobias Klauser wrote:
> > On 2014-10-07 at 13:31:41 +0200, Pramod Gurav
> > wrote:
> > > This change switch to managed resources to simplifies error handling
> > > and module unloading and does
There are two masks associated with cpusets. The cpus/mems_allowed
and effective_cpus/mems. On the legacy hierarchy both these masks
are consistent with each other. This is the intersection of their
value and the currently active cpus. This means that we destroy the
original values set in these
> -Original Message-
> From: Johan Hovold [mailto:jhov...@gmail.com] On Behalf Of Johan Hovold
> Sent: Monday, October 06, 2014 7:03 PM
> To: Muthu Mani
> Cc: Samuel Ortiz; Lee Jones; Wolfram Sang; linux-...@vger.kernel.org; Linus
> Walleij; Alexandre Courbot; linux-g...@vger.kernel.org;
>
On Mon, Oct 06, 2014 at 08:53:51AM +0200, Jean Pihet wrote:
> Hi Jiri,
>
>
> On 5 October 2014 20:24, Jiri Olsa wrote:
> > On Sun, Oct 05, 2014 at 07:48:01PM +0200, Borislav Petkov wrote:
> >> Top-posting on purpose:
> >>
> >> Btw, jolsa, if you get your LCE proposal for the perf splitting
> >>
Sorry later response and just back from vacation.
On 2014年09月29日 16:20, Viresh Kumar wrote:
> But this change is buggy.. Because you are updating 'cpufreq_suspended'
> before actually stopping the governor, any calls to __cpufreq_governor()
> will be converted to NO-operations because of this in
Hi Mark,
On Tue, Oct 7, 2014 at 7:13 PM, Mark Rutland wrote:
>
> On Tue, Oct 07, 2014 at 01:40:28PM +0100, Arun Chandran wrote:
> > This is due to incorrect definition of ELF_ET_DYN_BASE. It
> > introduces randomization for text even if user does a "echo 0 >
> >
Hi all,
Please do not add any material intended for v3.19 to you linux-next
included trees until after v3.18-rc1 has been released.
Changes since 20141007:
Non-merge commits (relative to Linus' tree): 9651
8214 files changed, 378909 insertions(+), 275679 deletions(-)
On Tue, Sep 30, 2014 at 04:59:37PM +0200, Matteo Facchinetti wrote:
> From: Matteo Facchinetti
>
> In accordance with the other drivers that using the dma engine,
> fix it, leaving *only* to dma driver the complete control to
> ending the read operation.
>
> Removing STATUS_READ_OP_DONE event
Hello Karam,
On Mon, Oct 06, 2014 at 02:31:05PM +0900, karam@lge.com wrote:
> From: "karam.lee"
>
> Recently rw_page block device operation is added.
> This patch implements rw_page operation for zram block device so
> zram can process page sized I/O without bio.
It's a performance enhance
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