From: Bill Richardson wfric...@chromium.org
Chromebooks have an Embedded Controller (EC) that is used to
implement various functions such as keyboard, power and battery.
The AP can communicate with the EC through different bus types
such as I2C, SPI or LPC.
The cros_ec mfd driver is then
From: Bill Richardson wfric...@chromium.org
This patch adds a device interface to access the
Chrome OS Embedded Controller from user-space.
Signed-off-by: Bill Richardson wfric...@chromium.org
Reviewed-by: Simon Glass s...@google.com
Signed-off-by: Javier Martinez Canillas
The ChromeOS Embedded Controller has to be accessed by applications.
A virtual character device is used as an interface with user-space.
Extend the struct cros_ec_device with the fields needed by the driver
of this virtual character device.
Signed-off-by: Javier Martinez Canillas
Current migration code uses blk_put_request in order to finish a request
before requeuing it. This function doesn't update the statistics of the
queue, which completely screws accounting. Use blk_end_request_all instead
which properly updates the statistics of the queue.
Signed-off-by: Roger Pau
On 02/02/15 12:05, Jiri Olsa wrote:
On Mon, Feb 02, 2015 at 11:52:26AM +0200, Adrian Hunter wrote:
On 02/02/15 11:15, Jiri Olsa wrote:
On Mon, Feb 02, 2015 at 10:34:50AM +0200, Adrian Hunter wrote:
SNIP
but how about bump up the header version for this feature? ;-)
currently it's:
Hello Minchan:
2015-02-02 9:09 GMT+08:00 Minchan Kim minc...@kernel.org:
Hello Ganesh,
On Sat, Jan 31, 2015 at 04:59:58PM +0800, Ganesh Mahendran wrote:
ping.
2015-01-24 21:50 GMT+08:00 Ganesh Mahendran opensource.gan...@gmail.com:
The pool-size_class[i] is assigned with the i from
On Sun, Feb 01, 2015 at 06:42:11AM -0500, Nicholas Mc Guire wrote:
return type of wait_for_completion_timeout is unsigned long not int, this
patch adds an appropriate variable and fixes up the assignment.
Further it removes the else branch as the only thing it was
doing is assigning ret to 0
Hi,
This is the v8 of ACPI core patches for ARM64 based on ACPI 5.1, there are
some updates since v7:
- Add two more documantation to explain why we need ACPI in ARM64 servers
by Grant, and recommendations and prohibitions on the use of the numerous
ACPI tables and objects by Al Stone.
From: Mark Salter msal...@redhat.com
Commit 0e63ea48b4d8 (arm64/efi: add missing call to early_ioremap_reset())
added a missing call to early_ioremap_reset(). This triggers a BUG if code
tries using early_ioremap() after the early_ioremap_reset(). This is a
problem for some ACPI code which needs
From: Mark Salter msal...@redhat.com
The acpi_os_ioremap() function may be used to map normal RAM or IO
regions. The current implementation simply uses ioremap_cache(). This
will work for some architectures, but arm64 ioremap_cache() cannot be
used to map IO regions which don't support caching.
This patch adds the mux/divider/gate clocks of CMU_MIF domain which includes
the clocks for DMC(DRAM memory controller) and CCI(Cache Coherent Interconnect).
The CMU_MIF domain provides the source clocks for CMU_DISP/CMU_BUS2.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa
This patch adds the the mux/divider/gate clocks for CMU_DISP domain which
includes the clocks of Display IPs (DECON/HDMI/DSIM/MIXER). The CMU_DISP clocks
is used to need the source clock of CMU_MIF domain so, the CMU_MIF's clocks
related to CMU_DISP should be always on state.
Also, CMU_DISP must
This patch adds the mux/divider/gate clocks for CMU_AUD domain which
includes the clocks of Cortex-A5/Bus/Audio clocks.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
---
This patch adds the MUX (multiplexer) clocks for CMU_TOP domain of Exynos5433.
CMU_TOP domain provides source clocks to other CMU domains.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae
This patch adds the divider/gate of CMU_GSCL domain which contains gscaler
clocks.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
---
This patch adds devicetree binding document for Exynos5433 SoC system clock
controller.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
---
This patch adds the mux/divider/gate clocks for CMU_ATLAS domain which
generates the clocks for Cortex-A57 Quad-core processsor, L2 cache controller
and CoreSight.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
This patch adds the mux/divider/gate clocks for CMU_MFC domain which
generates the clocks for MFC(Multi-Format Codec) IP.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
From: Inha Song ideal.s...@samsung.com
This patch add CLKOUT driver support for Exynos5433 SoC.
Signed-off-by: Inha Song ideal.s...@samsung.com
Acked-by: Inki Dae inki@samsung.com
---
drivers/clk/samsung/clk-exynos-clkout.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
This patch adds the mux/divider/gate clocks for CMU_APOLLO domain which
generates the clocks for Cortex-A53 Quad-core processsor.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae
2015-02-02 19:20 GMT+09:00 Vlastimil Babka vba...@suse.cz:
On 02/02/2015 08:15 AM, Joonsoo Kim wrote:
Compaction has anti fragmentation algorithm. It is that freepage
should be more than pageblock order to finish the compaction if we don't
find any freepage in requested migratetype buddy list.
Hi,
I have an extremely odd situation when the I/O speed changes for both
SATA and SSD disks every few days or weeks with no apparent reason.
The servers have clean base install with nothing but SSH running and
the test I am doing is the following:
# dd if=/dev/zero of=/dev/sda4 bs=1M
On Mon, Feb 02, 2015 at 01:56:39PM +0100, Paul Bolle wrote:
On Sat, 2015-01-31 at 02:17 +0200, Kirill A. Shutemov wrote:
We would want to use number of page table level to define mm_struct.
Let's expose it as CONFIG_PGTABLE_LEVELS.
We need to define PGTABLE_LEVELS before sourcing
Hello,
At 2015/2/2 18:20, Vlastimil Babka wrote:
On 02/02/2015 08:15 AM, Joonsoo Kim wrote:
Compaction has anti fragmentation algorithm. It is that freepage
should be more than pageblock order to finish the compaction if we don't
find any freepage in requested migratetype buddy list. This is
Hi Mike,
On Fri, Jan 30, 2015 at 10:25 PM, Michael Turquette
mturque...@linaro.org wrote:
Private clock framework data structures should be private, surprisingly.
Now that all platforms and drivers have been updated to remove static
initializations of struct clk and struct clk_core objects
On 2015-01-30 20:58, Calvin Owens wrote:
On Thursday 01/29 at 17:30 -0800, Kees Cook wrote:
On Tue, Jan 27, 2015 at 8:38 PM, Calvin Owens calvinow...@fb.com wrote:
On Monday 01/26 at 15:43 -0800, Andrew Morton wrote:
On Tue, 27 Jan 2015 00:00:54 +0300 Cyrill Gorcunov gorcu...@gmail.com wrote:
Hello Geert
On Mon, Feb 2, 2015 at 2:04 PM, Geert Uytterhoeven ge...@linux-m68k.org wrote:
void * pvar=varB;
... = varB;
*pvar = ioread8(valid_memory);
Depending if ioread8 returns a u8 or a unsigned int, aren't we also
accessing varC?
Could not this be a problem?
Please try to
This patch adds the support for CMU (Clock Management Units) of Exynos5433
which is 64bit SoC and has Octa-cores. This patch supports necessary clocks
(PLL/MMC/UART/MCT/I2C/SPI) for kernel boot and includes binding documentation
for Exynos5433 clock controller.
Cc: Sylwester Nawrocki
This patch adds the mux/divider/gate clocks for CMU_AUD domain which
includes the clocks of Cortex-A5/Bus/Audio clocks.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
---
From: Markus Elfring elfr...@users.sourceforge.net
Date: Mon, 2 Feb 2015 13:20:23 +0100
The video_unregister_device() function tests whether its argument is NULL
and then returns immediately. Thus the test around the call is not needed.
This issue was detected by using the Coccinelle software.
Hello
Regarding ioread8 et al.
On include/asm-generic/io.h is defined as:
extern unsigned int ioread8(void __iomem *);
On include/asm-generic/io.h:
static inline u8 ioread8(const volatile void __iomem *addr)
Please ignore the qualifiers right now. The first function returns an
unsigned
From: Al Stone al.st...@linaro.org
Two more documentation files are also being added:
(1) A verbatim copy of the Why ACPI on ARM? blog posting by Grant Likely,
which is also summarized in arm-acpi.txt, and
(2) A section by section review of the ACPI spec (acpi_object_usage.txt)
to note
From: Al Stone al.st...@linaro.org
ACPI reduced hardware mode is disabled by default, but ARM64
can only run properly in ACPI hardware reduced mode, so select
ACPI_REDUCED_HARDWARE_ONLY if ACPI is enabled on ARM64.
CC: Catalin Marinas catalin.mari...@arm.com
CC: Will Deacon will.dea...@arm.com
Hi David,
What exactly are we breaking here? The USB on BYT-CR does not work yet
with the mainline kernel, or does it? To enable it, I already
suggested the BYT quirk (attached again).
It used to work with mainline with minor restrictions. It stopped
working (and I failed
From: Graeme Gregory graeme.greg...@linaro.org
Add documentation for the guidelines of how to use ACPI
on ARM64.
Reviewed-by: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Reviewed-by: Yi Li phoenix.l...@huawei.com
Reviewed-by: Mark Langsdorf mlang...@redhat.com
Reviewed-by: Ashwin
From: Tomasz Nowicki tomasz.nowi...@linaro.org
ACPI kernel uses MADT table for proper GIC initialization. It needs to
parse GIC related subtables, collect CPU interface and distributor
addresses and call driver initialization function (which is hardware
abstraction agnostic). In a similar way,
From: Graeme Gregory graeme.greg...@linaro.org
Add Kconfigs to build ACPI on ARM64, and make ACPI available on ARM64.
acpi_idle driver is x86/IA64 dependent now, so make CONFIG_ACPI_PROCESSOR
depend on X86 || IA64, and implement it on ARM64 in the future.
CC: Rafael J. Wysocki
Using the information presented by GTDT (Generic Timer Description Table)
to initialize the arch timer (not memory-mapped).
CC: Daniel Lezcano daniel.lezc...@linaro.org
Originally-by: Amit Daniel Kachhap amit.dan...@samsung.com
Tested-by: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Introduce a new function map_gicc_mpidr() to allow MPIDRs to be obtained
from the GICC Structure introduced by ACPI 5.1.
MPIDR is the CPU hardware ID as local APIC ID on x86 platform, so we use
MPIDR not the GIC CPU interface ID to identify CPUs.
Further steps would typedef a phys_id_t for in
On 01/31/2015 06:07 AM, Russell King - ARM Linux wrote:
On Fri, Jan 30, 2015 at 06:25:30AM -0500, Yakir Yang wrote:
For Designerware HDMI, the following write sequence is recommended:
1. aud_n3 (set bit ncts_atomic_write if desired)
2. aud_cts3 (set CTS_manual and CTS value if desired/enabled)
Tomi Valkeinen wrote:
On 06/01/15 14:45, Sudip Mukherjee wrote:
the check for info is not required as we are checking it immediately
after gxfb_init_fbinfo() and lxfb_init_fbinfo() and returnig -ENOMEM
if it is NULL.
Signed-off-by: Sudip Mukherjee su...@vectorindia.org
---
Hi Tomi,
This
This patchset adds the support for Exynos5433 CMU (Clock Management Unit)
by using common clock framework. This patchset is divided from patch[1]
and then sent it.
[1] https://lkml.org/lkml/2014/12/2/134
Changelog:
Changes from v3:
- Use 'oscclk' clock name instead of 'fin_pll'
- Add the clock
This patch adds the mux/divider/gate clocks for CMU_FSYS domain which
contains the clocks of USB/UFS/SDMMC/TSI/PDMA IPs.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
On Mon, Feb 02, 2015 at 05:50:52PM +0800, Ken Xue wrote:
From b9654ecbfaebde00aee746a024eec9fe8de24b97 Mon Sep 17 00:00:00 2001
From: Ken Xue ken@amd.com
Date: Mon, 2 Feb 2015 17:32:24 +0800
Subject: [PATCH] This new feature is to interpret AMD specific ACPI device to
platform device
Hi Ricardo,
On Mon, Feb 2, 2015 at 1:49 PM, Ricardo Ribalda Delgado
ricardo.riba...@gmail.com wrote:
Regarding ioread8 et al.
On include/asm-generic/io.h is defined as:
extern unsigned int ioread8(void __iomem *);
On include/asm-generic/io.h:
static inline u8 ioread8(const volatile void
On 01/31/2015 07:00 AM, Russell King - ARM Linux wrote:
On Fri, Jan 30, 2015 at 06:23:51AM -0500, Yakir Yang wrote:
We found Designware hdmi driver only support audio clock config, we can not
play sound through it.
To add Designware HDMI Audio support, we make those patch set:
1): modify
This patch adds the mux/divider/gate clocks for CMU_ISP domain which
generates the clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae
This patch adds the mux/divider/gate clocks for CMU_HEVC domain which
generates the clocks for HEVC(High Efficiency Video Codec) decoder IP.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae
This patch adds the mux/divider/gate clocks for CMU_HEVC domain which
generates the clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki
This patchset adds the support for following clock domains of Exynos5433
and clkout drvier.
Following clock domains has clocks for each IP.
- CMU_APOLLO : clocks for Cortex-A53 Quad-core processor.
- CMU_ATLAS : clocks for Cortex-A57 Quad-core processor, CoreSight and
L2 cache
This patch adds the mux/divider/gate clocks for CMU_MSCL domain which
generates the clocks for M2M (Memory to Memory) scaler, JPEG IPs.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae
On Fri, Jan 30, 2015 at 10:54:25PM +, mathieu.poir...@linaro.org wrote:
From: Mathieu Poirier mathieu.poir...@linaro.org
Adding a lookup function allowing for quick and easy mapping
between processor HWID (as found, for example) in DT specifications
and the CPU index known to the kernel.
attach_to_pi_owner() checks p-mm to prevent attaching to kthreads and
this looks doubly wrong:
1. It should actually check PF_KTHREAD, kthread can do use_mm().
2. If this task is not kthread and it is actually the lock owner we can
wrongly return -EPERM instead of -ESRCH or retry-if-EAGAIN.
Thomas, et al, could you please review?
The change looks trivial, but I simply can not understand this logic,
please help.
First of all, why exactly do we need this mm/PF_KTHREAD check added by
f0d71b3dcb8332f7971 ? Of course, it is simply wrong to declare a random
kernel thread to be the
This patch adds the divider/gate of CMU_GSCL domain which contains gscaler
clocks.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
---
This patch adds missing divider/gate clocks of CMU_PERIC domain
which includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may use
external input clock which has 'ioclk_*' prefix.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi
This patchset adds the support for Exynos5433 CMU (Clock Management Unit)
by using common clock framework. This patchset is divided from patch[1]
and then sent it.
[1] https://lkml.org/lkml/2014/12/2/134
Changelog:
Changes from v4:
- Add input clock information to binding document
Changes from
This patch adds the mux/divider/gate clocks for CMU_BUS{0|1|2} domains
which contain global data buses clocked at up the 400MHz. These blocks
transfer data between DRAM and various sub-blocks. These clock domains
also contain global peripheral buses clocked at 67/111/200/222/266/333/400
MHz and
This patch adds ths mux/divider/gate clocks of CMU_G2D domain which includes
G2D/MDMA IPs. The CMU_G2D must need the clocks related to G2D by providing
CMU_TOP domain. So, this patch add several clocks for G2D from CMU_TOP domain.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa
CONFIG_ACPI depends CONFIG_PCI on x86 and ia64, in ARM64 server
world we will have PCIe in most cases, but some of them may not,
make CONFIG_ACPI depend CONFIG_PCI on ARM64 will satisfy both.
With that case, we need some arch dependent PCI functions to
access the config space before the PCI root
From: Graeme Gregory graeme.greg...@linaro.org
ACPI 5.1 does not currently support S states for ARM64 hardware but
ACPI code will call acpi_target_system_state() for device power
managment, so introduce sleep_arm.c to allow other drivers to function
until S states are defined.
CC: Rafael J.
From: Graeme Gregory graeme.greg...@linaro.org
Now with the base changes to the arm memory mapping it is safe
to convert to using ioremap to map in the tables after
acpi_gbl_permanent_mmap is set.
CC: Rafael J Wysocki r...@rjwysocki.net
Signed-off-by: Al Stone al.st...@linaro.org
Signed-off-by:
You can't really compare a bus like i2c, which can't enumerate devices
natively, to ULPI which can.
why not ? The BIOS might not need to use the PHY (or USB) at all, it can
very well decide to never turn it on, right ?
If ULPI was seen as a bus, then no. BIOS would have
This patch adds the mux/divider/gate clocks for CMU_G3D domain which contains
the clocks for GPU(3D Graphics Engine).
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
On Sun, Feb 01, 2015 at 09:52:05PM -0500, gr...@linuxhacker.ru wrote:
From: Dmitry Eremin dmitry.ere...@intel.com
Expression if (size != (ssize_t)size) is always false.
Therefore no bounds check errors detected.
The original code actually worked as designed. The integer overflow
could only
On Mon, Feb 02, 2015 at 07:32:05AM -0500, Yang Kuankuan wrote:
On 02/02/2015 06:53 AM, Russell King - ARM Linux wrote:
On Mon, Feb 02, 2015 at 12:02:50PM +0800, Daniel Kurtz wrote:
Hi ykk,
On Sat, Jan 31, 2015 at 10:34 PM, Yang Kuankuan y...@rock-chips.com wrote:
On 01/31/2015 06:48 AM,
Hello,
I have an extremely odd situation when the I/O speed changes for both SATA
and SSD disks every few days or weeks with no apparent reason.
The servers have clean base install with nothing but SSH running and the
test I am doing is the following:
# dd if=/dev/zero of=/dev/sda4 bs=1M
Hi,
we've got a bug report about the mishandling of DVD/CDROM media eject
button, and it seems indeed broken since some time ago. In short:
when the eject button is pressed, the media is forcibly ejected no
matter whether it's mounted or in use. And, the mount remains even
after ejecting the
2015-02-02 21:56 GMT+09:00 Zhang Yanfei zhangyanfei...@hotmail.com:
Hello Joonsoo,
At 2015/2/2 15:15, Joonsoo Kim wrote:
This is preparation step to use page allocator's anti fragmentation logic
in compaction. This patch just separates fallback freepage checking part
from fallback freepage
On Tue 2015-01-27 10:16:24, Nicolas Pitre wrote:
On Tue, 27 Jan 2015, Pavel Machek wrote:
I would say, problem is because omap3-n900 binary DT is too large
I agree.
OK if that's the case, then your patch makes sense to me. It also
seems we can have the temporary stack
Hi!
[Actually, you could _always_ do two reads on those devices, discard
first result, and return the second. But I'm not sure how hardware
will like that.]
This would be the most sensible option.
However, let's analyze the typical use cases for flash strobing:
Hi Jens,
I found 2 patches commits (74170118b e09aae7e)from
https://git.kernel.org/cgit/linux/kernel/git/axboe/linux-block.git/log/?h=for-linus
After apply those 2 patches, the bug was fixed.
Is it possible to include those 2 patches in official 3.19.0?
On Mon, Feb 2, 2015 at 12:11 PM, Jinpu
On Mon, Feb 02, 2015 at 01:40:33PM +, Leif Lindholm wrote:
On Mon, Feb 02, 2015 at 08:45:36PM +0800, Hanjun Guo wrote:
When system supporting both DT and ACPI but firmware providing
no dtb, we can use this linux,uefi-stub-generated-dtb property
to let kernel know that we can try ACPI
On 01/30/2015, 10:54 PM, Tim Chen wrote:
On Sat, 2015-01-31 at 00:03 +0300, Sergei Shtylyov wrote:
On 01/30/2015 10:54 PM, Tim Chen wrote:
return NULL;
}
+ /* round up to full page size */
+ size = (((size-1) PAGE_SHIFT) + 1) * PAGE_SIZE;
This is quite
On 02/02/2015 02:23 PM, Joonsoo Kim wrote:
2015-02-02 19:20 GMT+09:00 Vlastimil Babka vba...@suse.cz:
On 02/02/2015 08:15 AM, Joonsoo Kim wrote:
So I've realized that this problaby won't always work as intended :/ Because
we
still differ from what page allocator does.
Consider we compact
This series is tested on usb-next with Heikki's patch [1]:
base: platform: name the device already during allocation
Changes since v6:
- Dropped the changes for adding additional phy_calibrate() callback.
- Added phy_init() and phy_power_on() sequence in xhci-plat driver;
NOTE: both
Currently, to enable kmem accounting for a cgroup, one has to set
kmem.limit_in_bytes for it, otherwise the cgroup will not have kmem
accounting enabled. This means we can configure kmem accounting for a
subset of cgroups, while leaving it disabled for the rest.
However, a separate knob for
From: Al Stone al.st...@linaro.org
As we want to get ACPI tables to parse and then use the information
for system initialization, we should get the RSDP (Root System
Description Pointer) first, it then locates Extended Root Description
Table (XSDT) which contains all the 64-bit physical address
FADT Major.Minor version was introduced in ACPI 5.1, it is the same
as ACPI version.
In ACPI 5.1, some major gaps are fixed for ARM, such as updates in
MADT table for GIC and SMP init, without those updates, we can not
get the MPIDR for SMP init, and GICv2/3 related init information, so
we can't
Introduce ACPI_IRQ_MODEL_GIC which is needed for ARM64 as GIC is
used, and then register device's gsi with the core IRQ subsystem.
acpi_register_gsi() is similar to DT based irq_of_parse_and_map(),
since gsi is unique in the system, so use hwirq number directly
for the mapping.
We are going to
From: Al Stone al.st...@linaro.org
Introduce two early parameters off and force for acpi, acpi=off
will be the default behavior for ARM64, so introduce acpi=force to
enable ACPI on ARM64.
Disable ACPI before early parameters parsed, and enable it to pass
acpi=force if people want use ACPI on
When MADT is parsed, print GIC information to make the boot
log look pretty:
ACPI: GICC (acpi_id[0x] address[e112f000] MPIDR[0x0] enabled)
ACPI: GICC (acpi_id[0x0001] address[e112f000] MPIDR[0x1] enabled)
...
ACPI: GICC (acpi_id[0x0201] address[e112f000] MPIDR[0x201]
Hello Joonsoo,
At 2015/2/2 15:15, Joonsoo Kim wrote:
This is preparation step to use page allocator's anti fragmentation logic
in compaction. This patch just separates fallback freepage checking part
from fallback freepage management part. Therefore, there is no functional
change.
On Sat, 2015-01-31 at 02:17 +0200, Kirill A. Shutemov wrote:
We would want to use number of page table level to define mm_struct.
Let's expose it as CONFIG_PGTABLE_LEVELS.
We need to define PGTABLE_LEVELS before sourcing init/Kconfig:
arch/Kconfig will define default value and it's sourced
On Mon, Feb 02 2015, George Spelvin li...@horizon.com wrote:
Rasmus Villemoes li...@rasmusvillemoes.dk wrote:
... and this be part of _find_next_bit? Can find_next_bit not be simply
'return _find_next_bit(addr, size, offset, 1);', and similarly for
find_next_zero_bit? Btw., passing true and
This patch adds missing divider/gate clocks of CMU_PERIC domain
which includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may use
external input clock which has 'ioclk_*' prefix.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi
This patch adds the mux/divider/gate clocks for CMU_CAM1 domain which
generates the clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae
On 01/28/2015 11:47 PM, Rickard Strandqvist wrote:
Variable ar assigned a value that is never used.
I have also removed all the code that thereby serves no purpose.
This was found using a static code analysis program called cppcheck
FYI: I've dropped this patch since the vino driver will be
If the divider or multiplier values values are 0 in the
register, bypassing the divider and returning the parent
clock rate in clk_fd_recalc_rate().
Signed-off-by: Heikki Krogerus heikki.kroge...@linux.intel.com
---
drivers/clk/clk-fractional-divider.c | 3 +++
1 file changed, 3 insertions(+)
When running sparse on the osc/ subdirectory, it shows the
following warning:
andreas@workbox:~/linux-next$ make C=1 M=drivers/staging/lustre/lustre/osc/
[...]
drivers/staging/lustre/lustre/osc/osc_request.c:3335:12: warning:
symbol 'osc_init' was not declared. Should it be static?
[...]
As this
On Mon, Feb 2, 2015 at 2:33 AM, Christoph Hellwig h...@lst.de wrote:
On Sat, Jan 31, 2015 at 07:19:17PM -0800, Fengguang Wu wrote:
Hi Christoph,
FYI, this patch discloses an 100% reproducible boot warning.
git://git.infradead.org/users/hch/pnfs.git flexfiles+pnfsd
commit
Hi Linus,
there is a high bug-spot activity in GPIO this merge window, much
due to Johan Hovolds spearheading into actually exercising the
removal path for GPIO chips, something that was never really
exercised before.
The other two fixes are augmenting erroneous behaviours in two
specific
It is possible for the *_read*() functions to fail, in which case it'll
leave its third argument untouched. Most of the code do not check the
return value of *_read*() functions, and will happily use garbage from the
stack to test various things. For example, ch7xxx_dump_regs() will leak 1
byte
On Mon, Feb 02, 2015 at 02:36:43PM +0100, Andreas Ruprecht wrote:
When running sparse on the osc/ subdirectory, it shows the
following warning:
andreas@workbox:~/linux-next$ make C=1 M=drivers/staging/lustre/lustre/osc/
[...]
drivers/staging/lustre/lustre/osc/osc_request.c:3335:12: warning:
This patch adds missing gate clocks of CMU_PERIS domain
which includes TMU/TZPC/SECKEY/CHIPID/TOPRTC/EFUSE IPs.
The special clocks of CMU_PERIS use fin_pll source clock directly.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi
2015-02-02 15:26+0100, Radim Krčmář:
2015-01-30 09:52+0100, Paolo Bonzini:
+ return ((logical_id 4) == (mda 4))
+ (logical_id mda 0xf) != 0;
but it has to be parenthesized ('' has lower precedence than '!=').
No, my bad, I understood it now.
--
To
This patch adds the mux/divider/gate clocks of CMU_MIF domain which includes
the clocks for DMC(DRAM memory controller) and CCI(Cache Coherent Interconnect).
The CMU_MIF domain provides the source clocks for CMU_DISP/CMU_BUS2.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa
On 02/02/2015 15:26, Radim Krčmář wrote:
+ return ((logical_id 4) == (mda 4))
+ (logical_id mda 0xf);
was merged as
+ return ((logical_id 4) == (mda 4))
+ (logical_id mda 0xf) != 0;
but it has to be
On 02/02/15 11:15, Jiri Olsa wrote:
On Mon, Feb 02, 2015 at 10:34:50AM +0200, Adrian Hunter wrote:
SNIP
but how about bump up the header version for this feature? ;-)
currently it's:
struct perf_file_header {
u64 magic;
u64
On 02/02/2015 08:15 AM, Joonsoo Kim wrote:
This is preparation step to use page allocator's anti fragmentation logic
in compaction. This patch just separates fallback freepage checking part
from fallback freepage management part. Therefore, there is no functional
change.
Signed-off-by:
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