Platform device driver that sets up the basic bus infrastructure
for the fsl-mc bus type, including support for adding/removing
fsl-mc devices, register/unregister of fsl-mc drivers, and bus
match support to bind devices to drivers.
Signed-off-by: J. German Rivera german.riv...@freescale.com
This patch series introduces Linux support for the Freescale
Management Complex (fsl-mc) hardware. This patch series is dependent
on the patch series ARM64: Add support for FSL's LS2085A SoC
(http://thread.gmane.org/gmane.linux.ports.arm.kernel/351829)
The fsl-mc is a hardware resource manager
Dear Jan
-Original Message-
From: Jan Beulich [mailto:jbeul...@suse.com]
Sent: Thursday, March 5, 2015 5:00 PM
To: Wang, Xiaoming
Cc: l...@aserp2030.oracle.com; zh...@aserp2030.oracle.com; chris@chris-
wilson.co.uk; david.vra...@citrix.com; lau...@codeaurora.org;
* Robert Abel ra...@cit-ec.uni-bielefeld.de [150303 05:03]:
Hi Roger,
On Tue, Mar 3, 2015 at 1:55 PM, Roger Quadros rog...@ti.com wrote:
I'm OK with this version.
Tony, after you ACK these I will queue them for v4.1.
Please use v4 of my patches. The DTS output has been changed and the
(2015/03/05 23:18), Josh Poimboeuf wrote:
On Thu, Mar 05, 2015 at 09:52:41AM +0900, Masami Hiramatsu wrote:
(2015/03/04 22:17), Petr Mladek wrote:
On Tue 2015-03-03 17:02:22, Josh Poimboeuf wrote:
It's possible for klp_register_patch() to see a module before the COMING
notifier is called, or
Please always CC linux-pm on CC patches.
On Thursday, March 05, 2015 04:34:06 PM Tony Lindgren wrote:
Some devices have separate wake-up interrupts in addition to the
normal device interrupts. The wake-up interrupts can be connected
to a separate interrupt controller that is always powered.
From: Stefan Agner ste...@agner.ch Sent: Thursday, March 05, 2015 10:09 PM
To: da...@davemloft.net
Cc: Duan Fugang-B38611; net...@vger.kernel.org; linux-
ker...@vger.kernel.org; ste...@agner.ch
Subject: [PATCH] net: fec: fix unbalanced clk disable on driver unbind
When the driver is removed
Please attach the acpidump output.
Thanks,
rui
-Original Message-
From: linux-pm-ow...@vger.kernel.org [mailto:linux-pm-ow...@vger.kernel.org] On
Behalf Of Josh Boyer
Sent: Thursday, March 5, 2015 10:30 PM
To: Zhang, Rui
Cc: Eduardo Valentin; Linux PM list; Linux-Kernel@Vger. Kernel.
On Thu, Mar 5, 2015 at 7:57 AM, Baoquan He b...@redhat.com wrote:
Hi Yinghai,
I have rearrange my patchset, they depend on your patchset in below
link. How should I post them?
Please check
https://git.kernel.org/cgit/linux/kernel/git/yinghai/linux-yinghai.git/log/?h=for-x86-4.0-rc2-aslr
On Thu, Mar 05, 2015 at 12:52:30PM -0600, Kumar Gala wrote:
On Mar 3, 2015, at 6:21 PM, Kenneth Westfield kwest...@codeaurora.org wrote:
+++ b/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.txt
@@ -0,0 +1,49 @@
+* Qualcomm Technologies LPASS CPU DAI
+
+Required subnodes:
+
From: Chao Xie chao@marvell.com
For some old PXA series, they used PXA GPIO driver.
The IP of GPIO changes since PXA988 which is Marvell MMP
series.
It will use new way to control the GPIO level, direction
and edge status.
Signed-off-by: Chao Xie chao@marvell.com
---
On Thu, Mar 5, 2015 at 8:59 PM, Olof Johansson o...@lixom.net wrote:
On Thu, Mar 5, 2015 at 12:23 PM, Kumar Gala ga...@codeaurora.org wrote:
On Mar 5, 2015, at 1:42 PM, Kevin Hilman khil...@kernel.org wrote:
Kumar Gala ga...@codeaurora.org writes:
The top level qcom,msm-id and qcom,board-id
On Thu, Mar 05, 2015 at 01:18:54PM +0100, Stefan Wahren wrote:
Hi Peter,
Am 05.03.2015 um 11:35 schrieb Peter Chen:
Hi lists,
Any good ways at code/dts to show parent/child hierarchy for regulator?
The related regulators at my platforms like below:
PMIC (SWB 5v) -- Switch Chip
On Thu, Mar 05, 2015 at 12:22:34PM +, Mark Brown wrote:
On Thu, Mar 05, 2015 at 06:35:36PM +0800, Peter Chen wrote:
Any good ways at code/dts to show parent/child hierarchy for regulator?
There's plenty of examples in mainline...
thanks, I am back to study again.
The related
On (03/05/15 09:20), Minchan Kim wrote:
In summary, I want to support only cat /sys/class/zram-control/zram_add
unless you have feasible usecase.
What do you think about it?
Hello Minchan,
I've tried to contact as many guys (who has previously demonstrated some
interest in on-demand
On Thu, 5 Mar 2015 17:46:05 +0100
Christophe Leroy christophe.le...@c-s.fr wrote:
[15/17] crypto: talitos - Implementation of SEC1
...
[16/17] crypto: talitos - SEC1 bugs on 0 data hash
[17/17] crypto: talitos - Update DT bindings with SEC1
This patchseries doesn't apply, at least on top of
Some devices have separate wake-up interrupts in addition to the
normal device interrupts. The wake-up interrupts can be connected
to a separate interrupt controller that is always powered. This
allows the devices and the whole system to enter deeper idle states
while still being able to wake-up
We can now use generic wakeirq handling and remove the custom handling
for the wake-up interrupts.
Signed-off-by: Tony Lindgren t...@atomide.com
---
drivers/tty/serial/8250/8250_omap.c | 67 -
1 file changed, 14 insertions(+), 53 deletions(-)
diff --git
We can now use generic wakeirq handling and remove the custom handling
for the wake-up interrupts.
Signed-off-by: Tony Lindgren t...@atomide.com
---
drivers/tty/serial/omap-serial.c | 38 ++
1 file changed, 14 insertions(+), 24 deletions(-)
diff --git
We can now use generic wakeirq handling and remove the custom handling
for the wake-up interrupts.
Signed-off-by: Tony Lindgren t...@atomide.com
---
drivers/mmc/host/omap_hsmmc.c | 55 +++
1 file changed, 14 insertions(+), 41 deletions(-)
diff --git
APIs to access the Management Complex (MC) hardware
module of Freescale LS2 SoCs. This patch includes
APIs to check the MC firmware version and to manipulate
DPRC objects in the MC.
Signed-off-by: J. German Rivera german.riv...@freescale.com
Signed-off-by: Stuart Yoder stuart.yo...@freescale.com
On Thu, Mar 5, 2015 at 3:48 PM, Mathieu Desnoyers
mathieu.desnoy...@efficios.com wrote:
llist_next() is pretty simple:
static inline struct llist_node *llist_next(struct llist_node *node)
{
return node-next;
}
It is so simple that I wonder if the compiler would be
within its
This adds the support for Broadcom iProc PCIe controller
pcie-iproc.c servers as the common core driver, and front-end bus
interface needs to be added to support different bus interfaces
pcie-iproc-pltfm.c contains the support for the platform bus interface
Signed-off-by: Ray Jui
On Fri, Mar 6, 2015 at 6:36 AM, Dmitry Torokhov d...@chromium.org wrote:
On Thu, Mar 5, 2015 at 2:12 PM, Marcel Holtmann mar...@holtmann.org wrote:
Hi Dmitry,
Specifically this was motivated by a situation where we have one
device with a dual-sourced touchscreen. Both use the same driver but
A DPRC (Data Path Resource Container) is an isolation device
that contains a set of DPAA networking devices to be
assigned to an isolation domain (e.g., a virtual machine).
Signed-off-by: J. German Rivera german.riv...@freescale.com
Signed-off-by: Stuart Yoder stuart.yo...@freescale.com
---
On 2015/3/5 20:12, Marc Zyngier wrote:
On 04/03/15 03:18, Yun Wu wrote:
This patch series makes some enhancement to ITS configuration in the
following aspects:
o make allocation of the ITS tables more sensible
o replace magic numbers with sensible macros
o guarantees a safe quiescent
On 2015/3/5 20:05, Marc Zyngier wrote:
On 04/03/15 03:18, Yun Wu wrote:
It's unsafe to change the configurations of an activated ITS directly
since this will lead to unpredictable results. This patch guarantees
the ITSes being initialized are quiescent.
Signed-off-by: Yun Wu
This is a checkpatch'd version of the pids patchset[1]. It fixes some
style problems, as well as switch to using need_canfork_callback inside
kernel/cgroup.c. Also remove the dependency on PAGE_COUNTER (because
pids now uses an internal hierarchical counter) in Kconfig.
[1]:
Add a new cgroup subsystem callback can_fork that conditionally
states whether or not the fork is accepted or rejected with a cgroup
policy.
Make the cgroup subsystem can_fork callback return an error code so
that subsystems can accept or reject a fork from completing with a
custom error value,
Hi, Gabriele
I couldn't find this in my mail box, but saw it in the spinics.net.
For EC query, there is no spec definitions around its behavior.
Some EC firmware will have events queued (like edge triggering) while the
others will keeps on reporting events when a condition is set (like level
On Thu, Mar 05, 2015 at 11:33:14AM +0100, Richard Weinberger wrote:
Brian,
Am 28.02.2015 um 11:23 schrieb Brian Norris:
Except for the last one, these were inspired by Coverity Scan results.
These fixes have barely been tested, but they are pretty straightforward
logically. As they've
From: Yanjiang Jin yanjiang@windriver.com
sec4_sg_bytes not being properly initialized causes ahash_done
to try to free unallocated DMA memory:
caam_jr ffe301000.jr: DMA-API: device driver tries to free DMA memory it has
not allocated [device address=0xdeadbeefdeadbeef] [size=3735928559
From: Yanjiang Jin yanjiang@windriver.com
Hi,
This patch series fix some CAAM compile and runtime warnings.
I have tested this on fsl-p5020ds board using upstream 4.0.0-rc2 with the below
configs:
CONFIG_DMA_API_DEBUG=y
# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
Change log:
v3:
From: Yanjiang Jin yanjiang@windriver.com
Fix rng_unmap_ctx's DMA_UNMAP size problem for caam_rng, else system would
report the below calltrace during cleanup caam_rng.
Since rng_create_sh_desc() creates a fixed descriptor of exactly 4
command-lengths now, also update DESC_RNG_LEN to (4 *
From: Alexander Drozdov al.droz...@gmail.com
Date: Thu, 5 Mar 2015 10:29:39 +0300
ip_check_defrag() may be used by af_packet to defragment outgoing packets.
skb_network_offset() of af_packet's outgoing packets is not zero.
Signed-off-by: Alexander Drozdov al.droz...@gmail.com
Applied,
On Thu, Mar 05, 2015 at 09:37:52AM +, Naoya Horiguchi wrote:
...
With the above simplified versions used, the rest of the patch becomes
almost trivial.
Other than that, I'm OK to write in the simplified form.
Here is the updated one.
And I found some cleanups and/or tiny fixes
On Thu, Mar 5, 2015 at 5:35 PM, Alexandre Belloni
alexandre.bell...@free-electrons.com wrote:
On 05/03/2015 at 16:50:57 -0600, Rob Herring wrote :
-config SOC_SAMA5
+config ARCH_AT91
bool
- select ATMEL_AIC5_IRQ
+ select ARCH_REQUIRE_GPIOLIB
select
The INIT_TSS is unnecessary. Just define the initial TSS where cpu_tss
is defined.
While we're at it, merge the 32-bit and 64-bit definitions. The only
syntactic change is that 32-bit kernels were computing sp0 as long, but
now they compute it as unsigned long.
Verified by objdump: the
This has nothing to do with the init thread or the initial anything.
It's just the TSS.
Signed-off-by: Andy Lutomirski l...@amacapital.net
---
arch/x86/kernel/entry_64.S | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kernel/entry_64.S
We currently store references to the top of the kernel stack in
multiple places: kernel_stack (with an offset) and
init_tss.x86_tss.sp0 (no offset). The latter is defined by hardware
and is a clean canonical way to find the top of the stack. Add an
accessor so we can start using it.
This needs
From: Michal Simek michal.si...@xilinx.com
Date: Thu, 5 Mar 2015 15:02:10 +0100
From: Punnaiah Choudary Kalluri punnaiah.choudary.kall...@xilinx.com
The latest spec I-IPA01-0266-USR Rev 10 limit the MID field length to 12 bit
value. For previous versions it is 16 bit value.
This change
From: Stefan Agner ste...@agner.ch
Date: Thu, 5 Mar 2015 15:09:29 +0100
When the driver is removed (e.g. using unbind through sysfs), the
clocks get disabled twice, once on fec_enet_close and once on
fec_drv_remove. Since the clocks are enabled only once, this leads
to a warning:
WARNING:
On Thu, Mar 05, 2015 at 05:00:05PM +0100, Frederic Weisbecker wrote:
On Thu, Mar 05, 2015 at 07:56:59AM -0800, Paul E. McKenney wrote:
On Thu, Mar 05, 2015 at 04:35:09PM +0100, Frederic Weisbecker wrote:
So, in the case we are calling that right after setting
cputimer-running, I guess we
-Original Message-
From: Andy Shevchenko [mailto:andy.shevche...@gmail.com]
Sent: Friday, March 6, 2015 12:11 AM
To: Ong, Boon Leong
Cc: Bryan O'Donoghue; Zhang, Rui; edubez...@gmail.com; Kweh, Hock Leong;
linux...@vger.kernel.org; linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/1]
Thanks for feedback :).
You are right, checkpatch.pl does not complain about issues in existing code.
I did these changes so that existing code has similar coding style with the
newly added code.
This way, in the entire driver we will have the same coding style.
Regards,
Anda
On 02/24/2015 11:32 AM, Vlastimil Babka wrote:
On 02/23/2015 11:56 PM, Andrew Morton wrote:
On Mon, 23 Feb 2015 14:46:43 -0800 Davidlohr Bueso d...@stgolabs.net wrote:
On Mon, 2015-02-23 at 13:58 +0100, Vlastimil Babka wrote:
Recently, there was concern expressed (e.g. [1]) whether the quite
Add missing cdns,at91sam9260-macb, atmel,sama5d3-gem and
atmel,sama5d4-gem compatible strings.
Signed-off-by: Boris Brezillon boris.brezil...@free-electrons.com
---
Documentation/devicetree/bindings/net/macb.txt | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git
On 03/05/2015 06:15 PM, Vinod Koul wrote:
On Thu, Mar 05, 2015 at 03:03:04PM +0200, Stanimir Varbanov wrote:
Avoid the warning below triggered during dmaengine async device
registration.
WARNING: CPU: 1 PID: 1 at linux/drivers/dma/dmaengine.c:863
dma_async_device_register+0x2a8/0x4b8()
this
On 03/04/2015 09:14 PM, Frederic Weisbecker wrote:
Current context tracking symbols are designed to express living state.
As such they are prefixed with IN_: IN_USER, IN_KERNEL.
Now we are going to use these symbols to also express state transitions
such as context_tracking_enter(IN_USER) or
Hi Rafael,
enable_irq_wake() has no effect on IRQF_NO_SUSPEND interrupts, so if the
driver uses IRQF_NO_SUSPEND, it does not need to use enable_irq_wake()
in addition to that.
That's not generally true -- certainly not for irq_chips without the
IRQCHIP_SKIP_SET_WAKE flag.
Consider systems
Building with the attached random configuration file,
In file included from include/linux/vmalloc.h:8:0,
from ./arch/x86/include/asm/io.h:200,
from ./arch/x86/include/asm/realmode.h:5,
from ./arch/x86/include/asm/acpi.h:33,
from
On Thu, Feb 19, 2015 at 06:45:50PM +0200, Stanimir Varbanov wrote:
The commit fb93f520e (dmaengine: qcom_bam_dma: Generalize BAM
register offset calculations) wrongly populated base offsets
for event registers for bam v1.4.
Applied, thanks
--
~Vinod
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Commit-ID: 9ab6eb51ef4ad63cb71533d3a4dfb09ea8f69b4c
Gitweb: http://git.kernel.org/tip/9ab6eb51ef4ad63cb71533d3a4dfb09ea8f69b4c
Author: Andy Shevchenko andriy.shevche...@linux.intel.com
AuthorDate: Thu, 5 Mar 2015 17:24:04 +0200
Committer: Ingo Molnar mi...@kernel.org
CommitDate: Thu, 5
SEC1 bugs on 0 data hash, so we submit an already padded block representing 0
data
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 3 +++
drivers/crypto/talitos1.c | 21 +
drivers/crypto/talitos1.h | 4
SEC1 doesn't support scatter/gather, therefore this part of the code will
have to be implemented differently for SEC1, so we isolate it in a small
helper function
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 29 +++--
1 file
j_extent field is specific to SEC2 so we add a helper function to clear it
so that SEC1 can redefine that function as nop
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 2 +-
drivers/crypto/talitos2.h | 5 +
2 files changed, 6 insertions(+), 1
Move reset/init helpers init talitos2.h as they are specific to SEC2
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 19 ---
drivers/crypto/talitos2.h | 20
2 files changed, 20 insertions(+), 19 deletions(-)
diff
On Sun, Feb 15, 2015 at 07:49:16PM +0100, Robert Jarzmik wrote:
Fix the dmaengine complaint about missing slave caps :
- declare the available bus widths
- declare the available transfer types
- declare the residue calculation type
Applied, thanks
--
~Vinod
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To unsubscribe from this
This patch updates the documentation by including SEC1 into SEC2/3 doc
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
Documentation/devicetree/bindings/crypto/fsl-sec2.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git
Move hash chain handling into talitos2.h as only SEC2 has sg chaining
capatibility
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 34 --
drivers/crypto/talitos2.h | 34 ++
2 files changed,
* Daniel Lezcano daniel.lezc...@linaro.org wrote:
Hi Ingo, Thomas,
This couple of patches fixes a potential crash at boot time.
- Fix setup_irq / clockevents_config_and_register init ordering in order to
prevent to have an interrupt to be fired before the handler is set for sun5i
and
Only commit log and patch additions are checked for
typos and spelling errors currently. Add a check
of the email subject line too.
Suggested-by: Jani Nikula jani.nik...@linux.intel.com
Signed-off-by: Joe Perches j...@perches.com
---
scripts/checkpatch.pl | 3 ++-
1 file changed, 2
On 02/12/2015 08:32 AM, Joonsoo Kim wrote:
1) Break non-overlapped zone assumption
CMA regions could be spread to all memory range, so, to keep all of them
into one zone, span of ZONE_CMA would be overlap to other zones'.
From patch 13/16 ut seems to me that indeed the ZONE_CMA spans the
Please take Mark's patch if you think it is better.
On Thu, Mar 5, 2015 at 8:38 AM, Bjorn Helgaas bhelg...@google.com wrote:
[+cc Mark]
On Thu, Feb 26, 2015 at 06:21:51PM -0600, Bjorn Helgaas wrote:
On Tue, Feb 17, 2015 at 03:14:00PM -0800, Feng Kan wrote:
The generic accessor functions
Hi,
On 2015-03-05 17:30:16 +0100, Vlastimil Babka wrote:
That however means the workload is based on hugetlbfs and shouldn't trigger
THP
page fault activity, which is the aim of this patchset. Some more googling
made
me recall that last LSF/MM, postgresql people mentioned THP issues and
SEC1 and SEC2 have different EU base addresses, so define base addresses
as #define
SEC1 and SEC2 have different bit masks for ISR registers, so create a
macro to define them
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.h | 85
In order to be able to manage differences between SEC1 and SEC2, we split
talitos.h into two parts.
talitos2.h will contain all parts that are specific to SEC2 and different on
SEC1
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.h | 163
Do use zero_entry value to init the descriptors ptrs to zero instead of
writing 0 in each field
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/crypto/talitos.c
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 4 +---
drivers/crypto/talitos2.h | 2 ++
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 6c1f6f1..9f75ec9 100644
---
On Thu, 5 Mar 2015 16:56:43 +0100 (CET)
Miroslav Benes mbe...@suse.cz wrote:
I don't know if you plan to do something about this patch or if you just
missed it in your e-mail pile. Should I resend it or have you already
scratched that?
Thanks for the reminder. It was marked as todo but fell
On Thu, Mar 05, 2015 at 03:03:04PM +0200, Stanimir Varbanov wrote:
Avoid the warning below triggered during dmaengine async device
registration.
WARNING: CPU: 1 PID: 1 at linux/drivers/dma/dmaengine.c:863
dma_async_device_register+0x2a8/0x4b8()
this driver doesn't support generic slave
On Wed, Mar 4, 2015 at 11:24 AM, Peter Hurley pe...@hurleysoftware.com wrote:
Cleanup the early DT/earlycon separation; remove the 'addr' parameter
from of_setup_earlycon() and get the uart phys addr directly with a
new wrapper function, of_flat_dt_translate_addr(). Limit
With multi platform support those sections could lead to unexpected
behavior if both ARCH_AT91 and another ARM SoC using the MACB IP are
selected.
Add two new capabilities to encode the default MII mode and the presence
of a CLKEN bit in USRIO register.
Then define the appropriate config for IPs
On Thu, 5 Mar 2015, Steven Rostedt wrote:
On Thu, 5 Mar 2015 16:56:43 +0100 (CET)
Miroslav Benes mbe...@suse.cz wrote:
I don't know if you plan to do something about this patch or if you just
missed it in your e-mail pile. Should I resend it or have you already
scratched that?
Some at91 SoCs embed a 10/100 Mbit Ethernet IP, that is based on the
at91sam9260 SoC.
Fix at91 DTs accordingly.
Signed-off-by: Boris Brezillon boris.brezil...@free-electrons.com
---
arch/arm/boot/dts/at91sam9260.dtsi | 2 +-
arch/arm/boot/dts/at91sam9263.dtsi | 2 +-
On Wed, Mar 4, 2015 at 11:24 AM, Peter Hurley pe...@hurleysoftware.com wrote:
commit 7914a7c5651a5 (of: support passing console options with
stdout-path) added options string support to the stdout-path property.
Handle the options string for earlycon as well.
Requires: libfdt: Teach
Michel Machado wrote:
Hi there,
We have been developing Linux XIA, a new network stack that
emphasizes evolvability and interoperability, for a couple of years, and
it has now reached a degree of maturity that allows others to experiment
with it.
From looking at your wiki, network
Hello,
This removes the #if defined(ARCH_AT91) sections to prevent any problem
when enabling ARM multi-platform support.
The at91 specific logic is now activated when the at91sam9260-macb
compatible string is found.
Best Regards,
Boris
Boris Brezillon (3):
net/macb: Update DT bindings
[+cc Mark]
On Thu, Feb 26, 2015 at 06:21:51PM -0600, Bjorn Helgaas wrote:
On Tue, Feb 17, 2015 at 03:14:00PM -0800, Feng Kan wrote:
The generic accessor functions for pci-xgene uses map_bus
call that returns the base address but did not add the additional
offset.
Signed-off-by: Feng
On Fri, Feb 20, 2015 at 05:58:44PM +0530, Tapasweni Pathak wrote:
Remove double check on chan-desc.
Found by Coccinelle.
Please use the right substem name in patches. Hint git log is your friend
Applied, now
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Fix build errors in pud_set_huge() and pmd_set_huge() in
asm-generic/pgtable.h on some architectures in linux-next
and -mm trees.
C-stype code needs be used under #ifndef __ASSEMBLY__.
Signed-off-by: Toshi Kani toshi.k...@hp.com
---
include/asm-generic/pgtable.h | 12 ++--
1 file
On 4 March 2015 at 20:32, Arnd Bergmann a...@arndb.de wrote:
This is my final piece of the puzzle for ARMv6/v7 multiplatform
support. In combination with the other patches that are now
at git://kernel.org/pub/scm/linux/kernel/git/arnd/playground.git
multiplatform-4.0-rc2 and the at91 and
SEC1 doesn't have IPSec descriptor, so all functions using that descriptor
are specific to SEC2. This patch moves them in a new talitos2.c file
dedicated to SEC2
We also move to talitos2.c all the functions that will be different for
SEC1, like the handling of mapping/unmapping of input/output
During init and reset, some actions are different between SEC1 and SEC2
This patch isolates them in small helper functions that we will be able
to redefine for SEC1
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 20
1 file changed, 16
On 03/05/2015 09:40 AM, Tony Lindgren wrote:
* Dave Gerlach d-gerl...@ti.com [150304 20:14]:
Dave,
Looks like the commit message disappeared during your patch preparation.
Signed-off-by: Suman Anna s-a...@ti.com
Signed-off-by: Dave Gerlach d-gerl...@ti.com
---
arch/arm/boot/dts/am33xx.dtsi
On Wed, Mar 04, 2015 at 04:22:30PM -0500, Konrad Rzeszutek Wilk wrote:
On Tue, Feb 24, 2015 at 01:34:06PM +0300, Vladimir Davydov wrote:
On Mon, Feb 23, 2015 at 11:12:22AM -0500, Konrad Rzeszutek Wilk wrote:
Thank you for posting these patches. I was wondering if you had
run through some
On Thu, 2015-03-05 at 20:35 +0800, kbuild test robot wrote:
Signed-off-by: Fengguang Wu fengguang...@intel.com
Thanks for the update!
Reviewed-by: Toshi Kani toshi.k...@hp.com
-Toshi
---
ioremap.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
This patch adds talitos1.c and talitos1.h with all specificities needed
to handle the SEC1 security engine found in MPC885 and MPC8272.
The SEC1 has several differences with its younger brother SEC2:
* Several bits in registers have different locations
* Many bits are missing
* Some bits are in
This patch refactors the handling of the input and output data that is quite
similar in several functions
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 163 ---
1 file changed, 85 insertions(+), 78 deletions(-)
Move interrupt related macros in talitos2.h as they are specific to SEC2
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 58 -
drivers/crypto/talitos2.h | 60 +++
2
The purpose of this set of patchs is to add to talitos crypto driver the
support for the SEC1 version of the security engine, which is found in
mpc885 and mpc8272 processors.
The approach has been to split the driver in two main parts:
* talitos.c and talitos.h contains parts that are common
*
Acked-by: Feng Kan f...@apm.com
On Wed, Mar 4, 2015 at 2:24 PM, Mark Salter msal...@redhat.com wrote:
Commit 350f8be5bb402 (PCI: xgene: Convert to use generic config
accessors) breaks PCI on the X-Gene platform. It creates two
problems with the xgene_pcie_map_bus() function. First, it returns
Vinod Koul vinod.k...@intel.com writes:
On Sun, Feb 15, 2015 at 07:49:16PM +0100, Robert Jarzmik wrote:
Fix the dmaengine complaint about missing slave caps :
- declare the available bus widths
- declare the available transfer types
- declare the residue calculation type
Applied,
On 03/05/2015 05:52 PM, Andres Freund wrote:
Hi,
On 2015-03-05 17:30:16 +0100, Vlastimil Babka wrote:
That however means the workload is based on hugetlbfs and shouldn't trigger
THP
page fault activity, which is the aim of this patchset. Some more googling
made
me recall that last
remap_pages is the lowlevel mm helper needed to implement
UFFDIO_REMAP.
Signed-off-by: Andrea Arcangeli aarca...@redhat.com
---
include/linux/userfaultfd_k.h | 17 ++
mm/huge_memory.c | 120 ++
mm/userfaultfd.c | 526 ++
Once an userfaultfd has been created and certain region of the process
virtual address space have been registered into it, the thread
responsible for doing the memory externalization can manage the page
faults in userland by talking to the kernel using the userfaultfd
protocol.
poll() can be used
userfaultfd needs to wake all waitqueues (pass 0 as nr parameter),
instead of the current hardcoded 1 (that would wake just the first
waitqueue in the head list).
Signed-off-by: Andrea Arcangeli aarca...@redhat.com
---
include/linux/wait.h | 5 +++--
kernel/sched/wait.c | 7 ---
Kernel header defining the methods needed by the VM common code to
interact with the userfaultfd.
Signed-off-by: Andrea Arcangeli aarca...@redhat.com
---
include/linux/userfaultfd_k.h | 79 +++
1 file changed, 79 insertions(+)
create mode 100644
These two flags gets set in vma-vm_flags to tell the VM common code
if the userfaultfd is armed and in which mode (only tracking missing
faults, only tracking wrprotect faults or both). If neither flags is
set it means the userfaultfd is not armed on the vma.
Signed-off-by: Andrea Arcangeli
As far as the rmap code is concerned, rmap_pages only alters the
page-mapping and page-index. It does it while holding the page
lock. However there are a few places that in presence of anon pages
are allowed to do rmap walks without the page lock (split_huge_page
and page_referenced_anon). Those
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