[PATCH 01/11] powerpc/8xx: remove remaining unnecessary code in FixupDAR

Since commit 33fb845a6f01 ("powerpc/8xx: Don't use MD_TWC for walk"), MD_EPN and MD_TWC are not writen anymore in FixupDAR so saving r3 has become useless. Signed-off-by: Christophe Leroy --- arch/powerpc/kernel/head_8xx.S | 6 -- 1 file changed, 6 deletions(-) diff --git

[PATCH 02/11] powerpc/8xx: remove tests on PGDIR entry validity

Kernel MMU handling code handles validity of entries via _PMD_PRESENT which corresponds to V bit in MD_TWC and MI_TWC. When the V bit is not set, MPC8xx triggers TLBError exception. So we don't have to check that and branch ourself to TLBError. We can set TLB entries with non present entries,

Re: [PATCH 1/2] drm: rockchip: Don't pass DRM fake offset to dma-api

On 2015年04月19日 00:55, Heiko Stübner wrote: Am Donnerstag, 16. April 2015, 16:41:51 schrieb Ørjan Eide: Set vm_pgoff to 0 after using it to look up the GEM node, before passing it on rockchip_gem_mmap_buf() where the offset must be from the start of the buffer. Passing in the fake offset

linux-next: manual merge of the akpm-current tree

Hi Andrew, Today's linux-next merge of the akpm-current tree got many conflicts in many files (presumably because most of this has been merged upstream). I just dropped the akpm-current tree for today. -- Cheers, Stephen Rothwells...@canb.auug.org.au pgpCZ8MshhXE_.pgp

Re: qemu:arm test failure due to commit 8053871d0f7f (smp: Fix smp_call_function_single_async() locking)

* Linus Torvalds wrote: > On Sun, Apr 19, 2015 at 11:01 AM, Ingo Molnar wrote: > > > > That's all fine and good, but why is an IPI sent to a non-existent > > CPU? It's not like we don't know which CPU is up and down. > > I agree that the qemu-arm behavior smells like a bug, plain and >

Re: [PATCH 1/2] drm: rockchip: Don't pass DRM fake offset to dma-api

On 2015年04月20日 13:34, Mark yao wrote: On 2015年04月19日 00:55, Heiko Stübner wrote: Am Donnerstag, 16. April 2015, 16:41:51 schrieb Ørjan Eide: Set vm_pgoff to 0 after using it to look up the GEM node, before passing it on rockchip_gem_mmap_buf() where the offset must be from the start of the

linux-next: Tree for Apr 20

Hi all, Please do not add any v4.2 material to your linux-next included trees until after v4.1-rc1 is released. Changes since 20150415: Dropped tree: akpm-current (too many conflicts) The s390 tree gained a conflict against Linus' tree. The xfs tree gaind a conflict against Linus' tree and a

[PATCH] input: cyapa: fix update suspend scanrate set to max 1000 issue

Fix update suspend scareate always set to max 1000 issue, the root cause is the missed using max_t as min_t. TEST=test on Chromebook. Signed-off-by: Dudley Du --- drivers/input/mouse/cyapa.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/input/mouse/cyapa.c

[PATCH RESEND v5 1/5] powerpc/8xx: macro for handling CPU15 errata

Having a macro will help keep clear code. Signed-off-by: Christophe Leroy --- arch/powerpc/kernel/head_8xx.S | 18 -- 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 9b53fe1..1279018 100644 ---

[PATCH RESEND v5 0/5] powerpc8xx: Further optimisation of TLB handling

This patchset provides a further optimisation of TLB handling in the 8xx. Changes are: - Not saving registers like CR when not needed - Adding support to any TASK_SIZE Only the last patch of the set is changed compared to v4 Resending with proper From: this time. Christophe Leroy (5):

[PATCH RESEND v5 3/5] powerpc/8xx: dont save CR in SCRATCH registers

CR only needs to be preserved when checking if we are handling a kernel address. So we can preserve CR in a register: - In ITLBMiss, check is done only when CONFIG_MODULES is defined. Otherwise we don't need to do anything at all with CR. - We use r10, then we reload SRR0/MD_EPN into r10 when CR

[PATCH RESEND v5 5/5] powerpc/8xx: Add support for TASK_SIZE greater than 0x80000000

By default, TASK_SIZE is set to 0x8000 for PPC_8xx, which is most likely sufficient for most cases. However, kernel configuration allows to set TASK_SIZE to another value, so the 8xx shall handle it. This patch also takes into account the case of PAGE_OFFSET lower than 0x8000, allthought

Re: [PATCH 00/11] powerpc8xx: Further optimisation of TLB handling

Le 20/04/2015 07:26, Christophe Leroy a écrit : This patchset provides a further optimisation of TLB handling in the 8xx. Main changes are based on: - Using processor handling of PGD/PTE Validity bits instead of testing ourselves the entries validity - Aligning PGD address to allow direct bit

[PATCH RESEND v5 4/5] powerpc/8xx: Use SPRG2 instead of DAR for saving r3

We now have SPRG2 available as in it not used anymore for saving CR, so we don't need to crash DAR anymore for saving r3 for CPU6 ERRATA handling. Signed-off-by: Christophe Leroy --- arch/powerpc/kernel/head_8xx.S | 9 - 1 file changed, 4 insertions(+), 5 deletions(-) diff --git

[PATCH RESEND v5 2/5] powerpc/8xx: Handle CR out of exception PROLOG/EPILOG

In order to be able to reduce scope during which CR is saved, we take CR saving/restoring out of exception PROLOG and EPILOG Signed-off-by: Christophe Leroy --- arch/powerpc/kernel/head_8xx.S | 10 +++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git

[PATCH 00/11] Convert the posix_clock_operations and k_clock structure to ready for 2038

This patch series changes the 32-bit time type (timespec/itimerspec) to the 64-bit one (timespec64/itimerspec64), since 32-bit time types will break in the year 2038. This patch series introduces new methods with timespec64/itimerspec64 type, and removes the old ones with timespec/itimerspec

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