Re: [PATCH v3 3/7] QE: Add uqe_serial document to bindings

On Tue, Mar 01, 2016 at 03:09:39PM +0800, Zhao Qiang wrote: > Add uqe_serial document to > Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.txt > > Signed-off-by: Zhao Qiang > --- > Changes for v2 > - modify tx/rx-clock-name specification > Changes for v2

Re: [PATCH 1/3] Documentation: dt: Add Broadcom iproc pwm controller binding

On Tue, Mar 01, 2016 at 12:42:47PM -0500, Yendapally Reddy Dhananjaya Reddy wrote: > Add a binding for Broadcom iproc pwm controller > > Signed-off-by: Yendapally Reddy Dhananjaya Reddy > > --- > Documentation/devicetree/bindings/pwm/brcm,kona-pwm.txt | 2 +- > 1 file changed, 1 insertion(+),

Re: [PATCH v3 4/7] bindings: move cpm_qe binding from powerpc/fsl to soc/fsl

On Tue, Mar 01, 2016 at 03:09:40PM +0800, Zhao Qiang wrote: > cpm_qe is supported on both powerpc and arm. > and the QE code has been moved from arch/powerpc into > drivers/soc/fsl, so move cpm_qe binding from powerpc/fsl > to soc/fsl > > Signed-off-by: Zhao Qiang > --- I already acked this. In

Re: [RFC v2 1/3] dt-bindings: soc: Add documentation for the MediaTek GCE unit

On Tue, Mar 01, 2016 at 09:29:14PM +0800, HS Liao wrote: > This adds documentation for the MediaTek Global Command Engine (GCE) unit > found in MT8173 SoCs. > > Signed-off-by: HS Liao > --- > .../devicetree/bindings/soc/mediatek/gce.txt | 34 > > 1 file changed, 34

Re: [PATCH 2/5] Documentation: dt: socfpga: Add Altera Arri10 L2 cache binding

On Tue, Mar 01, 2016 at 10:38:18AM -0600, ttha...@opensource.altera.com wrote: > From: Thor Thayer > > Add the device tree binding string needed to support the Altera L2 > cache on the Arria10 chip. > > Signed-off-by: Thor Thayer > --- > .../bindings/arm/altera/socfpga-eccmgr.txt |

Re: [PATCH v3 3/7] QE: Add uqe_serial document to bindings

On Tue, Mar 01, 2016 at 03:09:39PM +0800, Zhao Qiang wrote: > Add uqe_serial document to > Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.txt > > Signed-off-by: Zhao Qiang > --- > Changes for v2 > - modify tx/rx-clock-name specification > Changes for v2 > - NA > >

Re: [PATCH v3 2/7] QE: Add ucc hdlc document to bindings

On Tue, Mar 01, 2016 at 03:09:38PM +0800, Zhao Qiang wrote: > Add ucc hdlc document to > Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/network.txt > > Signed-off-by: Zhao Qiang > --- > Changes for v2 > - use ucc-hdlc instead of ucc_hdlc > - add more

Re: [PATCH v3 2/7] QE: Add ucc hdlc document to bindings

On Tue, Mar 01, 2016 at 03:09:38PM +0800, Zhao Qiang wrote: > Add ucc hdlc document to > Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/network.txt > > Signed-off-by: Zhao Qiang > --- > Changes for v2 > - use ucc-hdlc instead of ucc_hdlc > - add more information to properties.

Re: [PATCH v3 1/7] QE: Add IC, SI and SIRAM document to device tree bindings.

On Tue, Mar 01, 2016 at 03:09:37PM +0800, Zhao Qiang wrote: > Add IC, SI and SIRAM document of QE to > Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt > > Signed-off-by: Zhao Qiang > --- > Changes for v2 > - Add interrupt-controller in Required properties >

Re: [PATCH v3 1/7] QE: Add IC, SI and SIRAM document to device tree bindings.

On Tue, Mar 01, 2016 at 03:09:37PM +0800, Zhao Qiang wrote: > Add IC, SI and SIRAM document of QE to > Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt > > Signed-off-by: Zhao Qiang > --- > Changes for v2 > - Add interrupt-controller in Required properties > - delete

Re: [PATCH V5 01/15] ACPI: MCFG: Move mmcfg_list management to drivers/acpi

On Fri, Mar 04, 2016 at 02:05:56PM +0530, Jayachandran Chandrashekaran Nair wrote: > On Fri, Mar 4, 2016 at 4:21 AM, Bjorn Helgaas wrote: > > Hi Tomasz, Jayachandran, et al, > > > > On Tue, Feb 16, 2016 at 02:53:31PM +0100, Tomasz Nowicki wrote: > >> From: Jayachandran C

Re: [PATCH V5 01/15] ACPI: MCFG: Move mmcfg_list management to drivers/acpi

On Fri, Mar 04, 2016 at 02:05:56PM +0530, Jayachandran Chandrashekaran Nair wrote: > On Fri, Mar 4, 2016 at 4:21 AM, Bjorn Helgaas wrote: > > Hi Tomasz, Jayachandran, et al, > > > > On Tue, Feb 16, 2016 at 02:53:31PM +0100, Tomasz Nowicki wrote: > >> From: Jayachandran C > >> > >> Move

Re: [4/9] powerpc: inline ip_fast_csum()

On Tue, Sep 22, 2015 at 04:34:25PM +0200, Christophe Leroy wrote: > @@ -137,6 +130,45 @@ static inline __wsum csum_add(__wsum csum, __wsum addend) > #endif > } > > +/* > + * This is a version of ip_compute_csum() optimized for IP headers, > + * which always checksum on 4 octet boundaries. ihl

Re: [4/9] powerpc: inline ip_fast_csum()

On Tue, Sep 22, 2015 at 04:34:25PM +0200, Christophe Leroy wrote: > @@ -137,6 +130,45 @@ static inline __wsum csum_add(__wsum csum, __wsum addend) > #endif > } > > +/* > + * This is a version of ip_compute_csum() optimized for IP headers, > + * which always checksum on 4 octet boundaries. ihl

Re: [PATCH 2/2] isdn: i4l: move active-isdn drivers to staging

Hi Arnd, [auto build test WARNING on staging/staging-testing] [also build test WARNING on v4.5-rc6 next-20160304] [if your patch is applied to the wrong git tree, please drop us a note to help improving the system] url: https://github.com/0day-ci/linux/commits/Arnd-Bergmann/isdn-icn-remove

Re: [PATCH 2/2] isdn: i4l: move active-isdn drivers to staging

Hi Arnd, [auto build test WARNING on staging/staging-testing] [also build test WARNING on v4.5-rc6 next-20160304] [if your patch is applied to the wrong git tree, please drop us a note to help improving the system] url: https://github.com/0day-ci/linux/commits/Arnd-Bergmann/isdn-icn-remove

Re: [PATCH v6 0/3] fallocate for block devices to provide zero-out

On Fri, Mar 4, 2016 at 4:55 PM, Darrick J. Wong wrote: > > This is a redesign of the patch series that fixes various interface > problems with the existing "zero out this part of a block device" > code. BLKZEROOUT2 is gone. I replied to two of the patches with small

Re: [PATCH v6 0/3] fallocate for block devices to provide zero-out

On Fri, Mar 4, 2016 at 4:55 PM, Darrick J. Wong wrote: > > This is a redesign of the patch series that fixes various interface > problems with the existing "zero out this part of a block device" > code. BLKZEROOUT2 is gone. I replied to two of the patches with small nits, but on the whole I

Re: [PATCH 3/3] block: implement (some of) fallocate for block devices

On Fri, Mar 4, 2016 at 4:56 PM, Darrick J. Wong wrote: > + > + /* We can't change the bdev size from here */ > + if (!(mode & FALLOC_FL_KEEP_SIZE)) > + return -EOPNOTSUPP; Oh, and this I think is wrong. The thing is, FALLOC_FL_KEEP_SIZE is only

Re: [PATCH 3/3] block: implement (some of) fallocate for block devices

On Fri, Mar 4, 2016 at 4:56 PM, Darrick J. Wong wrote: > + > + /* We can't change the bdev size from here */ > + if (!(mode & FALLOC_FL_KEEP_SIZE)) > + return -EOPNOTSUPP; Oh, and this I think is wrong. The thing is, FALLOC_FL_KEEP_SIZE is only supposed to matter if

Re: [PATCH] mtd: nand: pxa3xx_nand: fix dmaengine initialization

On Fri, Feb 12, 2016 at 11:29:04PM +0100, Robert Jarzmik wrote: > When the driver is initialized in a pure device-tree platform, the > driver's probe fails allocating the dma channel : > [ 525.624435] pxa3xx-nand 4310.nand: no resource defined for data DMA > [ 525.632088] pxa3xx-nand

Re: [PATCH] mtd: nand: pxa3xx_nand: fix dmaengine initialization

On Fri, Feb 12, 2016 at 11:29:04PM +0100, Robert Jarzmik wrote: > When the driver is initialized in a pure device-tree platform, the > driver's probe fails allocating the dma channel : > [ 525.624435] pxa3xx-nand 4310.nand: no resource defined for data DMA > [ 525.632088] pxa3xx-nand

Re: [PATCH 3/3] block: implement (some of) fallocate for block devices

On Fri, Mar 4, 2016 at 4:56 PM, Darrick J. Wong wrote: > + /* Only punch if the device can do zeroing discard. */ > + if ((mode & FALLOC_FL_PUNCH_HOLE) && > + (!blk_queue_discard(q) || !q->limits.discard_zeroes_data)) > + return

Re: [PATCH 3/3] block: implement (some of) fallocate for block devices

On Fri, Mar 4, 2016 at 4:56 PM, Darrick J. Wong wrote: > + /* Only punch if the device can do zeroing discard. */ > + if ((mode & FALLOC_FL_PUNCH_HOLE) && > + (!blk_queue_discard(q) || !q->limits.discard_zeroes_data)) > + return -EOPNOTSUPP; I'm ok with this,

Re: [PATCH 2/3] block: require write_same and discard requests align to logical block size

On Fri, Mar 4, 2016 at 4:56 PM, Darrick J. Wong wrote: > > + bs_mask = (bdev_logical_block_size(bdev) >> 9) - 1; > + if ((sector & bs_mask) || ((sector + nr_sects) & bs_mask)) > + return -EINVAL; This test may _work_, but it's kind of crazily

Re: [PATCH 2/3] block: require write_same and discard requests align to logical block size

On Fri, Mar 4, 2016 at 4:56 PM, Darrick J. Wong wrote: > > + bs_mask = (bdev_logical_block_size(bdev) >> 9) - 1; > + if ((sector & bs_mask) || ((sector + nr_sects) & bs_mask)) > + return -EINVAL; This test may _work_, but it's kind of crazily overly complicated. The

Re: [PATCH 07/10] staging: lustre: add last missing sparse annotation __user

On Mar 4, 2016, at 9:09 PM, James Simmons wrote: > From: Frank Zago > > One of the __user was missed in being applied to upstream > client. This is broken out of patch 11819. It was not, the bug was fixed in another way. > Signed-off-by: Frank Zago >

Re: [PATCH 07/10] staging: lustre: add last missing sparse annotation __user

On Mar 4, 2016, at 9:09 PM, James Simmons wrote: > From: Frank Zago > > One of the __user was missed in being applied to upstream > client. This is broken out of patch 11819. It was not, the bug was fixed in another way. > Signed-off-by: Frank Zago > Intel-bug-id:

Re: [PATCH v11 17/24] perf config: Collect configs to handle config variables

On 03/04/2016 10:58 PM, Namhyung Kim wrote: Hi Taeung, On Fri, Mar 04, 2016 at 09:45:44PM +0900, Taeung Song wrote: Hi, Namhyung and all (I'm modifying this patch to be tidy) I have a mere question about name of a variable for current config list that contains section list which has

Re: [PATCH v11 17/24] perf config: Collect configs to handle config variables

On 03/04/2016 10:58 PM, Namhyung Kim wrote: Hi Taeung, On Fri, Mar 04, 2016 at 09:45:44PM +0900, Taeung Song wrote: Hi, Namhyung and all (I'm modifying this patch to be tidy) I have a mere question about name of a variable for current config list that contains section list which has

[RFC PATCH 1/2] percpu_counter: Allow falling back to global counter on large system

Per-cpu counters are used in quite a number of places within the kernel. On large system with a lot of CPUs, however, doing a percpu_counter_sum() can be very expensive as nr_cpu cachelines will need to be read. In __percpu_counter_compare(), the chance of calling percpu_counter_sum() also

[RFC PATCH 2/2] xfs: Allow degeneration of m_fdblocks/m_ifree to global counters

Small XFS filesystems on systems with large number of CPUs can incur a significant overhead due to excessive calls to the percpu_counter_sum() function which needs to walk through a large number of different cachelines. This patch uses the newly added percpu_counter_set_limit() API to potentially

[RFC PATCH 1/2] percpu_counter: Allow falling back to global counter on large system

Per-cpu counters are used in quite a number of places within the kernel. On large system with a lot of CPUs, however, doing a percpu_counter_sum() can be very expensive as nr_cpu cachelines will need to be read. In __percpu_counter_compare(), the chance of calling percpu_counter_sum() also

[RFC PATCH 2/2] xfs: Allow degeneration of m_fdblocks/m_ifree to global counters

Small XFS filesystems on systems with large number of CPUs can incur a significant overhead due to excessive calls to the percpu_counter_sum() function which needs to walk through a large number of different cachelines. This patch uses the newly added percpu_counter_set_limit() API to potentially

[RFC PATCH 0/2] percpu_counter: Enable switching to global counter

This patchset allows the degeneration of per-cpu counters back to global counters when: 1) The number of CPUs in the system is large, hence a high cost for calling percpu_counter_sum(). 2) The initial count value is small so that it has a high chance of excessive percpu_counter_sum()

[RFC PATCH 0/2] percpu_counter: Enable switching to global counter

This patchset allows the degeneration of per-cpu counters back to global counters when: 1) The number of CPUs in the system is large, hence a high cost for calling percpu_counter_sum(). 2) The initial count value is small so that it has a high chance of excessive percpu_counter_sum()

Re: [PATCH v5 00/26] memory: omap-gpmc: mtd: nand: Support GPMC NAND on non-OMAP platforms

On Mon, Feb 29, 2016 at 06:25:12PM +0200, Roger Quadros wrote: > On 19/02/16 23:15, Roger Quadros wrote: > > Hi, > > > > @Tony > > Patches 15 and 24 are new and will need your review. > > I've modified patch 22 to include the new am335x boards introduced since > > v4.4. > > > > Patches are

Re: [PATCH v5 00/26] memory: omap-gpmc: mtd: nand: Support GPMC NAND on non-OMAP platforms

On Mon, Feb 29, 2016 at 06:25:12PM +0200, Roger Quadros wrote: > On 19/02/16 23:15, Roger Quadros wrote: > > Hi, > > > > @Tony > > Patches 15 and 24 are new and will need your review. > > I've modified patch 22 to include the new am335x boards introduced since > > v4.4. > > > > Patches are

[PATCH v6 1/2] Documentation: bindings: add description of phy for sdhci-of-arasan

This patch adds phys and phy-names for sdhci-of-arasan as required properties for arasan,sdhci-5.1, and details the example as well. Signed-off-by: Shawn Lin Acked-by: Rob Herring --- Changes in v6: - add Rob's Acked-by tag Changes in v2: - Keep phy

[PATCH v6 2/2] mmc: sdhci-of-arasan: add phy support for sdhci-of-arasan

This patch adds Generic PHY access for sdhci-of-arasan. Driver can get PHY handler from dt-binding, and power-on/init the PHY. Currently, it's just mandatory for arasan,sdhci-5.1. Signed-off-by: Shawn Lin Serise-changes: 6 - rebase on Ulf's next - fix some preexisting

[PATCH v6 2/2] mmc: sdhci-of-arasan: add phy support for sdhci-of-arasan

This patch adds Generic PHY access for sdhci-of-arasan. Driver can get PHY handler from dt-binding, and power-on/init the PHY. Currently, it's just mandatory for arasan,sdhci-5.1. Signed-off-by: Shawn Lin Serise-changes: 6 - rebase on Ulf's next - fix some preexisting problems of err handling

[PATCH v6 1/2] Documentation: bindings: add description of phy for sdhci-of-arasan

This patch adds phys and phy-names for sdhci-of-arasan as required properties for arasan,sdhci-5.1, and details the example as well. Signed-off-by: Shawn Lin Acked-by: Rob Herring --- Changes in v6: - add Rob's Acked-by tag Changes in v2: - Keep phy as a mandatory requirement for

[PATCH v6 0/2] Add phy support for arasan,sdhci-5.1

Phy is mandatory requirement for arasan,sdhci-5.1, so we introduce generic phy support for sdhci-of-arasan. This version is rebased on Ulf's next to make it applied cleanly. Also, we fix some preexisting problems of err handling suggested by Adrian. Shawn Lin (2): Documentation: bindings: add

[PATCH v6 0/2] Add phy support for arasan,sdhci-5.1

Phy is mandatory requirement for arasan,sdhci-5.1, so we introduce generic phy support for sdhci-of-arasan. This version is rebased on Ulf's next to make it applied cleanly. Also, we fix some preexisting problems of err handling suggested by Adrian. Shawn Lin (2): Documentation: bindings: add

Re: [PATCH v5 09/26] mtd: nand: omap: Clean up device tree support

Sorry, another small thing I noticed. On Fri, Feb 19, 2016 at 11:15:31PM +0200, Roger Quadros wrote: > Move NAND specific device tree parsing to NAND driver. > > The NAND controller node must have a compatible id, register space > resource and interrupt resource. > > Signed-off-by: Roger

Re: [PATCH v5 09/26] mtd: nand: omap: Clean up device tree support

Sorry, another small thing I noticed. On Fri, Feb 19, 2016 at 11:15:31PM +0200, Roger Quadros wrote: > Move NAND specific device tree parsing to NAND driver. > > The NAND controller node must have a compatible id, register space > resource and interrupt resource. > > Signed-off-by: Roger

Re: [PATCH v3] net: jme: fix suspend/resume on JMC260

On Fri, Mar 4, 2016 at 1:32 AM, Diego Viola wrote: > On Thu, Mar 3, 2016 at 6:19 PM, Diego Viola wrote: >> On Thu, Mar 3, 2016 at 6:14 PM, Diego Viola wrote: >>> On Thu, Mar 3, 2016 at 2:55 AM, Diego Viola

Re: [PATCH v3 16/52] mtd: nand: use mtd_set_ecclayout() where appropriate

On Fri, Feb 26, 2016 at 01:57:24AM +0100, Boris Brezillon wrote: > Use the mtd_set_ecclayout() helper instead of directly assigning the > mtd->ecclayout field. > > Signed-off-by: Boris Brezillon > --- > drivers/mtd/nand/nand_base.c | 2 +- > 1 file changed, 1

Re: [PATCH v3] net: jme: fix suspend/resume on JMC260

On Fri, Mar 4, 2016 at 1:32 AM, Diego Viola wrote: > On Thu, Mar 3, 2016 at 6:19 PM, Diego Viola wrote: >> On Thu, Mar 3, 2016 at 6:14 PM, Diego Viola wrote: >>> On Thu, Mar 3, 2016 at 2:55 AM, Diego Viola wrote: On Thu, Mar 3, 2016 at 12:19 AM, Diego Viola wrote: > On Wed, Mar 2,

Re: [PATCH v3 16/52] mtd: nand: use mtd_set_ecclayout() where appropriate

On Fri, Feb 26, 2016 at 01:57:24AM +0100, Boris Brezillon wrote: > Use the mtd_set_ecclayout() helper instead of directly assigning the > mtd->ecclayout field. > > Signed-off-by: Boris Brezillon > --- > drivers/mtd/nand/nand_base.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > >

Re: [PATCH v2 2/3] libnvdimm, pmem: adjust for section collisions with 'System RAM'

On Fri, Mar 4, 2016 at 6:48 PM, Toshi Kani wrote: > On Thu, 2016-03-03 at 13:53 -0800, Dan Williams wrote: >> On a platform where 'Persistent Memory' and 'System RAM' are mixed >> within a given sparsemem section, trim the namespace and notify about the >> sub-optimal

Re: [PATCH v2 2/3] libnvdimm, pmem: adjust for section collisions with 'System RAM'

On Fri, Mar 4, 2016 at 6:48 PM, Toshi Kani wrote: > On Thu, 2016-03-03 at 13:53 -0800, Dan Williams wrote: >> On a platform where 'Persistent Memory' and 'System RAM' are mixed >> within a given sparsemem section, trim the namespace and notify about the >> sub-optimal alignment. >> >> Cc: Toshi

Re: [RFT PATCH 1/2] usb: dwc2: Add a 10 ms delay to dwc2_core_reset()

On 3/4/2016 10:23 AM, Douglas Anderson wrote: > From testing and trying to make sense of the documentation, it appears > that a 10 ms delay is needed after resetting the core to make sure that > everything is stable and consistent. Let's add it. > > In my testing (on rk3288) this allows us to

Re: [RFT PATCH 1/2] usb: dwc2: Add a 10 ms delay to dwc2_core_reset()

On 3/4/2016 10:23 AM, Douglas Anderson wrote: > From testing and trying to make sense of the documentation, it appears > that a 10 ms delay is needed after resetting the core to make sure that > everything is stable and consistent. Let's add it. > > In my testing (on rk3288) this allows us to

Re: [PATCH] cxgbit: fix dma_addr_t printk format

On Sat, 2016-03-05 at 01:34 +0100, Arnd Bergmann wrote: > On Friday 04 March 2016 16:25:07 Joe Perches wrote: > > > diff --git a/drivers/target/iscsi/cxgbit/cxgbit_ddp.c > > > b/drivers/target/iscsi/cxgbit/cxgbit_ddp.c [] > > > @@ -179,7 +179,7 @@ cxgbit_dump_sgl(const char *cap, struct

Re: [PATCH] cxgbit: fix dma_addr_t printk format

On Sat, 2016-03-05 at 01:34 +0100, Arnd Bergmann wrote: > On Friday 04 March 2016 16:25:07 Joe Perches wrote: > > > diff --git a/drivers/target/iscsi/cxgbit/cxgbit_ddp.c > > > b/drivers/target/iscsi/cxgbit/cxgbit_ddp.c [] > > > @@ -179,7 +179,7 @@ cxgbit_dump_sgl(const char *cap, struct

[PATCH 04/10] staging: lustre: fix 'NULL pointer dereference' errors

From: Sebastien Buisson Fix 'NULL pointer dereference' defects found by Coverity version 6.5.3: Dereference after null check (FORWARD_NULL) For instance, Passing null pointer to a function which dereferences it. Dereference before null check (REVERSE_INULL) Null-checking

[PATCH 05/10] staging: lustre: fix 'data race condition' issue in framework.c

From: Sebastien Buisson Fix 'data race condition' defects found by Coverity version 6.5.0: Data race condition (MISSING_LOCK) Accessing variable without holding lock. Elsewhere, this variable is accessed with lock held. Signed-off-by: Sebastien Buisson

[PATCH 04/10] staging: lustre: fix 'NULL pointer dereference' errors

From: Sebastien Buisson Fix 'NULL pointer dereference' defects found by Coverity version 6.5.3: Dereference after null check (FORWARD_NULL) For instance, Passing null pointer to a function which dereferences it. Dereference before null check (REVERSE_INULL) Null-checking variable suggests that

[PATCH 05/10] staging: lustre: fix 'data race condition' issue in framework.c

From: Sebastien Buisson Fix 'data race condition' defects found by Coverity version 6.5.0: Data race condition (MISSING_LOCK) Accessing variable without holding lock. Elsewhere, this variable is accessed with lock held. Signed-off-by: Sebastien Buisson Intel-bug-id:

[PATCH 02/10] staging: lustre: LNet network latency simulation

From: Liang Zhen Incoming lnet message can be delayed for seconds if it can match any of LNet Delay Rules. User can add/remove/list Delay Rule by lctl commands: - lctl net_delay_add Add a new Delay Rule to LNet, options <-s | --source SRC_NID> <-d | --dest DST_NID>

[PATCH 02/10] staging: lustre: LNet network latency simulation

From: Liang Zhen Incoming lnet message can be delayed for seconds if it can match any of LNet Delay Rules. User can add/remove/list Delay Rule by lctl commands: - lctl net_delay_add Add a new Delay Rule to LNet, options <-s | --source SRC_NID> <-d | --dest DST_NID> <<-r | --rate

[PATCH 06/10] staging: lustre: Correct missing newline

From: James Nunez Several error messages are missing newline characters at the end of the message. Newlines are added where necessary and other minor corrections; no punctuation at the end of an error message, add a return code to the end of error messages, device name

[PATCH 07/10] staging: lustre: add last missing sparse annotation __user

From: Frank Zago One of the __user was missed in being applied to upstream client. This is broken out of patch 11819. Signed-off-by: Frank Zago Intel-bug-id: https://jira.hpdd.intel.com/browse/LU-5396 Reviewed-on: http://review.whamcloud.com/11819 Reviewed-by:

[PATCH 08/10] staging: lustre: change test to asser in LNetGetId

The ln_refcount test was changed into an assert. Signed-off-by: James Simmons --- drivers/staging/lustre/lnet/lnet/api-ni.c |4 +--- 1 files changed, 1 insertions(+), 3 deletions(-) diff --git a/drivers/staging/lustre/lnet/lnet/api-ni.c

[PATCH 06/10] staging: lustre: Correct missing newline

From: James Nunez Several error messages are missing newline characters at the end of the message. Newlines are added where necessary and other minor corrections; no punctuation at the end of an error message, add a return code to the end of error messages, device name at the beginning, etc.

[PATCH 07/10] staging: lustre: add last missing sparse annotation __user

From: Frank Zago One of the __user was missed in being applied to upstream client. This is broken out of patch 11819. Signed-off-by: Frank Zago Intel-bug-id: https://jira.hpdd.intel.com/browse/LU-5396 Reviewed-on: http://review.whamcloud.com/11819 Reviewed-by: James Simmons Reviewed-by:

[PATCH 08/10] staging: lustre: change test to asser in LNetGetId

The ln_refcount test was changed into an assert. Signed-off-by: James Simmons --- drivers/staging/lustre/lnet/lnet/api-ni.c |4 +--- 1 files changed, 1 insertions(+), 3 deletions(-) diff --git a/drivers/staging/lustre/lnet/lnet/api-ni.c b/drivers/staging/lustre/lnet/lnet/api-ni.c index

[PATCH 03/10] staging: lustre: fix 'data race condition' issue in conrpc.c

From: Sebastien Buisson Fix 'data race condition' defects found by Coverity version 6.5.0: Data race condition (MISSING_LOCK) Accessing variable without holding lock. Elsewhere, this variable is accessed with lock held. Signed-off-by: Sebastien Buisson

[PATCH 03/10] staging: lustre: fix 'data race condition' issue in conrpc.c

From: Sebastien Buisson Fix 'data race condition' defects found by Coverity version 6.5.0: Data race condition (MISSING_LOCK) Accessing variable without holding lock. Elsewhere, this variable is accessed with lock held. Signed-off-by: Sebastien Buisson Intel-bug-id:

Re: [PATCH v5 09/26] mtd: nand: omap: Clean up device tree support

A couple of sparse warnings. On Fri, Feb 19, 2016 at 11:15:31PM +0200, Roger Quadros wrote: > Move NAND specific device tree parsing to NAND driver. > > The NAND controller node must have a compatible id, register space > resource and interrupt resource. > > Signed-off-by: Roger Quadros

Re: [PATCH v5 09/26] mtd: nand: omap: Clean up device tree support

A couple of sparse warnings. On Fri, Feb 19, 2016 at 11:15:31PM +0200, Roger Quadros wrote: > Move NAND specific device tree parsing to NAND driver. > > The NAND controller node must have a compatible id, register space > resource and interrupt resource. > > Signed-off-by: Roger Quadros > ---

[PATCH 10/10] staging: lustre: make LNet use lprocfs_call_handler

Sometime ago a patch was submitted to duplicate the proc_call_handler code in the LNet layer. This was due to the thinking libcfs was not used by the LNet layer. This was a wrong assumption so lets make LNet use the lprocfs_call_handler from the libcfs layer. Signed-off-by: James Simmons

[PATCH 09/10] staging: lustre: rename proc_call_handler to lprocfs_call_handler

Using proc_call_handler as a function name is way too generic. Rename to lprocfs_call_handler to avoid possible collisions. Signed-off-by: James Simmons --- drivers/staging/lustre/lustre/libcfs/module.c | 18 +- 1 files changed, 9 insertions(+), 9

[PATCH 10/10] staging: lustre: make LNet use lprocfs_call_handler

Sometime ago a patch was submitted to duplicate the proc_call_handler code in the LNet layer. This was due to the thinking libcfs was not used by the LNet layer. This was a wrong assumption so lets make LNet use the lprocfs_call_handler from the libcfs layer. Signed-off-by: James Simmons ---

[PATCH 09/10] staging: lustre: rename proc_call_handler to lprocfs_call_handler

Using proc_call_handler as a function name is way too generic. Rename to lprocfs_call_handler to avoid possible collisions. Signed-off-by: James Simmons --- drivers/staging/lustre/lustre/libcfs/module.c | 18 +- 1 files changed, 9 insertions(+), 9 deletions(-) diff --git

[PATCH 01/10] staging: lustre: LNet drop rule implementation

From: Liang Zhen This is implementation of LNet Drop Rule, which can randomly drop LNet messages at specified rate. LNet Drop Rule can only be applied to receive side of message. User can add drop_rule either on end point of cluster (client/server) or on LNet routers.

[PATCH 00/10] Last batch of fixes for LNet

This batch merges the remaining LNet patches from the OpenSFS branch for the upstream client. Once merged the LNet code will be up to date with the latest production code. Only style issues are remaining. Still future patches being developed for LNet will be landed to the upstream client as soon

[PATCH 01/10] staging: lustre: LNet drop rule implementation

From: Liang Zhen This is implementation of LNet Drop Rule, which can randomly drop LNet messages at specified rate. LNet Drop Rule can only be applied to receive side of message. User can add drop_rule either on end point of cluster (client/server) or on LNet routers. Here are lctl command to

[PATCH 00/10] Last batch of fixes for LNet

This batch merges the remaining LNet patches from the OpenSFS branch for the upstream client. Once merged the LNet code will be up to date with the latest production code. Only style issues are remaining. Still future patches being developed for LNet will be landed to the upstream client as soon

Re: [PATCH v5 10/26] mtd: nand: omap: Update DT binding documentation

On Fri, Feb 19, 2016 at 11:15:32PM +0200, Roger Quadros wrote: > Add compatible id and interrupts. The NAND interrupts are > provided by the GPMC controller node. > > Signed-off-by: Roger Quadros > --- > Documentation/devicetree/bindings/mtd/gpmc-nand.txt | 17 + >

Re: [PATCH v5 10/26] mtd: nand: omap: Update DT binding documentation

On Fri, Feb 19, 2016 at 11:15:32PM +0200, Roger Quadros wrote: > Add compatible id and interrupts. The NAND interrupts are > provided by the GPMC controller node. > > Signed-off-by: Roger Quadros > --- > Documentation/devicetree/bindings/mtd/gpmc-nand.txt | 17 + > 1 file

Re: [PATCH v2 2/3] libnvdimm, pmem: adjust for section collisions with 'System RAM'

On Thu, 2016-03-03 at 13:53 -0800, Dan Williams wrote: > On a platform where 'Persistent Memory' and 'System RAM' are mixed > within a given sparsemem section, trim the namespace and notify about the > sub-optimal alignment. > > Cc: Toshi Kani > Cc: Ross Zwisler

Re: [RESEND PATCH v5 2/2] mmc: sdhci-of-arasan: add phy support for sdhci-of-arasan

Hi Adrian, On 2016/3/4 20:12, Adrian Hunter wrote: [...] I don't know that disabling clocks is necessarily the right thing to do if the resume fails. You might want to consider what happens if the system tries to use the device when it is in that state. It's been a long time since I did

Re: [PATCH v2 2/3] libnvdimm, pmem: adjust for section collisions with 'System RAM'

On Thu, 2016-03-03 at 13:53 -0800, Dan Williams wrote: > On a platform where 'Persistent Memory' and 'System RAM' are mixed > within a given sparsemem section, trim the namespace and notify about the > sub-optimal alignment. > > Cc: Toshi Kani > Cc: Ross Zwisler > Signed-off-by: Dan Williams >

Re: [RESEND PATCH v5 2/2] mmc: sdhci-of-arasan: add phy support for sdhci-of-arasan

Hi Adrian, On 2016/3/4 20:12, Adrian Hunter wrote: [...] I don't know that disabling clocks is necessarily the right thing to do if the resume fails. You might want to consider what happens if the system tries to use the device when it is in that state. It's been a long time since I did

Re: [PATCH] platform/chrome: Add Chrome OS keyboard backlight LEDs support

On Fri, Mar 4, 2016 at 5:23 PM, Dmitry Torokhov wrote: > This is a driver for ACPI-based keyboard backlight LEDs found on > Chromebooks. The driver locates \\_SB.KBLT ACPI device and exports > backlight as "chromeos::kbd_backlight" LED class device in sysfs. > >

Re: [PATCH] platform/chrome: Add Chrome OS keyboard backlight LEDs support

On Fri, Mar 4, 2016 at 5:23 PM, Dmitry Torokhov wrote: > This is a driver for ACPI-based keyboard backlight LEDs found on > Chromebooks. The driver locates \\_SB.KBLT ACPI device and exports > backlight as "chromeos::kbd_backlight" LED class device in sysfs. > > Signed-off-by: Simon Que >

Re: [PATCH v5 17/26] mtd: nand: omap2: Implement NAND ready using gpiolib

+ Boris On Fri, Feb 19, 2016 at 11:15:39PM +0200, Roger Quadros wrote: > The GPMC WAIT pin status are now available over gpiolib. > Update the omap_dev_ready() function to use gpio instead of > directly accessing GPMC register space. > > Signed-off-by: Roger Quadros > --- >

Re: [PATCH v5 17/26] mtd: nand: omap2: Implement NAND ready using gpiolib

+ Boris On Fri, Feb 19, 2016 at 11:15:39PM +0200, Roger Quadros wrote: > The GPMC WAIT pin status are now available over gpiolib. > Update the omap_dev_ready() function to use gpio instead of > directly accessing GPMC register space. > > Signed-off-by: Roger Quadros > --- >

Re: [PATCH v5 03/26] memory: omap-gpmc: Introduce GPMC to NAND interface

Hi Roger, On Fri, Feb 19, 2016 at 11:15:25PM +0200, Roger Quadros wrote: > The OMAP GPMC module has certain registers dedicated for NAND > access and some NAND bits mixed with other GPMC functionality. > > For the NAND dedicated registers we have the struct gpmc_nand_regs. > > The NAND driver

Re: [PATCH v5 03/26] memory: omap-gpmc: Introduce GPMC to NAND interface

Hi Roger, On Fri, Feb 19, 2016 at 11:15:25PM +0200, Roger Quadros wrote: > The OMAP GPMC module has certain registers dedicated for NAND > access and some NAND bits mixed with other GPMC functionality. > > For the NAND dedicated registers we have the struct gpmc_nand_regs. > > The NAND driver

[PATCH] platform/chrome: Add Chrome OS keyboard backlight LEDs support

This is a driver for ACPI-based keyboard backlight LEDs found on Chromebooks. The driver locates \\_SB.KBLT ACPI device and exports backlight as "chromeos::kbd_backlight" LED class device in sysfs. Signed-off-by: Simon Que Signed-off-by: Duncan Laurie

[PATCH] platform/chrome: Add Chrome OS keyboard backlight LEDs support

This is a driver for ACPI-based keyboard backlight LEDs found on Chromebooks. The driver locates \\_SB.KBLT ACPI device and exports backlight as "chromeos::kbd_backlight" LED class device in sysfs. Signed-off-by: Simon Que Signed-off-by: Duncan Laurie Signed-off-by: Dmitry Torokhov ---

[PATCH] mtd: nand: check status before reporting timeout

In commit b70af9bef49b ("mtd: nand: increase ready wait timeout and report timeouts"), we increased the likelihood of scheduling during nand_wait(). This makes us more likely to hit the time_before(...) condition, since a lot of time may pass before we get scheduled again. Now, the loop was

[PATCH] mtd: nand: check status before reporting timeout

In commit b70af9bef49b ("mtd: nand: increase ready wait timeout and report timeouts"), we increased the likelihood of scheduling during nand_wait(). This makes us more likely to hit the time_before(...) condition, since a lot of time may pass before we get scheduled again. Now, the loop was

Re: [RFT PATCH 1/2] usb: dwc2: Add a 10 ms delay to dwc2_core_reset()

Hi, On Fri, Mar 4, 2016 at 4:33 PM, Doug Anderson wrote: > Michael, > > On Fri, Mar 4, 2016 at 4:09 PM, Michael Niewoehner > wrote: From testing and trying to make sense of the documentation, it appears that a 10 ms delay is needed after

Re: [RFT PATCH 1/2] usb: dwc2: Add a 10 ms delay to dwc2_core_reset()

Hi, On Fri, Mar 4, 2016 at 4:33 PM, Doug Anderson wrote: > Michael, > > On Fri, Mar 4, 2016 at 4:09 PM, Michael Niewoehner > wrote: From testing and trying to make sense of the documentation, it appears that a 10 ms delay is needed after resetting the core to make sure that

[GIT PULL] libnvdimm, nfit: fix for 4.5-rc7

Hi Linus, please pull from:   git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm libnvdimm-fixes ...to receive one straggling fix for NVDIMM support. The KVM/QEMU enabling for NVDIMMs has recently reached the point where it is able to accept some ACPI _DSM requests from a guest VM.  

[GIT PULL] libnvdimm, nfit: fix for 4.5-rc7

Hi Linus, please pull from:   git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm libnvdimm-fixes ...to receive one straggling fix for NVDIMM support. The KVM/QEMU enabling for NVDIMMs has recently reached the point where it is able to accept some ACPI _DSM requests from a guest VM.  

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