Hi,
Can someone explain to me what is the difference between put_page and
release_pages and which one should be used when ?
To explain my case:
We have a PCIe driver than transfers data between user process (read/write
scalls) to a PCI device, using DMA.
We followed the DMA guide so the code
On Thu, 29 Sep 2016 21:24:04 +0200
Christoph Hellwig wrote:
> On Thu, Sep 29, 2016 at 01:21:01PM -0600, Alex Williamson wrote:
> > Sorry for the delay, slipped by me. Overall a really nice cleanup.
> > One tiny nit, the commit log mis-names the function as
> >
On Thu, 2016-09-29 at 08:01 -0700, Joe Perches wrote:
> $Constant there is any number and the match regex is
> any upper case variable.
Why doesn't that regex match on "ORIGIN_HASH_SIZE"?
Paul Bolle
Hi,
On Thu, Sep 29, 2016 at 06:31:55PM +0200, Bartosz Golaszewski wrote:
> Default memory settings of da850 do not meet the throughput/latency
> requirements of tilcdc. This results in the image displayed being
> incorrect and the following warning being displayed by the LCDC
> drm driver:
>
>
On Sun, 11 Sep 2016 15:31:26 +0200
Christoph Hellwig wrote:
> Simply the interrupt setup by using the new PCI layer helpers.
>
> Signed-off-by: Christoph Hellwig
> ---
> drivers/vfio/pci/vfio_pci_intrs.c | 45
> +
>
Hi Lee,
[add Rob and Mark]
> Lee Jones hat am 29. September 2016 um 19:15
> geschrieben:
>
>
> On Thu, 29 Sep 2016, Stefan Wahren wrote:
> > > Lee Jones hat am 28. September 2016 um 03:05
> > > geschrieben:
> > >
> > >
> > > On Sat, 17 Sep 2016,
On Thu, 29 Sep 2016, Paul E. McKenney wrote:
> On Thu, Sep 29, 2016 at 08:44:39PM +0200, Peter Zijlstra wrote:
> > How about something like so on PPC?
> >
> > P0(int *x, int *y)
> > {
> > WRITE_ONCE(*x, 1);
> > smp_store_release(y, 1);
> > }
> >
> > P1(int *x, int *y)
> > {
> >
Page mappings with full RWX permissions are a security risk. x86
has an option to walk the page tables and dump any bad pages.
(See e1a58320a38d ("x86/mm: Warn on W^X mappings")). Add a similar
implementation for arm64.
Signed-off-by: Laura Abbott
---
Mimi Zohar writes:
> The TPM PCRs are only reset on a hard reboot. In order to validate a
> TPM's quote after a soft reboot (eg. kexec -e), the IMA measurement list
> of the running kernel must be saved and then restored on the subsequent
> boot, possibly of a
> Another possible optimization: when delivering an IPI, don't write the
> vector to PIR, but directly to VIRR. If the guest is not in VMX
> non-root mode, then vm entry will take care of the injection; in the
> other case, we'll send POSTED_INTR_VECTOR.
> It seems that we don't even have to set
On Thu, 2016-09-29 at 14:21 -0700, Joe Perches wrote:
> > > It doesn't matter match either way to me.
> > Why does this stop you fixing an apparently wrong checkpatch rule,
> > crude as parts of it are (ie, uppercase identifier must be a
> > constant)?
>
> It doesn't. It just doesn't matter much
Thiago Jung Bauermann writes:
> Hello Eric,
>
> Am Dienstag, 20 September 2016, 11:07:29 schrieb Eric W. Biederman:
>> A semi-generic concept called a hand-over buffer seems to be a
>> construction of infrustructure for no actual reason that will just
>> result in
On Thu, Sep 29, 2016 at 1:55 AM, wrote:
> On 28.09.2016 18:39, Dmitry Torokhov wrote:
>>
>> On Tue, Sep 27, 2016 at 4:38 PM, Roderick Colenbrander
>> wrote:
>>>
>>> From: Roderick Colenbrander
>>>
>>> This patch
Andrew Morton writes:
> On Thu, 29 Sep 2016 17:44:10 -0300 Thiago Jung Bauermann
> wrote:
>
>> Hello Andrew,
>>
>> You have in the -mm tree a version of the "kexec handover buffer" and "ima
>> carry measurement list" patches that were
On Thu, 29 Sep 2016, Moritz Fischer wrote:
> Hi Alan,
>
> On Wed, Sep 28, 2016 at 11:22 AM, Alan Tull
> wrote:
>
> > +static void socfpga_a10_fpga_generate_dclks(struct a10_fpga_priv *priv,
> > + u32 count)
> > +{
> > +
Hi Sinan,
On Fri, Sep 16, 2016 at 04:06:32PM -0400, Sinan Kaya wrote:
> Device states on the bus are saved and restored for all bus resets except
> the one initiated through pci_dev_reset. Filling the hole.
>
> Signed-off-by: Sinan Kaya
> ---
> drivers/pci/pci.c | 14
On Wed, Sep 28, 2016 at 11:21 AM, Alan Tull wrote:
> Add documentation for new FPGA bridge class's sysfs interface.
>
> Signed-off-by: Alan Tull
Acked-by: Moritz Fischer
Thiago Jung Bauermann writes:
> Am Donnerstag, 29 September 2016, 14:02:06 schrieb Andrew Morton:
>> On Thu, 29 Sep 2016 17:44:10 -0300 Thiago Jung Bauermann
> wrote:
>> > Hello Andrew,
>> >
>> > You have in the -mm tree a version of
On 27 September 2016 at 11:24, Arend Van Spriel
wrote:
> On 26-9-2016 14:38, Rafał Miłecki wrote:
>> On 26 September 2016 at 14:13, Rafał Miłecki wrote:
>>> On 26 September 2016 at 13:46, Arend Van Spriel
>>> wrote:
There is a existing tip as below.
If you have debuginfo enabled, try: perf report -s sym,srcline
However this tip only describe a condition to use --sort sym,scrline options.
So there is lack of explanation in the tip. I think that it would be better to
add a tip that exactly explain the
On Thu, Sep 29, 2016 at 03:36:38PM -0400, Alan Stern wrote:
> On Thu, 29 Sep 2016, Paul E. McKenney wrote:
>
> > On Thu, Sep 29, 2016 at 08:44:39PM +0200, Peter Zijlstra wrote:
>
> > > How about something like so on PPC?
> > >
> > > P0(int *x, int *y)
> > > {
> > > WRITE_ONCE(*x, 1);
> > >
On Thu, 2016-09-29 at 13:24 -0700, Joe Perches wrote:
> On Thu, 2016-09-29 at 21:43 +0200, Paul Bolle wrote:
> > Why doesn't that regex match on "ORIGIN_HASH_SIZE"?
>
> It does match.
If that regex does match, it being part of a negative test, the
specific checkpatch rule should be silent,
On Mon, Sep 26, 2016 at 4:49 AM, Wanpeng Li wrote:
> From: Wanpeng Li
>
> WARNING: CPU: 0 PID: 3331 at arch/x86/entry/common.c:45
> enter_from_user_mode+0x32/0x50
> CPU: 0 PID: 3331 Comm: ldt_gdt_64 Not tainted 4.8.0-rc7+ #13
> Call Trace:
>
On Thu, 29 Sep 2016 17:44:10 -0300 Thiago Jung Bauermann
wrote:
> Hello Andrew,
>
> You have in the -mm tree a version of the "kexec handover buffer" and "ima
> carry measurement list" patches that were NAKed by Eric Biederman. I would
> just like to double-check
The previous patch has adjusted async compaction so that it helps against
longterm fragmentation when compacting for a non-MOVABLE high-order allocation.
The goal of this patch is to force such allocations go through compaction
once before being allowed to fallback to a pageblock of different
On Thu, 2016-09-29 at 13:56 -0700, Joe Perches wrote:
> It doesn't matter match either way to me.
>
> The case for the unnecessary multiply with <= gcc 4.8 was
> removed with:
>
> commit 91c6a05f72a996bee5133e76374ab3ad7d3b9b72
> Author: Alexey Dobriyan
> Date: Tue Jul 26
Am Donnerstag, 29 September 2016, 14:02:06 schrieb Andrew Morton:
> On Thu, 29 Sep 2016 17:44:10 -0300 Thiago Jung Bauermann
wrote:
> > Hello Andrew,
> >
> > You have in the -mm tree a version of the "kexec handover buffer" and
> > "ima carry measurement list"
On Thu, Sep 29, 2016 at 9:47 AM, Vineet Gupta
wrote:
> On 09/28/2016 11:43 PM, Peter Zijlstra wrote:
>> On Wed, Sep 28, 2016 at 06:20:29PM -0700, Vineet Gupta wrote:
>>> On 09/28/2016 03:26 PM, Andy Lutomirski wrote:
>
>>
>>
>> userirq nmi
>>
>> |
Hi Muhammad,
On Thu, 2016-09-29 at 12:26:13 +0200, Muhammad Abdul WAHAB wrote:
> The Coresight components are present on the Zynq SoC but the corresponding
> device tree entries are missing. This patch adds device tree entries for
> coresight components while explaining how it was done in order
On Thu, Jul 21, 2016 at 07:52:43PM -0400, Paul Gortmaker wrote:
> A new i386-allmodconfig fail showed up relating to VDSO:
>
> I tried to reproduce it locally with x86-64 build host and could
> not, so I wonder if it is a missing HOSTCC vs. CC since next
> coverage is power host...
>
> VDSO2C
perf_config_set__init() check state of user config file
before opening it. But there is a bug when checking uid
and euid of current user. Although current user have superuser
permission, a error occurs as below.
Before:
user01@localhost:~$ ls -l ~/.perfconfig
-rw-rw-r-- 1 user01 user01 89
On Thu, 2016-09-29 at 21:43 +0200, Paul Bolle wrote:
> On Thu, 2016-09-29 at 08:01 -0700, Joe Perches wrote:
> > $Constant there is any number and the match regex is
> > any upper case variable.
> Why doesn't that regex match on "ORIGIN_HASH_SIZE"?
It does match.
Did you see my earlier email?
$
Hi Guenter,
> -Original Message-
> From: linux-usb-ow...@vger.kernel.org [mailto:linux-usb-
> ow...@vger.kernel.org] On Behalf Of Guenter Roeck
> Sent: Wednesday, August 24, 2016 5:11 AM
> To: Felipe Balbi
> Cc: Chandra Sekhar Anagani
On Thu, Sep 29, 2016 at 08:44:39PM +0200, Peter Zijlstra wrote:
> On Thu, Sep 29, 2016 at 11:10:15AM -0700, Paul E. McKenney wrote:
> > > >
> > > > P0(int *x, int *y)
> > > > {
> > > > WRITE_ONCE(*x, 1);
> > > > smp_wmb();
> > > >
On Thu, Sep 29, 2016 at 01:21:01PM -0600, Alex Williamson wrote:
> Sorry for the delay, slipped by me. Overall a really nice cleanup.
> One tiny nit, the commit log mis-names the function as
> pci_irq_allocate_vectors instead of pci_alloc_irq_vectors. With that,
>
> Acked-by: Alex Williamson
> -Original Message-
> From: Arvind Yadav [mailto:arvind.yadav...@gmail.com]
> Sent: Wednesday, September 28, 2016 5:45 AM
> To: le...@freescale.com; z...@zh-kernel.org; vinod.k...@intel.com
> Cc: dan.j.willi...@intel.com; linuxppc-...@lists.ozlabs.org;
> dmaeng...@vger.kernel.org;
We use __read_cr4() vs __read_cr4_safe() inconsistently. On
CR4-less CPUs, all CR4 bits are effectively clear, so we can make
the code simpler and more robust by making __read_cr4() always fix
up faults on 32-bit kernels.
This may fix some bugs on old 486-like CPUs, but I don't have any
easy way
Hi Ingo, etc:
Patch 1 fixes a boot regressions that's new in 4.8.
Patch 2 cleans the whole mess up. It's probably not 4.8 material,
but I'm sending it as part of this series for ease of review. If
you like, you could apply patch 1 to x86/urgent, merge into x86/asm,
and apply patch 3 on top.
Hi,
On Thu, Sep 22, 2016 at 5:12 PM, Shawn Lin wrote:
> When introducing hs400es, I didn't notice that we haven't
> switched voltage to 1V2 or 1V8 for it. That happens to work
> as the first controller claiming to support hs400es, arasan(5.1),
> which is designed to
Hi,
On Thu, Sep 22, 2016 at 5:03 PM, Shawn Lin wrote:
> Per the vendor's requirement, we shouldn't do any setting for
> 1.8V Signaling Enable, otherwise the interaction/behaviour between
> phy and controller will be undefined. Mostly it works fine if we do
> that, but
The condition for reading CR4 was wrong: there are some CPUs with
CPUID but not CR4. Rather than trying to make the condition exact,
using __read_cr4_safe().
Reported-by: da...@saggiorato.net
Fixes: 18bc7bd523e0 ("x86/boot: Synchronize trampoline_cr4_features and
mmu_cr4_features directly")
2016-09-27 23:20+0200, Paolo Bonzini:
> The difficult one is patch 2. I find the new code easier to follow than
> the old one, but it doesn't mean it works. :) The aim is for APICv to
> not use KVM_REQ_EVENT at all for interrupts, therefore turning APICv's
> weakness (having to look at PIR on
On Thu, Sep 29, 2016 at 09:43:53AM -0700, Paul E. McKenney wrote:
> On Thu, Sep 29, 2016 at 05:03:08PM +0100, Will Deacon wrote:
> > On Thu, Sep 29, 2016 at 05:58:17PM +0200, Peter Zijlstra wrote:
> > > On Thu, Sep 29, 2016 at 08:54:01AM -0700, Paul E. McKenney wrote:
> > > > If two processes are
On 9/29/2016 12:48 PM, Ondrej Zary wrote:
>> Let's see the new set. If this doesn't work, I'll have to provide you with
>> > another patch to get the penalty counts again. The original debug aids
>> > patch may not apply after these.
> It boots but the IRQ problem still remains the same. See the
On 09/28/2016 07:21 AM, Joel Fernandes wrote:
From: Joel Fernandes
PMSG now uses ramoops_pstore_write_buf_user instead of write_buf.
Remove the case where we check PSTORE_TYPE_PMSG case in write_buf.
Ack
Commit-ID: 2acad19500c28ce0c4dc3f9bf1dcfc82040b6531
Gitweb: http://git.kernel.org/tip/2acad19500c28ce0c4dc3f9bf1dcfc82040b6531
Author: Simon Que
AuthorDate: Wed, 28 Sep 2016 11:37:53 -0700
Committer: Arnaldo Carvalho de Melo
CommitDate: Thu, 29 Sep
On Wed, Sep 28, 2016 at 02:55:50PM +1000, Dave Chinner wrote:
> On Tue, Sep 27, 2016 at 07:08:42PM -0700, Christoph Hellwig wrote:
> > On Tue, Sep 27, 2016 at 02:47:51PM -0600, Ross Zwisler wrote:
> > > DAX PMDs have been disabled since Jan Kara introduced DAX radix tree based
> > > locking. This
Hi,
On Thu, Sep 29, 2016 at 06:31:52PM +0200, Bartosz Golaszewski wrote:
> From: Karl Beldan
>
> This adds the pins used by the LCD controller, and uses 'tilcdc,panel'
> with some default timings for 800x600.
>
> Tested on an LCDK connected on the VGA port (the LCDC is
Christoph Hellwig writes:
> On Thu, Sep 29, 2016 at 03:45:29PM -0300, Gabriel Krisman Bertazi wrote:
>> I'm stepping up to assist with the genwqe_card driver just now, since we
>> (ibm) missed some of the last patches that went in. I'll add myself to
>> maintainers file.
>
> Can
On Thu, Sep 29, 2016 at 4:48 AM, Borislav Petkov wrote:
> On Wed, Sep 28, 2016 at 12:34:15PM -0700, Andy Lutomirski wrote:
>> The condition for reading CR4 was wrong: there are some CPUs with
>> CPUID but not CR4. Rather than trying to make the condition exact,
>> using
On Thu, Sep 29, 2016 at 12:35:37PM -0400, Olimpiu Dejeu wrote:
> Resubmition of arcxcnn backliught driver bindings correcting the file
> location, device name, and proper use of reg for device address
>
> Signed-off-by: Olimpiu Dejeu
>
> ---
>
On Thu, Sep 29, 2016 at 12:34:39PM -0400, Olimpiu Dejeu wrote:
> Resubmition of arcxcnn backliught driver adding definitions of the
> internal registers of the chip.
s/backliught/backlight/
[...]
> +#ifdef CONFIG_OF
> +static int arcxcnn_parse_dt(struct arcxcnn *lp)
> +{
> + struct device
On 09/29/2016 11:54 AM, Andy Lutomirski wrote:
>> So lets first see how a single priority intr works on ARC (maybe on other
>> arches
>> > as well).
>> >
>> > 1. task t1 enters kernel syscall (Trap Exception on ARC), handler drops
>> > down to
>> > pure kernel model and proceeds into syscall
Hi,
On Thu, Sep 22, 2016 at 5:12 PM, Shawn Lin wrote:
> Per JESD84-B51 P69, Host need to change frequency to <=52MHz
Technically Page 49. In the PDF you go to page 69, but the heading on
the top of the page says 49.
> after setting HS_TIMING to 0x1, and host may
On Tue, 13 Sep 2016, Charles Keepax wrote:
> From: Praveen Kumar Vegivada
>
> This register is used in the AIF code but is missing from the register
> tables.
>
> Signed-off-by: Praveen Kumar Vegivada
> Signed-off-by: Charles Keepax
From: SeongSoo Cho
As you know, there are the common colored printing of percents so overhead(%)
can be c$
But Delta means difference percents from percents of overhead between two files
e.g. p$
Although the rule is for overhead(%), Delta value also follow the same rule.
On Wed, Sep 28, 2016 at 10:25:40PM -0400, Johannes Weiner wrote:
> On Wed, Sep 28, 2016 at 11:39:25AM -0400, Johannes Weiner wrote:
> > On Wed, Sep 28, 2016 at 11:00:15AM +0200, Vlastimil Babka wrote:
> > > I guess testing revert of 9c0415e could give us some idea. Commit
> > > 3a1086f shouldn't
On Mon, Sep 26, 2016 at 07:28:08PM +0200, Gerald Schaefer wrote:
> This addresses several issues with hugepages and memory offline. While
> the first patch fixes a panic, and is therefore rather important, the
> last patch is just a performance optimization.
>
> The second patch fixes a
* Jann Horn wrote:
> +{
> + /* Permitting a write to readonly memory is fine - making the readonly
> + * memory executable afterwards would require EXECMOD permission because
> + * anon_vma would be non-NULL.
> + */
Minor stylistic nit: please fix this
* Jann Horn wrote:
> +/*
> + * subject_cred must be the subjective credentials using which access is
> + * requested.
> + * object_cred must be the objective credentials of the target task at the
> time
> + * the mm_struct was acquired.
> + * Both of these may be NULL if
From: Huang Ying
This patchset is to optimize the performance of Transparent Huge Page
(THP) swap.
Hi, Andrew, could you help me to check whether the overall design is
reasonable?
Hi, Hugh, Shaohua, Minchan and Rik, could you help me to review the
swap part of the
From: Huang Ying
This patch make it possible to charge or uncharge a set of continuous
swap entries in the swap cgroup. The number of swap entries is
specified via an added parameter.
This will be used for the THP (Transparent Huge Page) swap support.
Where a swap cluster
From: Huang Ying
This patch enhanced the split_huge_page_to_list() to work properly for
the THP (Transparent Huge Page) in the swap cache during swapping out.
This is used for delaying splitting the THP during swapping out. Where
for a THP to be swapped out, we will
From: Huang Ying
Johannes suggested me to use two big patches instead 9 patches. And he
feels that is easier for him to review. I am not sure whether this is
desirable for other reviewers too. So I sent out both versions for
review. If this version is preferable for
From: Huang Ying
With this patch, a THP (Transparent Huge Page) can be added/deleted
to/from the swap cache as a set of (HPAGE_PMD_NR) sub-pages.
This will be used for the THP (Transparent Huge Page) swap support.
Where one THP may be added/delted to/from the swap cache.
From: Huang Ying
The swap cluster allocation/free functions are added based on the
existing swap cluster management mechanism for SSD. These functions
don't work for the rotating hard disks because the existing swap cluster
management mechanism doesn't work for them. The
From: Huang Ying
In this patch, the size of the swap cluster is changed to that of the
THP (Transparent Huge Page) on x86_64 architecture (512). This is for
the THP swap support on x86_64. Where one swap cluster will be used to
hold the contents of each THP swapped out.
From: Huang Ying
A variation of get_swap_page(), get_huge_swap_page(), is added to
allocate a swap cluster (HPAGE_PMD_NR swap slots) based on the swap
cluster allocation function. A fair simple algorithm is used, that is,
only the first swap device in priority list will be
From: Huang Ying
__swapcache_free() is added to support to clear the SWAP_HAS_CACHE flag
for the huge page. This will free the specified swap cluster now.
Because now this function will be called only in the error path to free
the swap cluster just allocated. So the
From: Huang Ying
In this patch, splitting huge page is delayed from almost the first step
of swapping out to after allocating the swap space for the
THP (Transparent Huge Page) and adding the THP into the swap cache.
This will reduce lock acquiring/releasing for the locks
From: Huang Ying
Separates checking whether we can split the huge page from
split_huge_page_to_list() into a function. This will help to check that
before splitting the THP (Transparent Huge Page) really.
This will be used for delaying splitting THP during swapping out.
On Wed, Sep 28, 2016 at 06:20:29PM -0700, Vineet Gupta wrote:
> On 09/28/2016 03:26 PM, Andy Lutomirski wrote:
> >> Right, so what I think Vineet is asking is if we need to disable NMIs as
> >> > well, we cannot on x86 disable NMIs so no.
> >> >
> > The same argument works here, too: an NMI won't
On Mon, Sep 26, 2016 at 12:00:30PM +0200, Wolfram Sang wrote:
> On Mon, Sep 26, 2016 at 11:54:15AM +0200, Bartosz Golaszewski wrote:
> > This is a follow-up to commit 559b46990e76 ("gpio: pca953x: fix an
> > incorrect lockdep warning"). The reason for calling
> > lockdep_set_subclass() in
2016-09-28 18:04 GMT+02:00 Joe Perches :
> On Wed, 2016-09-28 at 17:47 +0200, Nicolas Ferre wrote:
>> Change maintainer for the serial driver found on most of the
>> Microchip / Atmel MPUs and take advantage of the move to rename
>> and reorder the entry.
> []
>> diff --git
Hi all,
Changes since 20160928:
The xtensa tree gained a conflict against Linus' tree.
The tip tree gained a conflict against the vfs tree and a build failure
due to an interaction with the pm tree for which I added a merge fix
patch.
Non-merge commits (relative to Linus' tree): 13043
9796
On Wed, Sep 28, 2016 at 05:47:35PM +0200, Nicolas Ferre wrote:
> Change maintainer for the serial driver found on most of the
> Microchip / Atmel MPUs and take advantage of the move to rename
> and reorder the entry.
> I'm happy that Richard is taking over the maintenance of this
> driver.
>
>
On Wed, Sep 28, 2016 at 12:20 AM, Andrew Jeffery wrote:
> The System Control Unit IP in the Aspeed SoCs is typically where the
> pinmux configuration is found.
>
> But not always.
>
> On the AST2400 and AST2500 a number of pins depend on state in one of
> the SIO, LPC or GFX IP
On 28-09-16, 15:07, Vladimir Zapolskiy wrote:
> I would expect that the change below improves the situation, but I didn't
> perform any tests and here the core change is governed by the accepted
> i.MX i2c bus driver specific changes, thus conceptually it may be incorrect:
>
> diff --git
On Wed, Sep 28, 2016 at 11:36:10PM +0200, Rafael J. Wysocki wrote:
> On Fri, Sep 23, 2016 at 4:57 PM, Mika Westerberg
> wrote:
> > DT allows holes or empty phandles for references. This is used for example
> > in SPI subsystem where some chip selects are native
Hi Rafael,
On 2016-09-29 02:24, Rafael J. Wysocki wrote:
Hi Everyone,
On Thursday, September 08, 2016 11:25:44 PM Rafael J. Wysocki wrote:
Hi Everyone,
This is a refresh of the functional dependencies series that I posted last
year and which has picked up by Marek quite recently. For
I would like to help maintaining Marvell berlin SoCs.
Signed-off-by: Jisheng Zhang
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b003d0c..b1e5243 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1411,6 +1411,7 @@ F:
ping ping.
> Am 19.09.2016 um 11:55 schrieb H. Nikolaus Schaller :
>
> ping.
>
>> Am 08.09.2016 um 17:48 schrieb H. Nikolaus Schaller :
>>
>> of_node_put() has already been called inside of_graph_get_next_endpoint().
>>
>> Otherwise we may get warnings
On Wed, Sep 28, 2016 at 11:32:46PM +0200, Rafael J. Wysocki wrote:
> Hi,
>
> On Fri, Sep 23, 2016 at 4:57 PM, Mika Westerberg
> wrote:
> > Hi,
> >
> > This series brings couple of useful GPIO related properties from Device
> > Tree to ACPI _DSD device properties:
From: "Gautham R. Shenoy"
Hi,
In the current implementation, the code for ISA v3.0 stop
implementation has a couple of shortcomings.
a) The code hand-codes the values for ESL,EC,TR,MTL bits of PSSCR and
uses only the RL field from the firmware. While this is not
On Sep 28 2016 or thereabouts, Roderick Colenbrander wrote:
> On Wed, Sep 28, 2016 at 10:39 AM, Dmitry Torokhov
> wrote:
> >
> > On Tue, Sep 27, 2016 at 4:38 PM, Roderick Colenbrander
> > wrote:
> > > From: Roderick Colenbrander
在 2016/9/27 6:35, Heiko Stuebner 写道:
Am Samstag, 24. September 2016, 18:24:11 CEST schrieb Shawn Lin:
On 2016/9/24 2:26, Jacob Chen wrote:
From: Jacob Chen
In some drivers, disable_irq() call don't be symmetric with enable_irq()
, disable_irq() will be called
On Marvell berlin arm64 platforms, I see the preemptoff tracer report
a max 26543 us latency at __purge_vmap_area_lazy, this latency is an
awfully bad for STB. And the ftrace log also shows __free_vmap_area
contributes most latency now. I noticed that Joel mentioned the same
issue[1] on x86
On Mon, 4 Jul 2016, Masanari Iida wrote:
> This patch fix spelling typos within various Freescale
> Semiconductor's related drivers.
>
> Signed-off-by: Masanari Iida
> ---
> drivers/dma/mpc512x_dma.c | 2 +-
> drivers/dma/qcom/hidma.c | 2
This patch uses recently introduced device links to track the runtime pm
state of the master's device. This way each SYSMMU controller is runtime
activated when its master's device is active and can save/restore its state
instead of being enabled all the time. This way SYSMMU controllers no
longer
Hello,
This patch series finally implements proper runtime PM support in Exynos
IOMMU driver. This has been achieved by using recently introduce device
links, which lets SYSMMU controller's runtime PM to follow master's device
runtime PM state (the device which actually performs DMA transaction).
Remove excessive, useless debug about skipping TLB invalidation, which
is a normal situation when more aggressive power management is enabled.
Signed-off-by: Marek Szyprowski
---
drivers/iommu/exynos-iommu.c | 3 ---
1 file changed, 3 deletions(-)
diff --git
On Thu, Sep 29, 2016 at 03:34:11PM +0800, Jisheng Zhang wrote:
> On Marvell berlin arm64 platforms, I see the preemptoff tracer report
> a max 26543 us latency at __purge_vmap_area_lazy, this latency is an
> awfully bad for STB. And the ftrace log also shows __free_vmap_area
> contributes most
Hi Yan,
On Mon, Sep 26, 2016 at 11:38:05AM -0400, Zi Yan wrote:
> On 26 Sep 2016, at 11:22, zi@sent.com wrote:
>
> > From: Zi Yan
> >
> > Hi all,
> >
> > This patchset is based on Naoya Horiguchi's page migration enchancement
> > for thp patchset with additional IBM
From: Taniya Das
Alpha PLLs can support 2 kinds of input signals, normal and latched. The
normal input is directly passed to the core, while the latched input
requires a latch and acknowledge sequence to be performed for the
changed input to propagate.
Alpha PLLs can
The votable alpha PLLs need to have the fsm mode enabled as part
of the initialization. The sequence seems to be the same as used
by clk-pll, so move the function which does this into a common
place and reuse it for the clk-alpha-pll
Signed-off-by: Rajendra Nayak
This would be useful in subsequent patches when the .set_rate operation
would need to identify if the PLL is actually enabled
Signed-off-by: Rajendra Nayak
---
drivers/clk/qcom/clk-alpha-pll.c | 29 +
1 file changed, 29 insertions(+)
diff
Alpha PLLs which do not support dynamic update feature
need to be explicitly disabled before a rate change.
The ones which do support dynamic update do so within a
single vco range, so add a min/max freq check for such
PLLs so they fall in the vco range.
Signed-off-by: Taniya Das
Add support to pass a table of values for parent selection similar
to whats done in clk-mux
Signed-off-by: Rajendra Nayak
---
drivers/clk/qcom/clk-regmap-mux.c | 13 +
drivers/clk/qcom/clk-regmap-mux.h | 1 +
2 files changed, 14 insertions(+)
diff --git
On Tue 27-09-16 21:57:26, Tetsuo Handa wrote:
> Michal Hocko wrote:
> > > > > ) rather than by line number, and surround __warn_memalloc_stall()
> > > > > call with
> > > > > mutex in order to serialize warning messages because it is possible
> > > > > that
> > > > > multiple allocation requests
On Thu, Sep 29, 2016 at 02:16:44PM +0530, Manish Narani wrote:
> This patch adds support to configure bulk maxburst through
> module parameter. This parameter can be used to modify bulk
> maxburst in case if one wants to measure peak Bulk/Isoc-IN/OUT
> performance.
Eeek, this isn't the 1990's,
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