On Mon, Oct 31, 2016 at 9:50 AM, Zahari Doychev
wrote:
> On Sat, Oct 29, 2016 at 11:05:29AM +0200, Linus Walleij wrote:
>> > +static int dmec_gpio_irq_set_type(struct irq_data *d, unsigned int type)
>> > +{
>> > + struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
>> > + struct dme
Hi Michael et al,
On Monday, 31 October 2016 16:28:59 GMT Michael Ellerman wrote:
> Andreas Schwab writes:
> > Any news?
>
> We discovered it also breaks VGA on qemu, which presumably is not the
> type of news you were hoping for.
On the contrary, that's wonderful news - I can test that! Huzzah
On Mon, Oct 31, 2016 at 11:12:45AM +0100, Geert Uytterhoeven wrote:
> On Fri, Oct 7, 2016 at 6:09 PM, Laura Abbott wrote:
> > The current state of driver removal is not great.
> > CONFIG_DEBUG_TEST_DRIVER_REMOVE finds lots of errors. The help text
> > currently undersells exactly how many errors t
The powerpc dts file upstream does not have the xlnx,kind-of-intr
property. Instead of erroring out, give a warning instead.
And attempt to continue to probe the interrupt controller while
assuming kind-of-intr is 0x0 as a fall back.
Signed-off-by: Zubair Lutfullah Kakakhel
---
V5 -> V6
Rebase t
The drivers read/write function handling is a bit quirky.
And the irqmask is passed directly to the handler.
Add a new irqchip struct to pass to the handler and
cleanup read/write handling.
Signed-off-by: Zubair Lutfullah Kakakhel
---
V5 -> V6
Removed __func__ from printk
Rebase to v4.9-rc3
V4
The MIPS based xilfpga platform has the following IRQ structure
Peripherals --> xilinx_intcontroller -> mips_cpu_int controller
Add support for the driver to chain the irq handler
Signed-off-by: Zubair Lutfullah Kakakhel
---
V5 -> V6
Use chained_irq_enter and chained_irq_exit
Add error check f
Now that the driver is generic and used by multiple archs,
get_irq is too generic.
Rename get_irq to xintc_get_irq to avoid any conflicts
Signed-off-by: Zubair Lutfullah Kakakhel
---
V5 -> V6
Removed __func__ in printk
Rebase to v4.9-rc3
V4 -> V5
Rebased to v4.9-rc1
Use __func__ in pr_err
V3
The Xilinx AXI Interrupt Controller IP block is used by the MIPS
based xilfpga platform and a few PowerPC based platforms.
Move the interrupt controller code out of arch/microblaze so that
it can be used by everyone
Signed-off-by: Zubair Lutfullah Kakakhel
---
V5 -> V6
Rebase to v4.9-rc3
V4 ->
The Xilinx interrupt controller driver is now available in drivers/irqchip.
Switch to using that driver.
Signed-off-by: Zubair Lutfullah Kakakhel
Acked-by: Michael Ellerman (powerpc)
---
V5 -> V6 Added Acked-by Micheal Ellerman
V5 New patch
Tested on virtex440-ml507 using qemu
---
arch/power
Hi,
The MIPS based Xilfpga platform uses the Xilinx interrupt controller
daisy chained to the MIPS microAptiv cpu interrupt controller.
This patch series moves the Xilinx interrupt controller driver out
of arch/microblaze to drivers/irqchip and then cleans it up a bit.
And then removes another im
If a device tree specified a preferred device for kernel console output
via the stdout-path or linux,stdout-path chosen node properties there's
no guarantee that it will have specified a device for which we have a
driver. It may also be the case that we do have a driver but it doesn't
call of_conso
On Mon, Oct 31, 2016 at 01:51:17PM +0700, tnhu...@apm.com wrote:
> From: Tin Huynh
>
> Free and Open IPMI use SMBUS BLOCK Read/Write to support SSIF protocol.
> However, I2C Designware Core Driver doesn't handle the case at the moment.
> The below patch supports this feature.
>
> Signed-off-by:
On 10/25/2016 05:40 PM, Piotr Kwapulinski wrote:
> Hi Michael,
>
> I spent a couple of hours trying to review your patch. Unfortunately
> nowadays I spend no more than an hour per day for whole my linux
> kernel activity. It may take longer time for me to review it.
> This patch touches some areas
On 10/28/2016 05:12 PM, Ulf Hansson wrote:
> On 25 October 2016 at 21:58, Zach Brown wrote:
>> On some systems the sdhci capabilty registers are incorrect for one
>> reason or another.
>>
>> The sdhci-caps-mask property specifies which bits in the registers
>> are incorrect and should be turned of
Hi Sascha,
> On Mon, Oct 31, 2016 at 06:59:04AM +0100, Sascha Hauer wrote:
> > On Thu, Oct 27, 2016 at 09:40:05AM +0200, Boris Brezillon wrote:
> > > On Thu, 27 Oct 2016 08:29:39 +0200
> > > Lukasz Majewski wrote:
> > >
> > > > The code has been rewritten to remove "generic" calls to
> > > > imx
On Thursday 27 October 2016 05:48 AM, David Lechner wrote:
> This adds device names for the SoC USB devices to the clock lookup tables
> in da830.c and da850.c.
>
> Also add the USB device names to the da850_auxdata_lookup[] table.
>
> Signed-off-by: David Lechner
Applied to v4.10/soc
Thanks,
On Thursday 27 October 2016 05:48 AM, David Lechner wrote:
> There is now a proper phy driver for the DA8xx SoC USB PHY. This adds the
> platform device declarations needed to use it.
>
> Signed-off-by: David Lechner
> ---
>
> Updated this patch so that it applies/builds cleanly before "ARM: dav
Hi Rajendra,
On 06/10/16 09:43, Rajendra Nayak wrote:
On 10/06/2016 01:55 PM, Jon Hunter wrote:
Hi Rajendra,
On 06/10/16 07:04, Rajendra Nayak wrote:
On 09/20/2016 03:58 PM, Jon Hunter wrote:
The Tegra124/210 XUSB subsystem (that consists of both host and device
controllers) is partitioned
On 28/10/16 10:09, Christophe JAILLET wrote:
'devm_pinctrl_register()' returns an error pointer or a valid handle. So
checking for NULL here is pointless and can never trigger.
Check the returned value with IS_ERR instead and propagate this value as
done in the other functions which call 'devm_
On 31/10/2016 11:02, Lorenzo Stoakes wrote:
> - *
> - * get_user_pages should be phased out in favor of
> - * get_user_pages_locked|unlocked or get_user_pages_fast. Nothing
> - * should use get_user_pages because it cannot pass
> - * FAULT_FLAG_ALLOW_RETRY to handle_mm_fault.
This comment should
On 31/10/2016 12:05, Borislav Petkov wrote:
> On Mon, Oct 31, 2016 at 11:47:48AM +0100, Paolo Bonzini wrote:
>> The information is all in arch/x86/kernel/cpu/scattered.c's cpuid_bits
>> array. Borislav, would it be okay to export the cpuid_regs enum?
>
> Yeah, and kill the duplicated one in arc
On Friday 28 October 2016 02:47 AM, John Syne wrote:
>>
>> ---
>> include/linux/mfd/ti_am335x_tscadc.h | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/include/linux/mfd/ti_am335x_tscadc.h
>> b/include/linux/m
Instead of just delaying for 100us, we should
actually wait for End Transfer Command Complete
interrupt before moving on. Note that this should
only be done if we're dealing with one of the core
revisions that actually require the interrupt before
moving on.
[ felipe.ba...@linux.intel.com: minor i
Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven
---
v2:
- New.
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
b/ar
From: Arnd Bergmann
We keep running into cases where device drivers want to know the exact
version of the a SoC they are currently running on. In the past, this has
usually been done through a vendor specific API that can be called by a
driver, or by directly accessing some kind of version regist
Identify the SoC type and revision, and register this information with
the SoC bus, so it is available under /sys/devices/soc0/, and can be
checked where needed using soc_device_match().
Identification is done using the Product Register or Common Chip Code
Register, as declared in DT, or using a h
If soc_device_match() is used to check the value of a specific
attribute that is not present for the current SoC, the kernel crashes
with a NULL pointer dereference.
Fix this by explicitly checking for the absence of a needed property,
and considering this a non-match.
Signed-off-by: Geert Uytter
Add device tree binding documentation for the Common Chip Code Register
and Product Register, which provide SoC product and revision
information.
Signed-off-by: Geert Uytterhoeven
---
v2:
- New.
---
Documentation/devicetree/bindings/arm/shmobile.txt | 26 ++
1 file changed,
Hi all,
Some Renesas SoCs may exist in different revisions, providing slightly
different functionalities (e.g. R-Car H3 ES1.x and ES2.0), and behavior
(errate and quirks). This needs to be catered for by drivers and/or
platform code. The recently proposed soc_device_match() API seems lik
Provide a dummy implementation of soc_device_match(), to allow compiling
drivers that may be used on SoCs both with and without CONFIG_SOC_BUS,
and for compile testing.
Signed-off-by: Geert Uytterhoeven
---
v2:
- New.
---
include/linux/sys_soc.h | 6 ++
1 file changed, 6 insertions(+)
dif
If soc_device_register() is called before soc_bus_register(), it crashes
with a NULL pointer dereference.
soc_bus_register() is already a core_initcall(), but drivers/base/ is
entered later than e.g. drivers/pinctrl/ and drivers/soc/. Hence there
are several subsystems that may need to know SoC re
On 2016/10/30 at 20:18, David Woodhouse wrote:
> On Wed, 2016-10-12 at 13:17 +0100, David Woodhouse wrote:
>> Yes, that looks correct. I think we may also need to limit it, because
>> full 20-bit PASID support means we'll attempt an order 11 allocation.
>> But that's certainly correct for now
> Act
This patch adds module licence to lpass-cpu driver, without this
patch lpass-cpu module would taint with below error:
snd_soc_lpass_cpu: module license 'unspecified' taints kernel.
Disabling lock debugging due to kernel taint
snd_soc_lpass_cpu: Unknown symbol regmap_write (err 0)
snd_soc_lpass_cpu
On 29 October 2016 at 01:03, Mark Brown wrote:
> On Fri, Oct 28, 2016 at 08:51:41PM +0800, Baolin Wang wrote:
>> On 28 October 2016 at 06:00, NeilBrown wrote:
>
>> > 1/ I think we agreed that it doesn't make sense for there to be
>> > two chargers registered in a system.
>
>> Yes, until now...
>
This patch fixes lpass-platform driver which was broken in v4.9-rc1.
lpass_pcm_data data structure holds information specific to stream.
Holding a single private pointer to it in global lpass_data
will not work, because it would be overwritten by for each pcm instance.
This code was breaking playb
On Thursday 27 October 2016 09:02 PM, Alexandre Bailon wrote:
> Some macro for DA8xx CFGCHIP are defined in usb-davinci.h,
> but da8xx-cfgchip.h intend to replace them.
> Remove duplicated defines between da8xx-cfgchip.h and usb-davinci.h
>
> Signed-off-by: Alexandre Bailon
Applied to v4.10/clea
This patch cleans up usage of wrdma_ch and rdma_ch variables into a
common variable dma_ch, As there is no real use of tracking the dma
channel in two different variables based on stream direction.
Signed-off-by: Srinivas Kandagatla
Acked-by: Kenneth Westfield
---
sound/soc/qcom/lpass-platform.
Hi Mark,
This patchset fixes broken lpass-platform driver in v4.9-rc1, and also
fixes problem while using lpass as kernel module.
There is also a cleanup patch in this series just to tidy up the code
in the same area where there is regression.
Tested this patchset with msm8916 codec patchset in l
On 29 October 2016 at 11:23, John Stultz wrote:
> On Thu, Oct 27, 2016 at 12:32 AM, Baolin Wang wrote:
>> On 18 October 2016 at 14:47, Baolin Wang wrote:
>>> From the trace log, we can find out the 'Binder:3292_2' process
>>> set one alarm timer which resumes the system.
>>>
>>> Signed-off-by: B
Hi,
John Stultz writes:
> I had seen some odd behavior with HiKey's usb-gadget interface
> that I finally seemed to have chased down. Basically every other
> time I pluged in the OTG port, the gadget interface would
> properly initialize. The other times, I'd get a big WARN_ON
> in dwc2_hsotg_in
Hi Felipe,
>>
>> If this series looks good, can you pick it up please?
>
> it's in my testing/next branch. Has been there for a while ;-)
Good. Thanks for taking care of it!
--
Best Regards
Masahiro Yamada
From: Ziji Hu
Add Xenon eMMC/SD/SDIO host controller core functionality.
Add Xenon specific intialization process.
Add Xenon specific mmc_host_ops APIs.
Add Xenon specific register definitions.
Add CONFIG_MMC_SDHCI_XENON support in drivers/mmc/host/Kconfig.
Marvell Xenon SDHC conforms to SD Phy
Hi Neil,
On 31 October 2016 at 11:54, Neil Armstrong wrote:
> Add Synopsys Designware MAC Glue layer for the Oxford Semiconductor OX820.
>
> Acked-by: Joachim Eastwood
> Signed-off-by: Neil Armstrong
> ---
> +static int oxnas_dwmac_init(struct oxnas_dwmac *dwmac)
> +{
> + unsigned int val
From: Ziji Hu
Marvell Xenon eMMC/SD/SDIO Host Controller contains PHY.
Three types of PHYs are supported.
Add support to multiple types of PHYs init and configuration.
Add register definitions of PHYs.
Signed-off-by: Hu Ziji
Signed-off-by: Gregory CLEMENT
---
MAINTAINERS
Add the eMMC support for Armada 37xx SoC and enable it in the Armada 3720
DB board.
Signed-off-by: Gregory CLEMENT
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 8
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 11 +++
2 files changed, 19 insertions(+), 0 deletions(-)
Hello,
This the second version of the series adding support for the SDHCI
Xenon controller. It can be currently found on the Armada 37xx and the
Armada 7K/8K but will be also used in more Marvell SoC (and not only
the mvebu ones actually).
Some of the remarks had been taking into account since th
From: Ziji Hu
Export sdhci_start_signal_voltage_switch() from sdhci.c.
Thus vendor sdhci driver can implement its own signal voltage
switch routine.
Signed-off-by: Hu Ziji
Signed-off-by: Gregory CLEMENT
---
drivers/mmc/host/sdhci.c | 5 +++--
drivers/mmc/host/sdhci.h | 2 ++
2 files changed,
This patch enables the driver for the SDHCI controller found on the
Marvell Armada 3700 and 7K/8K ARM64 SoCs.
Signed-off-by: Gregory CLEMENT
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+), 0 deletions(-)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defc
From: Ziji Hu
Marvell Xenon SDHC can support eMMC/SD/SDIO.
Add Xenon-specific properties.
Also add properties for Xenon PHY setting.
Signed-off-by: Hu Ziji
Signed-off-by: Gregory CLEMENT
---
Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt | 161 +++-
MAINTAINERS
From: Ziji Hu
Export sdhci_set_ios() in sdhci.c.
Thus vendor sdhci driver can implement its own set_ios() routine.
Signed-off-by: Hu Ziji
Signed-off-by: Gregory CLEMENT
---
drivers/mmc/host/sdhci.c | 3 ++-
drivers/mmc/host/sdhci.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff
Also enable it on the Armada 7040 DB board
Signed-off-by: Gregory CLEMENT
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 8
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 9 +
2 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/a
From: Ziji Hu
Add maintainer entry for Marvell Xenon eMMC/SD/SDIO Host
Controller drivers.
Signed-off-by: Hu Ziji
Signed-off-by: Gregory CLEMENT
---
MAINTAINERS | 5 +
1 file changed, 5 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index c44795306342..1a5c4c30ea24
From: Ziji Hu
Export sdhci_execute_tuning() from sdhci.c.
Thus vendor sdhci driver can execute its own tuning process.
Signed-off-by: Hu Ziji
Signed-off-by: Gregory CLEMENT
---
drivers/mmc/host/sdhci.c | 3 ++-
drivers/mmc/host/sdhci.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
d
> -Original Message-
> From: Arnd Bergmann [mailto:a...@arndb.de]
> Sent: Friday, October 28, 2016 6:53 PM
> To: linuxppc-...@lists.ozlabs.org
> Cc: Y.B. Lu; linux-...@vger.kernel.org; ulf.hans...@linaro.org; Scott
> Wood; Mark Rutland; Greg Kroah-Hartman; X.B. Xie; M.H. Lian; linux-
> i...
On Mon, Oct 31, 2016 at 11:47:48AM +0100, Paolo Bonzini wrote:
> The information is all in arch/x86/kernel/cpu/scattered.c's cpuid_bits
> array. Borislav, would it be okay to export the cpuid_regs enum?
Yeah, and kill the duplicated one in arch/x86/events/intel/pt.c too
please, while at it.
I'd
Hi,
Masahiro Yamada writes:
> Hello Felipe,
>
> If this series looks good, can you pick it up please?
it's in my testing/next branch. Has been there for a while ;-)
--
balbi
signature.asc
Description: PGP signature
> -Original Message-
> From: Arnd Bergmann [mailto:a...@arndb.de]
> Sent: Friday, October 28, 2016 6:48 PM
> To: linuxppc-...@lists.ozlabs.org
> Cc: Y.B. Lu; linux-...@vger.kernel.org; ulf.hans...@linaro.org; Scott
> Wood; Mark Rutland; Greg Kroah-Hartman; X.B. Xie; M.H. Lian; linux-
> i...
On Fri, Sep 16, 2016 at 01:23:25PM -0700, Yinghai Lu wrote:
> From: Yinghai Lu
>
> For UE recovery support, current we need mce=2 in command line
> and also disable panic_on_oops with sysctl.
>
> but other user may still need to have panic_on_oops to 1 always.
>
> We can remove checking of pani
On Sun, 30 Oct 2016 16:37:32 -0400
Paul Gortmaker wrote:
> The Kconfig currently controlling compilation of this code is:
>
> arch/s390/Kconfig:config S390_GUEST
> arch/s390/Kconfig: def_bool y
>
> ...meaning that it currently is not being built as a module by anyone.
>
> Lets remove the
This patchset add support for the Sysnopsys DWMAC Gigabit Ethernet
controller Glue layer of the Oxford Semiconductor OX820 SoC.
Changes since v1 at https://patchwork.kernel.org/patch/9388231/ :
- Split dt-bindings in a separate patch
- Add IP version in the dt-bindings compatible
- Check return
Signed-off-by: Neil Armstrong
---
.../devicetree/bindings/net/oxnas-dwmac.txt| 39 ++
1 file changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/oxnas-dwmac.txt
diff --git a/Documentation/devicetree/bindings/net/oxnas-dwmac.txt
b/Docum
Add Synopsys Designware MAC Glue layer for the Oxford Semiconductor OX820.
Acked-by: Joachim Eastwood
Signed-off-by: Neil Armstrong
---
drivers/net/ethernet/stmicro/stmmac/Kconfig | 11 ++
drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
drivers/net/ethernet/stmicro/stmmac/dwma
On Sun, Oct 23, 2016 at 03:12:28PM +0300, Noam Camus wrote:
> From: Noam Camus
>
> Till now we used clockevent from generic ARC driver.
> This was enough as long as we worked with simple multicore SoC.
> When we are working with multithread SoC each HW thread can be
> scheduled to receive timer i
On 31/10/2016 11:30, Borislav Petkov wrote:
> On Mon, Oct 31, 2016 at 10:18:41AM +, Luc, Piotr wrote:
>> The cpuid_mask function, which usually used in kvm, read bit from this
>> x86_capabity and mask out. This prevents passing disabled features to
>> guest. If we use cpu_count instead, which
On 2016-10-28 22:24:52 [+], Trond Myklebust wrote:
> > diff --git a/fs/nfs/nfs4state.c b/fs/nfs/nfs4state.c
> > index 5f4281ec5f72..a442d9867942 100644
> > --- a/fs/nfs/nfs4state.c
> > +++ b/fs/nfs/nfs4state.c
> > @@ -1497,8 +1498,18 @@ static int nfs4_reclaim_open_state(struct
> > nfs4_state_
On Fri, Oct 28, 2016 at 04:14:44PM -0700, Dmitry Torokhov wrote:
> Make use of the device property API in this driver so that both OF based
> systems and ACPI based systems can use this driver.
>
> Suggested-by: Geert Uytterhoeven
> Suggested-by: Mika Westerberg
> Signed-off-by: Dmitry Torokhov
On Fri, Oct 28, 2016 at 04:14:39PM -0700, Dmitry Torokhov wrote:
> diff --git a/include/linux/gpio_keys.h b/include/linux/gpio_keys.h
> index ee2d8c6..d1250ad 100644
> --- a/include/linux/gpio_keys.h
> +++ b/include/linux/gpio_keys.h
> @@ -2,7 +2,6 @@
> #define _GPIO_KEYS_H
>
> struct device;
>
In case the screenshot doesn't make it to you, here it is:
https://postimg.org/image/5wl2wemt9/
Am 31.10.2016 11:36 schrieb Martin Kepplinger:
so guys,
I can't believe that nobody hits this: Since -rc1 Nautilus' list of
elements or Firefox' website window or just photos in eog (probably
among
so guys,
I can't believe that nobody hits this: Since -rc1 Nautilus' list of
elements or Firefox' website window or just photos in eog (probably
among many more things) is mangled. Please have a look at the screenshot
of nautilus.
This is the same on a i3 laptop with intel graphics and a i7
On Monday 31 October 2016 03:24 PM, Bartosz Golaszewski wrote:
> 2016-10-31 10:52 GMT+01:00 Sekhar Nori :
>> Hi Bartosz,
>>
>> On Monday 31 October 2016 03:10 PM, Bartosz Golaszewski wrote:
>>> 2016-10-31 5:30 GMT+01:00 Rob Herring :
On Wed, Oct 26, 2016 at 07:35:55PM +0200, Bartosz Golaszewsk
On Mon, Oct 31, 2016 at 10:18:41AM +, Luc, Piotr wrote:
> The cpuid_mask function, which usually used in kvm, read bit from this
> x86_capabity and mask out. This prevents passing disabled features to
> guest. If we use cpu_count instead, which reports bits directly from
Ah, you mean cpuid_cou
On Sat, Oct 29, 2016 at 09:19:05PM -0700, Deepa Dinamani wrote:
> > btw, where did you post the libevdev patch? I haven't seen it anywhere I'm
> > subscribed to.
>
> The libevdev patch was posted to input-to...@lists.freedesktop.org :
> https://www.mail-archive.com/y2038@lists.linaro.org/msg01824.
Hi Arnd,
On Sat, Oct 29, 2016 at 11:27 PM, Arnd Bergmann wrote:
> On Saturday, October 22, 2016 9:44:11 AM CEST Geert Uytterhoeven wrote:
>> On Fri, Oct 21, 2016 at 11:16 PM, Arnd Bergmann wrote:
>> > On Friday, October 21, 2016 8:16:00 PM CEST Geert Uytterhoeven wrote:
>> >> On Wed, Oct 19, 201
On Sun, Oct 23, 2016 at 03:12:27PM +0300, Noam Camus wrote:
> From: Noam Camus
>
> nps_setup_clocksource() should take node as only argument i.e.:
> replace
> int __init nps_setup_clocksource(struct device_node *node, struct clk *clk)
> with
> int __init nps_setup_clocksource(struct device_node *
On Sun, Oct 23, 2016 at 03:12:26PM +0300, Noam Camus wrote:
> From: Noam Camus
>
> This new header file is for NPS400 SoC (part of ARC architecture).
> The header file includes macros for save/restore of HW scheduling.
> The control of HW scheduling is acheived by writing core registers.
s/achei
On 10/31/2016 11:20 AM, Joachim Eastwood wrote:
> Hi Neil,
>
> On 31 October 2016 at 10:55, Neil Armstrong wrote:
>> On 10/30/2016 09:41 PM, Rob Herring wrote:
>>> On Fri, Oct 21, 2016 at 10:44:45AM +0200, Neil Armstrong wrote:
Add Synopsys Designware MAC Glue layer for the Oxford Semiconduc
On Mon, Oct 24, 2016 at 08:04:47AM -0400, Alexander Duyck wrote:
> The use of DMA_ATTR_SKIP_CPU_SYNC was not consistent across all of the DMA
> APIs in the arch/arm folder. This change is meant to correct that so that
> we get consistent behavior.
I'm really not convinced that this is anywhere cl
Hi Neil,
On 31 October 2016 at 10:55, Neil Armstrong wrote:
> On 10/30/2016 09:41 PM, Rob Herring wrote:
>> On Fri, Oct 21, 2016 at 10:44:45AM +0200, Neil Armstrong wrote:
>>> Add Synopsys Designware MAC Glue layer for the Oxford Semiconductor OX820.
>>>
>>> Signed-off-by: Neil Armstrong
>>> ---
On Tuesday 25 October 2016 11:24 PM, David Lechner wrote:
> This fixes pwm name matching for DA850 familiy devices. When using device
> tree, the da850_auxdata_lookup[] table caused pwm devices to have the exact
> same name, which caused errors when trying to register the devices.
>
> The names fo
On Mon, 2016-10-31 at 10:53 +0100, Borislav Petkov wrote:
> > I think that in v4.9-rc2 the CPUID[7,0].edx bits can be masked out
> by
> > applying noxsave to cmdline. Using directly cpu_count will result
> in
> > passing the bits in edx to a guest directly while the xsaveopt and
> rest
> > of AVX51
On Mon, Oct 31, 2016 at 09:00:08AM +, Russell King - ARM Linux wrote:
> I need the patch against v4.8. I'm happy to pick it up and add it
> to my drm-tda998x-devel branch, which you can then merge into
> drm-misc if you wish.
... or if Brian wants to send a git pull request to us with the
pat
On Fri, Oct 7, 2016 at 6:09 PM, Laura Abbott wrote:
> The current state of driver removal is not great.
> CONFIG_DEBUG_TEST_DRIVER_REMOVE finds lots of errors. The help text
> currently undersells exactly how many errors this option will find. Add
> a bit more description to indicate this option s
Trivial spelling fixes for Kconfig help text of config HWLAT_TRACER.
Fixes: e7c15cd8a113 ("tracing: Added hardware latency tracer")
Signed-off-by: Jesper Dangaard Brouer
---
kernel/trace/Kconfig |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/kernel/trace/Kconfig b/ker
> Ok,
>
> I actually tested boot time with my patch and didn't see a difference
> (so I guess our first attempt to send messages usually succeeds) but if
> we're concearned about less-than-a-second boot time we'd rather keep the
> microseonds delay for first several attempts. I'll do v2.
of cours
This patch adds an int *locked parameter to get_user_pages() to allow
VM_FAULT_RETRY faulting behaviour similar to get_user_pages_[un]locked().
It additionally clears the way for get_user_pages_locked() to be removed as its
sole remaining useful characteristic was to allow for VM_FAULT_RETRY behav
The subject line on this patch is misleading - it's not only ARM64
specific...
On Fri, Oct 21, 2016 at 11:30:13AM -0600, Tyler Baicar wrote:
> diff --git a/arch/arm/include/asm/system_misc.h
> b/arch/arm/include/asm/system_misc.h
> index a3d61ad..86e1faa 100644
> --- a/arch/arm/include/asm/system
get_user_pages() now has an int *locked parameter which renders
get_user_pages_locked() redundant, so remove it.
This patch should not introduce any functional changes.
Signed-off-by: Lorenzo Stoakes
---
include/linux/mm.h | 2 --
mm/frame_vector.c | 4 ++--
mm/gup.c | 56 +
KY Srinivasan writes:
>> -Original Message-
>> From: Vitaly Kuznetsov [mailto:vkuzn...@redhat.com]
>> Sent: Wednesday, October 26, 2016 4:12 AM
>> To: de...@linuxdriverproject.org
>> Cc: linux-kernel@vger.kernel.org; KY Srinivasan ;
>> Haiyang Zhang
>> Subject: [PATCH] Drivers: hv: vmbus
On Mon, Oct 24, 2016 at 04:27:45PM +0200, Daniel Vetter wrote:
> On Mon, Oct 24, 2016 at 12:14:14PM +0200, Arnd Bergmann wrote:
> > On Saturday, October 22, 2016 5:14:42 PM CEST Baoyou Xie wrote:
> > > We get 1 warning when building kernel with W=1:
> > > drivers/gpu/drm/i2c/tda998x_drv.c:1292:5: w
by adding an int *locked parameter to get_user_pages() callers to this function
can now utilise VM_FAULT_RETRY functionality.
Taken in conjunction with the patch series adding the same parameter to
get_user_pages_remote() this means all slow-path get_user_pages*() functions
will now have the abili
On Mon, Oct 31, 2016 at 10:52 AM, Simon Horman wrote:
> From: Simon Horman
> Subject: [PATCH] ARM: shmobile: only call rcar_gen2_clocks_init() if present
>
> The RZ/G1M (r8a7743) uses the R-Car Gen2 core, but not the R-Car Gen2 clock
> driver. This is a harbinger of a transition for R-Car Gen2 So
On 10/30/2016 09:41 PM, Rob Herring wrote:
> On Fri, Oct 21, 2016 at 10:44:45AM +0200, Neil Armstrong wrote:
>> Add Synopsys Designware MAC Glue layer for the Oxford Semiconductor OX820.
>>
>> Signed-off-by: Neil Armstrong
>> ---
>> .../devicetree/bindings/net/oxnas-dwmac.txt| 44 +
>
2016-10-31 10:52 GMT+01:00 Sekhar Nori :
> Hi Bartosz,
>
> On Monday 31 October 2016 03:10 PM, Bartosz Golaszewski wrote:
>> 2016-10-31 5:30 GMT+01:00 Rob Herring :
>>> On Wed, Oct 26, 2016 at 07:35:55PM +0200, Bartosz Golaszewski wrote:
Create the driver for the da8xx master peripheral priori
On Mon, Oct 31, 2016 at 09:15:43AM +, Luc, Piotr wrote:
> I think that in v4.9-rc2 the CPUID[7,0].edx bits can be masked out by
> applying noxsave to cmdline. Using directly cpu_count will result in
> passing the bits in edx to a guest directly while the xsaveopt and rest
> of AVX512 features b
Hi Bartosz,
On Monday 31 October 2016 03:10 PM, Bartosz Golaszewski wrote:
> 2016-10-31 5:30 GMT+01:00 Rob Herring :
>> On Wed, Oct 26, 2016 at 07:35:55PM +0200, Bartosz Golaszewski wrote:
>>> Create the driver for the da8xx master peripheral priority
>>> configuration and implement support for wr
On Mon, Oct 31, 2016 at 10:23:00AM +0100, Geert Uytterhoeven wrote:
> On Tue, Oct 25, 2016 at 10:37 AM, Geert Uytterhoeven
> wrote:
> > On Fri, Oct 21, 2016 at 11:07 PM, Arnd Bergmann wrote:
> >> On Friday, October 21, 2016 8:01:49 PM CEST Geert Uytterhoeven wrote:
> >>> > diff --git a/drivers/cl
Hello.
On 10/31/2016 2:02 AM, Paul Cercueil wrote:
Now that the jz4740-rtc driver supports devicetree, we can add a
devicetree node for it.
Signed-off-by: Paul Cercueil
Acked-by: Maarten ter Huurne
---
arch/mips/boot/dts/ingenic/jz4740.dtsi | 11 +++
1 file changed, 11 insertions(+)
Andrew Donnellan writes:
> On 31/10/16 08:34, Christophe JAILLET wrote:
>> 'cxl_dev_context_init()' returns an error pointer in case of error, not
>> NULL. So test it with IS_ERR.
>>
>> Signed-off-by: Christophe JAILLET
>
> Reviewed-by: Andrew Donnellan
>
>> ---
>> un-compiled because I don't h
Hello.
On 10/31/2016 2:02 AM, Paul Cercueil wrote:
This commit adds documentation for the device-tree bindings of the
jz4740-rtc driver, which supports the RTC unit present in the JZ4740 and
JZ4780 SoCs from Ingenic.
Signed-off-by: Paul Cercueil
Acked-by: Maarten ter Huurne
---
.../devicetr
On Mon, 31 Oct 2016, Ondrej Zary wrote:
> On Monday 31 October 2016, Finn Thain wrote:
> > On Sun, 30 Oct 2016, Ondrej Zary wrote:
> > > Trigger an IRQ first with a test IRQ handler to find out if it really
> > > works. Disable the IRQ if not.
> > >
> > > This prevents hang when incorrect IRQ was
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