Hi Rob,
On 27/03/17 15:34, Rob Herring wrote:
> On Sat, Mar 25, 2017 at 12:31 AM, Oza Pawandeep wrote:
>> it jumps to the parent node without examining the child node.
>> also with that, it throws "no dma-ranges found for node"
>> for pci dma-ranges.
>>
>> this patch fixes
hidpp->name can't be null.
Only HID++ 2.0 and above device supports the query.
Signed-off-by: Benjamin Tissoires
---
changes in v3:
- moved up in the series
new in v2
---
drivers/hid/hid-logitech-hidpp.c | 14 +++---
1 file changed, 7 insertions(+), 7
Or the device just answers a valid feature '0'.
Signed-off-by: Benjamin Tissoires
---
changes in v3:
- moved up in the series
no changes in v2
---
drivers/hid/hid-logitech-hidpp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
On 24/03/2017 19:47, Marc Zyngier wrote:
> On 23/03/17 17:03, Mason wrote:
>
>> On 23/03/2017 15:22, Marc Zyngier wrote:
>>
>>> On 23/03/17 13:05, Mason wrote:
>>>
+ writel_relaxed(status, pcie->msi_status); /* clear IRQs */
>>>
>>> Why isn't this your irq_ack method instead of open-coding
From: Kan Liang
Currently, the SMIs are visible to all performance counters. Because
many users want to measure everything including SMIs. But in some
cases, the SMI cycles should not be count. For example, to calculate
the cost of SMI itself. So a knob is needed.
When
On Mon, Mar 27, 2017 at 12:38 AM, Andrew Donnellan
wrote:
> On 01/02/17 07:24, Kees Cook wrote:
>>
>> From: Emese Revfy
>>
>> The kernel already has a mechanism to free up code and data memory that
>> is only used during kernel or module
> Il giorno 27 mar 2017, alle ore 16:30, Tony Lindgren ha
> scritto:
>
> […]
> I wonder if the following test patch allows the mode changing
> devices to been properly found? Of course it's just for testing,
> and scanning for devices takes now 5 seconds.. But it might
>
On Mon, 27 Mar 2017, Mason wrote:
> On 24/03/2017 19:22, Marc Zyngier wrote:
>
> > You cannot directly use a pointer to a u32 in any of the bitmap
> > operations. You need to copy the value to an unsigned long, and
> > apply the bitmap op on that.
>
> On my platform, find_first_zero_bit()
Hello,
I've got the following use-after-free report on
linux-next/65b2dc38291f9f27e5ec3b804d6eb3b5f79a3ce4.
==
BUG: KASAN: use-after-free in debug_spin_unlock
kernel/locking/spinlock_debug.c:97 [inline]
BUG: KASAN: use-after-free in
On 27/03/2017 16:46, Dmitry Vyukov wrote:
>
> Paul McKenney writes:
>
> ===
> Hmmm... I am not seeing a call to cleanup_srcu_struct() for the
> ->track_srcu field of the kvm_page_track_notifier_head structure.
> Or is this structure immortal, so that it is never cleaned up?
> Or am I just
[+Al,Darren to comment on _DSD review process]
On Mon, Mar 27, 2017 at 12:24:45PM +, Gabriele Paoloni wrote:
> Hi Marc Many thanks for your comments
>
> > -Original Message-
> > From: linuxarm-boun...@huawei.com [mailto:linuxarm-boun...@huawei.com]
> > On Behalf Of Marc Zyngier
> >
On Thu, 23 Mar 2017 05:07:20 +0900
Masahiro Yamada wrote:
> Collect multi NAND fixups into a helper function instead of
> scattering them in denali_init().
>
> I am rewording the comment block to clearly explain what is called
> "multi device".
I will take the
On 03/27/2017 05:14 PM, Petr Mladek wrote:
On Mon 2017-03-20 13:03:00, Aleksey Makarov wrote:
[..]
diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c
index fd752f0c8ef1..462036e7a767 100644
--- a/kernel/printk/printk.c
+++ b/kernel/printk/printk.c
@@ -1909,8 +1909,28 @@ static
On 25/03/17 18:23, Leo Yan wrote:
Coresight includes debug module and usually the module connects with CPU
debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has
description for related info in "Part H: External Debug".
Chapter H7 "The Sample-based Profiling Extension"
Unless they are connected through unifying, they don't support it,
so remove one error in the logs.
Signed-off-by: Benjamin Tissoires
---
changes in v3:
- moved up in the series
no changes in v2
---
drivers/hid/hid-logitech-hidpp.c | 2 ++
1 file changed, 2
Register 0xB5 should be handled specially no matter what function is
used. This allows to retrieve the serial and the Quad ID from
hid-logitech-hidpp directly.
Signed-off-by: Benjamin Tissoires
---
changes in v3:
- fixed 0xb5 to handle any incoming parameters
no
Unifying devices are different from others because they can probed
while not connected. So we need to talk to the receiver to get some
extra information like the device name and the serial.
Instead of having conditionals while attempting to read the device name
from HID++ 2.0, have a special init
This way, upower can add a simple udev rule to decide whether or not
it should use the internal unifying support or just the generic kernel
one.
Signed-off-by: Benjamin Tissoires
---
no changes in v3
no changes in v2
---
drivers/hid/hid-logitech-hidpp.c | 20
From: Pablo Neira Ayuso
> Sent: 27 March 2017 13:08
> On Sat, Mar 25, 2017 at 06:19:47PM +0530, Arushi Singhal wrote:
> > This patch removes multiple assignments.
> > Done using coccinelle.
> > @@
> > identifier i1,i2;
> > constant c;
> > @@
> > - i1=i2=c;
> > + i1=c;
> > + i2=c;
>
> You have to
On Tue, Mar 28, 2017 at 04:39:25PM +0800, Changpeng Liu wrote:
> Currently virtio-blk driver does not provide discard feature flag, so the
> filesystems which built on top of the block device will not send discard
> command. This is okay for HDD backend, but it will impact the performance
> for
On Fri, Mar 24, 2017 at 02:47:09PM +0300, Kirill A. Shutemov wrote:
>
> From d2f416a3ee3e5dbb10e59d0b374d382fdc4ba082 Mon Sep 17 00:00:00 2001
> From: "Kirill A. Shutemov"
> Date: Fri, 24 Mar 2017 14:13:05 +0300
> Subject: [PATCH] mm: Fix false-positive
On Mon, Mar 27, 2017 at 4:45 PM, none wrote:
> Hello,
>
> There’s three way to perform an invalid memory access :
>
> The attempt to execute/jump at an invalid address.
> The attempt to read at an invalid address.
> The attempt to write at an invalid address.
>
> Determining
From: Kan Liang
Having msr_set/clear_bit on many cpus or given CPU can avoid extra
unnecessory IPIs and simplify MSR content manipulation, when it only
needs to flip a bit.
There is already msr_set/clear_bit, but missing the _on_cpu and _on_cpus
version.
Signed-off-by: Kan
From: Kan Liang
Currently, there is no way to measure the time cost in System management
mode (SMM) by perf.
Intel perfmon supports FREEZE_WHILE_SMM bit in IA32_DEBUGCTL. Once it sets,
the PMU core counters will freeze on SMI handler. But it will not have an
effect on free
On Mon, Mar 27, 2017 at 04:56:51PM +0200, Luca Abeni wrote:
> > > +u64 grub_reclaim(u64 delta, struct rq *rq, u64 u)
> > > {
> > > + u64 u_act;
> > > +
> > > + if (rq->dl.this_bw - rq->dl.running_bw > (1 << 20) - u)
> > > + u_act = u;
> > > + else
> > > + u_act = (1 << 20) -
On Mon, Mar 27, 2017 at 10:40:23AM +0800, Zhang Rui wrote:
> On Sun, 2017-03-26 at 12:26 +0100, Andrey Utkin wrote:
> > On Fri, Mar 10, 2017 at 10:07:35AM +0100, Greg Kroah-Hartman wrote:
> > >
> > > 4.10-stable review patch. If anyone has any objections, please let
> > > me know.
> > >
> > >
> >
>> > [auto build test WARNING on tip/perf/core]
>> > [also build test WARNING on v4.11-rc4 next-20170327]
>> > [if your patch is applied to the wrong git tree, please drop us a note to
>> > help improve the system]
>> >
>> > url:
On x86-32, with CONFIG_FIRMWARE and multiple CPUs, if you enable
function graph tracing and then suspend to RAM, it will triple fault and
reboot when it resumes.
The first fault happens when booting a secondary CPU:
startup_32_smp()
load_ucode_ap()
prepare_ftrace_return()
* Kishon Vijay Abraham I [170326 23:27]:
> On Thursday 23 March 2017 05:16 AM, Tony Lindgren wrote:
> > +static const struct phy_ops ops = {
> > + .owner = THIS_MODULE,
> > +};
>
> Given that this phy doesn't have any phy_ops, Is there a reason for
> registering
> this
On 3/22/2017 10:53 AM, bod...@mellanox.com wrote:
From: Bodong Wang
Sometimes it is not desirable to probe the virtual functions after
SRIOV is enabled. This can save host side resource usage by VF
instances which would be eventually probed to VMs.
Add a new PCI sysfs
On Sat, Mar 25, 2017 at 12:31 AM, Oza Pawandeep wrote:
> it is possible that PCI device supports 64-bit DMA addressing,
> and thus it's driver sets device's dma_mask to DMA_BIT_MASK(64),
> however PCI host bridge may have limitations on the inbound
> transaction addressing.
On Mon, 27 Mar 2017 13:28:29 +0530
Ravi Bangoria wrote:
> SDT marker argument is in N@OP format. Here OP is arch dependent
> component. Add powerpc logic to parse OP and convert it to uprobe
> compatible format.
Looks good to me.
Acked-by: Masami Hiramatsu
> > 2 --
> > 1 file changed, 2 deletions(-)
>
> Ugh, Alan, what's going on here, I thought you fixed this?
I sent you a patch that removed the arrays entirely and turned it into
a single string as well as removing the define. Not quite sure what
happened but I've resynched to -next and I'll
On Mon, 27 Mar 2017 16:53:09 +0200
Arnd Bergmann wrote:
> > Actually, I believe that "%zd" will work. It's made to work with size_t
> > which is long long on 32 and long on 64.
>
> size_t is always 'long', not 'long long'. We have %pad for dma_addr_t
> which may be 'long' or
On Mon, Mar 27, 2017 at 5:30 PM, Steven Rostedt wrote:
> On Mon, 27 Mar 2017 16:53:09 +0200
>> We could probably introduce a %pts format string for timespec64
>> and have that pretty-printed.
>
> Hmm, probably don't want a %p as that suggests its a pointer, which it
> should
2017-03-27 21:20 GMT+09:00 Nicolas Dichtel :
>
>
> Patches #1 and #2 are just cleanup: some exported headers were still under
> a non-uapi directory. Patch #3 is a fix to avoid exporting a file that was
> not under an uapi directory.
> After these three patches, all
This patch converts tpm_tis to use of the new tpm class ops
request_locality, and relinquish_locality.
With the move to using the callbacks, release_locality is changed so
that we now release the locality even if there is no request pending.
This required some changes to the tpm_tis_core_init
On Mon, 2017-03-27 at 16:59 +0200, Benjamin Tissoires wrote:
> Hi,
>
> this is finally a rework of the series that provides kernel
> power_supply
> for hidpp devices.
>
> This will allow upower to not handle those devices anymore and to
> have more
> immediate reportng of the device to the
Às 7:19 AM de 3/23/2017, Niklas Cassel escreveu:
> On 03/22/2017 04:47 PM, Joao Pinto wrote:
>> Hi Niklas,
>>
>> Às 2:43 PM de 3/21/2017, Niklas Cassel escreveu:
>>> From: Niklas Cassel
>>>
>>> Fix the following crash, seen in dwc/pcie-artpec6.
>>>
>>> Unable to handle
Hi Wendy,
On 03/24/2017 02:22 PM, Wendy Liang wrote:
> This patch enables the remoteproc to specify the shared memory.
> Remoteproc declared this memory as DMA memory.
> It can be used for virtio, or shared buffers.
You should be able to achieve this without any remoteproc core changes.
You can
Hello,
On 03/27/2017 03:12 AM, Thomas Scariah wrote:
> From: "Scariah, Thomas"
>
> Added functions to support ethtool to print the phy statistics and error
> information along with other ethtool statistics. This will help ethtool
> information to know the error is
Hi Peter,
On Mon, 27 Mar 2017 16:03:41 +0200
Peter Zijlstra wrote:
> On Fri, Mar 24, 2017 at 04:53:02AM +0100, luca abeni wrote:
>
> > +static inline
> > +void __dl_update(struct dl_bw *dl_b, s64 bw)
> > +{
> > + struct root_domain *rd = container_of(dl_b, struct
> >
Hello,
There’s three way to perform an invalid memory access :
The attempt to execute/jump at an invalid address.
The attempt to read at an invalid address.
The attempt to write at an invalid address.
Determining the execute case with rt_sigaction is easy : the last value
of eip match the
When ONLINE isn't set, upower should ignore the battery capacity,
so there is no need to overload it with some random values.
Signed-off-by: Benjamin Tissoires
---
completely reworked in v3:
- store a online field in hidpp->battery to be able to fine control
CAPACITY LEVEL allows to forward rough information on the battery mileage.
HID++ 2.0 devices will either report percentage or levels, so better
forwarding this information to the user space.
The M325 supports only 2 levels: 'Full' and 'Critical'. With mileage,
it will report either 90% or 5%,
The power_supply term for the percentage is capacity. Capacity level
can be given when non accurate mileage is provided by the device, so
better stick to the terms used in power_supply.
Signed-off-by: Benjamin Tissoires
---
new in v3
---
On 24/03/17 18:00, Christoffer Dall wrote:
On Mon, Mar 20, 2017 at 06:26:42PM +, Suzuki K Poulose wrote:
In order to perform an operation on a gpa range, the hyp iterates
the hyp ?
To be precise "the host" ?
over each page in a user memory slot for the given range. This is
On 27/03/2017 16:46, Thomas Gleixner wrote:
> On Mon, 27 Mar 2017, Mason wrote:
>
>> On 24/03/2017 19:22, Marc Zyngier wrote:
>>
>>> You cannot directly use a pointer to a u32 in any of the bitmap
>>> operations. You need to copy the value to an unsigned long, and
>>> apply the bitmap op on that.
On Sat, Mar 25, 2017 at 12:52:58PM +0300, Ivan Safonov wrote:
> DIV_ROUND_UP is bit useful than series of "/" and "%" operations.
> Replace "/%" sequence with DIV_ROUND_UP macro.
>
> Signed-off-by: Ivan Safonov
Applied. Thanks.
-Bin.
> ---
> Changes in v2:
> - little
On Mon, 2017-03-27 at 15:37 +0200, Stefan Wahren wrote:
> In order to share common functions between QCA7000 SPI and UART
> protocol
> driver the qca_common needs to be a separate kernel module.
Maybe "qca_eth_common"? There are many things Qualcomm, slightly fewer
things Qualcomm Atheros, and
On Mon, 27 Mar 2017 17:35:13 +0200
Arnd Bergmann wrote:
> On Mon, Mar 27, 2017 at 5:30 PM, Steven Rostedt wrote:
> > On Mon, 27 Mar 2017 16:53:09 +0200
> >> We could probably introduce a %pts format string for timespec64
> >> and have that pretty-printed.
On Monday, March 13, 2017 10:05:09 PM CEST Alban wrote:
> The current binding only cover PCI devices so extend it for SoC devices.
>
> Most SoC platforms use an MTD partition for the calibration data
> instead of an EEPROM. The qca,no-eeprom property was added to allow
> loading the EEPROM
This patch bring support for non-folded additional page table level.
Signed-off-by: Kirill A. Shutemov
Cc: Dmitry Vyukov
Cc: Andrey Ryabinin
---
arch/x86/mm/kasan_init_64.c | 18 --
1 file changed,
Looks like all users don't care about a disconnect.
Simplify the various variant_connect() and put the connect state check
at the beginning.
For delayed input devices, make sure we go through all other connect
values (protocol, battery) before bailing out.
Signed-off-by: Benjamin Tissoires
The Solar Keyboard uses a different feature to report the battery level.
Signed-off-by: Benjamin Tissoires
---
changes in v3:
- fixed online status
changes in v2:
* update state according to lux information
* do not update Lux if the event does not contain lux
Better forwarding the device name, manufacturer and serial to upower.
Note that serial is still empty, it will be filled in a later patch
in this series.
Signed-off-by: Benjamin Tissoires
---
changes in v3:
- moved up in the series
changes in v2:
* model
Do not pollute the quirks bits field which is public API
with elements that are queried from the device.
Move the 2 battery capabilities into the new field.
Signed-off-by: Benjamin Tissoires
---
new in v3
---
drivers/hid/hid-logitech-hidpp.c | 10 ++
1
Battery events are reported through HID++, so we need to be sure
the report ID is the HID++ one.
Without this, we might receive keyboard events that looks just like
battery events with wrong data and which will confuse user space.
Signed-off-by: Benjamin Tissoires
Hi,
this is finally a rework of the series that provides kernel power_supply
for hidpp devices.
This will allow upower to not handle those devices anymore and to have more
immediate reportng of the device to the system.
I have splitted the series to not support non unifying receivers here. I
Le lundi 27 mars 2017 à 10:45 +0200, Hans Verkuil a écrit :
> > > timestamp and sequence are only set for CAPTURE, not OUTPUT. Is
> > > that correct?
> >
> > Correct. I can add sequence for the OUTPUT queue too, but I have no
> > idea how that sequence is used by userspace.
>
> You set
- Original Message -
> From: "Fam Zheng"
> To: linux-kernel@vger.kernel.org
> Cc: "Martin K. Petersen" , f...@redhat.com,
> linux-s...@vger.kernel.org, "James E.J.
> Bottomley"
> Sent: Monday, March 27, 2017
5-level paging support is required from hardware when compiled with
CONFIG_X86_5LEVEL=y.
We will implement boot-time switch between 4- and 5-level paging later.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/boot/cpucheck.c | 9 +
Add operations to allocate/release p4ds.
Xen requires more work. We will need to come back to it.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/include/asm/paravirt.h | 37 ---
arch/x86/include/asm/paravirt_types.h | 7
We don't need the assert anymore. 17be0aec74fb ("x86/asm/entry/64:
Implement better check for canonical addresses") made canonical
address check generic wrt. address width.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/entry/entry_64.S | 7 ++-
1 file
We don't need extra virtual address space for ESPFIX, so it stays within
one PUD page table for both 4- and 5-level paging.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/kernel/espfix_64.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff
Simple extension to support one more page table level.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/mm/dump_pagetables.c | 49 ---
1 file changed, 42 insertions(+), 7 deletions(-)
diff --git
The first part of memory map (up to %esp fixup) simply scales existing
map for 4-level paging by factor of 9 -- number of bits addressed by
additional page table level.
The rest of the map is unchanged.
Signed-off-by: Kirill A. Shutemov
---
Here's the third bunch of patches of 5-level patchset.
This time we prepare code to handle non-folded version of the additional page
table level.
Kirill A. Shutemov (8):
x86/boot: Detect 5-level paging support
x86/asm: Remove __VIRTUAL_MASK_SHIFT==47 assert
x86/mm: Define virtual memory
Extends pagetable headers to support new paging mode.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/include/asm/pgtable_64.h | 11 +++
arch/x86/include/asm/pgtable_64_types.h | 20 +++
arch/x86/include/asm/pgtable_types.h| 10
On Mon 27-03-17 12:36:17, kernel test robot wrote:
> FYI, we noticed the following commit:
>
> commit: 0ee0efcf7c7968fb045454f621b5681e94b2c288 ("fsnotify: Move queueing of
> mark for destruction into fsnotify_put_mark()")
> https://git.kernel.org/cgit/linux/kernel/git/jack/linux-fs.git
On Mon, 27 Mar 2017 16:26:33 +0200
Peter Zijlstra wrote:
> On Fri, Mar 24, 2017 at 04:53:01AM +0100, luca abeni wrote:
> > From: Luca Abeni
> >
> > Instead of decreasing the runtime as "dq = -Uact dt" (eventually
> > divided by the maximum
The creation of the power_supply should not be in a HID++ 2.0 specific
function.
Signed-off-by: Benjamin Tissoires
---
changes in v3:
- moved up in the series
no changes in v2
---
drivers/hid/hid-logitech-hidpp.c | 94 ++--
1
From: Bastien Nocera
Without a scope defined, UPower assumes that the battery provides
power to the computer it's connected to, like a laptop battery or a UPS.
Tested-by: Peter Hutterer
Signed-off-by: Bastien Nocera
Both atmel-ebi and atmel-sdram are maintained as part of the Atmel ARM
SoCs.
Signed-off-by: Alexandre Belloni
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index c45c02bc6082..6531d239db6b 100644
---
Le 27/03/2017 à 17:21, Alexandre Belloni a écrit :
> Both atmel-ebi and atmel-sdram are maintained as part of the Atmel ARM
> SoCs.
>
> Signed-off-by: Alexandre Belloni
Acked-by: Nicolas Ferre
> ---
> MAINTAINERS | 1 +
> 1
On x86-32, with CONFIG_FIRMWARE and multiple CPUs, if you enable
function graph tracing and then suspend to RAM, it will triple fault and
reboot when it resumes.
The first fault happens when booting a secondary CPU:
startup_32_smp()
load_ucode_ap()
prepare_ftrace_return()
On (03/26/17 22:47), Samuel Thibault wrote:
> commit bbeddf52adc1 ("printk: move braille console support into
> separate braille.[ch] files") introduced _braille_console_setup()
> to outline the braille initialization code. There was however some
> confusion over the value it was supposed to
On Montag, 6. März 2017 12:34:13 CEST Mauro Carvalho Chehab wrote:
> Em Sat, 4 Mar 2017 03:23:42 +0200
>
> Antti Palosaari escreveu:
> > On 03/03/2017 08:35 PM, Brüns, Stefan wrote:
> > > On Fr, 2017-02-17 at 01:55 +0100, Stefan Brüns wrote:
> > >> The required command sequence for
> > static int cpsw_get_sset_count(struct net_device *ndev, int sset)
> > {
> > + struct cpsw_priv *priv = netdev_priv(ndev);
> > + int slave_no = cpsw_slave_index(priv);
> > + int count;
> > +
> > switch (sset) {
> > case ETH_SS_STATS:
> > - return CPSW_STATS_LEN;
> > +
On Monday, March 27, 2017 06:13:36 PM Juri Lelli wrote:
> On 27/03/17 19:05, Rafael J. Wysocki wrote:
> > On Monday, March 27, 2017 06:01:34 PM Juri Lelli wrote:
> > > On 27/03/17 18:50, Peter Zijlstra wrote:
> > > > On Fri, Mar 24, 2017 at 02:08:58PM +, Juri Lelli wrote:
> > > > > Worker
Hello Matthias,
On 03/27/2017 01:39 PM, Matthias Kaehlcke wrote:
> Thanks for the reviews and testing!
>
You are welcome.
[snip]
+ if (ops->get_voltage || ops->get_voltage_sel)
>>
>> It's valid to have a .get_voltage_sel callback without a .list_voltage?
>>
>> At least it seems
> -Original Message-
> From: devel [mailto:driverdev-devel-boun...@linuxdriverproject.org] On
> Behalf Of k...@exchange.microsoft.com
> Sent: Friday, March 24, 2017 11:07 AM
> To: helg...@kernel.org; linux-...@vger.kernel.org; linux-
> ker...@vger.kernel.org; de...@linuxdriverproject.org;
On Wed, Mar 22, 2017 at 10:10:49AM -0700, Tony Lindgren wrote:
> At least Motorola CPCAP PMIC needs it's device interrupts re-read
> until there are no more interrupts. Otherwise the PMIC interrupt to
> the SoC will eventually stop toggling. This seems to be a bug in the
> CPCAP PMIC where it can
each queue will have a state machine. Initially queue is in LIMIT_LOW
state, which means all cgroups will be throttled according to their low
limit. After all cgroups with low limit cross the limit, the queue state
gets upgraded to LIMIT_MAX state.
For max limit, cgroup will use the limit
From: Ben Shelton
Add a file under debugfs to allow easy access to the erase count for
each physical erase block on an UBI device. This is useful when
debugging data integrity issues with UBIFS on NAND flash devices.
Signed-off-by: Ben Shelton
Em Mon, Mar 27, 2017 at 04:10:38PM +0900, Taeung Song escreveu:
> If running 'perf annotate --stdio -l --show-total-period',
> you can see a problem showing only zero '0' for number of samples.
>
> Before:
> $ perf annotate --stdio -l --show-total-period
> ...
>0 :400816:
On Mon, 2017-03-27 at 19:05 +0200, Christoph Hellwig wrote:
> Hi Mike,
>
> does the patch below fix that issue for you?
Thanks, I'll give it a go in the A.M.
BTW, WRT RT woes with $subject, I tried booting a generic kernel with
threadirqs, and bingo, same deal, just a bit more painful than for
Hi,
cgroup still lacks a good iocontroller. CFQ works well for hard disk, but not
much for SSD. This patch set try to add a conservative limit for blk-throttle.
It isn't a proportional scheduling, but can help prioritize cgroups. There are
several advantages we choose blk-throttle:
- blk-throttle
On Sun, Mar 26, 2017 at 3:54 AM, Julia Lawall wrote:
> Is an unlock needed before line 848? Or does blkg_lookup_check take care
> of it?
Unlock is not needed. On success, function returns with locks held.
It is documented at line 805:
"... This function returns with RCU
Add low limit for cgroup and corresponding cgroup interface. To be
consistent with memcg, we allow users configure .low limit higher than
.max limit. But the internal logic always assumes .low limit is lower
than .max limit. So we add extra bps/iops_conf fields in throtl_grp for
userspace
Em Wed, Mar 22, 2017 at 03:06:18PM +0200, Tommi Rantala escreveu:
> Hi,
>
> Some small perf fixes, mostly caught with valgrind.
>
> The last patch is a simplification: it is easier to open /proc/self/exe
> than /proc/$pid/exe.
Thanks, applied the series.
- Arnaldo
> Tommi Rantala (6):
>
On Mon, 27 Mar 2017 09:56:47 +0800
Wanpeng Li wrote:
> Actually after I bisect, the first bad commit is ff9a9b4c4334 ("sched,
> time: Switch VIRT_CPU_ACCOUNTING_GEN to jiffy granularity"). The bug
> can be reproduced readily if CONFIG_CONTEXT_TRACKING_FORCE is true,
> then
On Fri, Mar 24, 2017 at 02:08:58PM +, Juri Lelli wrote:
> Worker kthread needs to be able to change frequency for all other
> threads.
>
> Make it special, just under STOP class.
*yuck* ;-)
So imagine our I2C/SPI bus is 'busy' and its mutex taken, then this
'soecial' task will need to boost
On Mon, Mar 27, 2017 at 08:47:37AM -0700, kan.li...@intel.com wrote:
> From: Kan Liang
>
> Having msr_set/clear_bit on many cpus or given CPU can avoid extra
> unnecessory IPIs
How does that happen?
You have smp_call_function_many() sending IPIs to each CPU in the mask.
Our chosen ic_dev may be anywhere in our list of ic_devs, and we may
free it before attempting to close others. When we compare d->dev and
ic_dev->dev, we're potentially dereferencing memory returned to the
allocator. This causes KASAN to scream for each subsequent ic_dev we
check.
As there's a
On 27/03/17 16:53, Mason wrote:
> On 24/03/2017 19:47, Marc Zyngier wrote:
>
>> On 23/03/17 17:03, Mason wrote:
>>
>>> On 23/03/2017 15:22, Marc Zyngier wrote:
>>>
On 23/03/17 13:05, Mason wrote:
> + writel_relaxed(status, pcie->msi_status); /* clear IRQs */
Why isn't this
* Moreno Bartalucci [170327 09:23]:
> If I understood your patch, however, if the device (anyone, not just my one)
> takes longer to switch, VBUS is deasserted anyway.
Yeah some of them can take at least 10 seconds even to enumerate.
So probably we need to have
From: Colin Ian King
err is being checked for failure each time it is being updated
so this err check is totally redundant and can be removed
Detected with CoverityScan, CID#1420665 ("Logically dead code")
Signed-off-by: Colin Ian King
---
When cgroups all reach low limit, cgroups can dispatch more IO. This
could make some cgroups dispatch more IO but others not, and even some
cgroups could dispatch less IO than their low limit. For example, cg1
low limit 10MB/s, cg2 limit 80MB/s, assume disk maximum bandwidth is
120M/s for the
User configures latency target, but the latency threshold for each
request size isn't fixed. For a SSD, the IO latency highly depends on
request size. To calculate latency threshold, we sample some data, eg,
average latency for request size 4k, 8k, 16k, 32k .. 1M. The latency
threshold of each
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