On 04/06/2017 11:49 AM, Steven Rostedt wrote:
>> >
>> > This tftp's the kernel image (Image.q) and then boots. I'm having
>> > difficulty figuring out how to implement that in ktest.
>> >
> Can you make a script do this? If so, then you can simply tell ktest to
> call that script. See the
On 04/06/2017 11:49 AM, Steven Rostedt wrote:
>> >
>> > This tftp's the kernel image (Image.q) and then boots. I'm having
>> > difficulty figuring out how to implement that in ktest.
>> >
> Can you make a script do this? If so, then you can simply tell ktest to
> call that script. See the
On Thu, Apr 06, 2017 at 05:48:47PM +0100, Al Viro wrote:
> * use unaligned.h, not unaligned/access_ok.h
... which got misspelled in that patch, sorry... Fixed variant follows:
commit b3e79ba1708c9b74781079c9f8617448fce36b51
Author: Al Viro
Date: Thu Apr 6 12:42:14
On Thu, Apr 06, 2017 at 05:48:47PM +0100, Al Viro wrote:
> * use unaligned.h, not unaligned/access_ok.h
... which got misspelled in that patch, sorry... Fixed variant follows:
commit b3e79ba1708c9b74781079c9f8617448fce36b51
Author: Al Viro
Date: Thu Apr 6 12:42:14 2017 -0400
nfc: fix
Hi Jassi/Sudeep,
On Wed, Mar 29, 2017 at 07:01:09PM +0100, Sudeep Holla wrote:
>
>
> On 29/03/17 18:43, Jassi Brar wrote:
> > Currently two threads, wait on blocking requests, could wake up for
> > completion of request of each other as ...
> >
> > Thread#1(T1)
Hi Jassi/Sudeep,
On Wed, Mar 29, 2017 at 07:01:09PM +0100, Sudeep Holla wrote:
>
>
> On 29/03/17 18:43, Jassi Brar wrote:
> > Currently two threads, wait on blocking requests, could wake up for
> > completion of request of each other as ...
> >
> > Thread#1(T1)
Both typos are in example 3.
Because cache id 0 is the only cache id, the ";" is redundant in
"# echo "L3:0=ffc00;" > p0/schemata".
And "C0" in "# echo C0 > p0/cpus" is wrong because it specifies core
6-7 instead of wanted core 4-7.
Correct the typos to avoid confusion.
Signed-off-by: Xiaochen
Both typos are in example 3.
Because cache id 0 is the only cache id, the ";" is redundant in
"# echo "L3:0=ffc00;" > p0/schemata".
And "C0" in "# echo C0 > p0/cpus" is wrong because it specifies core
6-7 instead of wanted core 4-7.
Correct the typos to avoid confusion.
Signed-off-by: Xiaochen
On Thu, Apr 06, 2017 at 10:43:19PM +0800, Jin, Yao wrote:
>
>
> On 4/6/2017 5:25 PM, Peter Zijlstra wrote:
> > On Thu, Apr 06, 2017 at 04:21:06PM +0800, Jin, Yao wrote:
> > > Hi, otherwise we have to maintain 2 branch type copies between kernel and
> > > user-space.
> > >
> > > For example,
On Thu, Apr 06, 2017 at 10:43:19PM +0800, Jin, Yao wrote:
>
>
> On 4/6/2017 5:25 PM, Peter Zijlstra wrote:
> > On Thu, Apr 06, 2017 at 04:21:06PM +0800, Jin, Yao wrote:
> > > Hi, otherwise we have to maintain 2 branch type copies between kernel and
> > > user-space.
> > >
> > > For example,
On Thu, Apr 06, 2017 at 08:18:33AM +0200, Paul Menzel wrote:
> Indeed, that improves the situation. I still need to pass `force=1` to the
> module to get `/dev/tpm0`. No idea, why it’s not in included in Linux 4.9
> yet.
Fair point.. Jarkko - could you forward that patch to -stable?
> $
On Thu, Apr 06, 2017 at 08:18:33AM +0200, Paul Menzel wrote:
> Indeed, that improves the situation. I still need to pass `force=1` to the
> module to get `/dev/tpm0`. No idea, why it’s not in included in Linux 4.9
> yet.
Fair point.. Jarkko - could you forward that patch to -stable?
> $
On Thu, Apr 06, 2017 at 06:21:55PM +0200, Michal Hocko wrote:
> > This was my first time using your git branch instead of applying the patches
> > from this thread to v4.11-rc5 myself.
>
> OK, so this looks like another thing to resolve. I have seen this
> warning as well but I didn't consider it
On Thu, Apr 06, 2017 at 06:21:55PM +0200, Michal Hocko wrote:
> > This was my first time using your git branch instead of applying the patches
> > from this thread to v4.11-rc5 myself.
>
> OK, so this looks like another thing to resolve. I have seen this
> warning as well but I didn't consider it
Hi Alex,
On 06/04/2017 16:53, Alex Williamson wrote:
> If the mmap_sem is contented then the vfio type1 IOMMU backend will
> defer locked page accounting updates to a workqueue task. This has
> a few problems and depending on which side the user tries to play,
> they might be over-penalized for
Hi Alex,
On 06/04/2017 16:53, Alex Williamson wrote:
> If the mmap_sem is contented then the vfio type1 IOMMU backend will
> defer locked page accounting updates to a workqueue task. This has
> a few problems and depending on which side the user tries to play,
> they might be over-penalized for
On Thu, 2017-04-06 at 10:49 -0400, Johannes Weiner wrote:
> On Wed, Apr 05, 2017 at 06:11:04PM -0400, Rik van Riel wrote:
> > On Tue, 2017-04-04 at 18:00 -0400, Johannes Weiner wrote:
> >
> > > +
> > > + /*
> > > + * When refaults are being observed, it means a new
> > > workingset
> > > + * is
On Thu, 2017-04-06 at 10:49 -0400, Johannes Weiner wrote:
> On Wed, Apr 05, 2017 at 06:11:04PM -0400, Rik van Riel wrote:
> > On Tue, 2017-04-04 at 18:00 -0400, Johannes Weiner wrote:
> >
> > > +
> > > + /*
> > > + * When refaults are being observed, it means a new
> > > workingset
> > > + * is
On Thu, 06 Apr 2017, Laurent Dufour wrote:
How is 'seqnum' wrapping handled here ?
I'd rather see something like time_before() here, isn't it ?
Its a 64bit counter, no overflows.
On Thu, 06 Apr 2017, Laurent Dufour wrote:
How is 'seqnum' wrapping handled here ?
I'd rather see something like time_before() here, isn't it ?
Its a 64bit counter, no overflows.
On 06/04/17 15:05, Andrew Lunn wrote:
>>> Do you really need more than one GPIO? A single gpio would make all
>>> this code a lot simpler.
>>>
>>
>> Yes we need. Some of our boards have separate GPIO RESET lines for
>> different PHYs on the same MDIO bus.
>
> If you have a one-to-one mapping of
I added LKML (others may want to know this too), and John, who's going
to help me maintain ktest.
On Thu, 6 Apr 2017 11:34:45 -0500
Timur Tabi wrote:
> On 04/05/2017 08:53 PM, Steven Rostedt wrote:
> >> > Why is it prompting me for the MACHINE when I've specified it in
I added LKML (others may want to know this too), and John, who's going
to help me maintain ktest.
On Thu, 6 Apr 2017 11:34:45 -0500
Timur Tabi wrote:
> On 04/05/2017 08:53 PM, Steven Rostedt wrote:
> >> > Why is it prompting me for the MACHINE when I've specified it in the
> >> > ktest.conf
On 06/04/17 15:05, Andrew Lunn wrote:
>>> Do you really need more than one GPIO? A single gpio would make all
>>> this code a lot simpler.
>>>
>>
>> Yes we need. Some of our boards have separate GPIO RESET lines for
>> different PHYs on the same MDIO bus.
>
> If you have a one-to-one mapping of
* use unaligned.h, not unaligned/access_ok.h
* if a local variable of type uint16_t is unaligned, your compiler is FUBAR
* the whole point of get_unaligned_... is to avoid memcpy + ..._to_cpu().
Using it *after* memcpy() (into aligned object, no less) is pointless.
Signed-off-by: Al Viro
* use unaligned.h, not unaligned/access_ok.h
* if a local variable of type uint16_t is unaligned, your compiler is FUBAR
* the whole point of get_unaligned_... is to avoid memcpy + ..._to_cpu().
Using it *after* memcpy() (into aligned object, no less) is pointless.
Signed-off-by: Al Viro
On Thu, Apr 06, 2017 at 07:02:15AM +0300, Kalle Valo wrote:
> Brian Norris writes:
>
> > nl80211 provides the NL80211_SCAN_FLAG_RANDOM_ADDR for every scan
> > request that should be randomized; the absence of such a flag means we
> > should not randomize. However,
On Thu, Apr 06, 2017 at 07:02:15AM +0300, Kalle Valo wrote:
> Brian Norris writes:
>
> > nl80211 provides the NL80211_SCAN_FLAG_RANDOM_ADDR for every scan
> > request that should be randomized; the absence of such a flag means we
> > should not randomize. However, mwifiex was stashing the latest
Hi Mark,
On 6 April 2017 at 02:38, Mark Rutland wrote:
> Hi,
>
> I tried to fix the issue that Lornzo raised, such that I could queue
> these patches. From looking at this patch in more detail however, I
> think there are further issues that need to be addressed.
>
> On
Hi Mark,
On 6 April 2017 at 02:38, Mark Rutland wrote:
> Hi,
>
> I tried to fix the issue that Lornzo raised, such that I could queue
> these patches. From looking at this patch in more detail however, I
> think there are further issues that need to be addressed.
>
> On Sat, Apr 01, 2017 at
Hi Alex,
On 06/04/2017 16:43, Alex Williamson wrote:
> On Thu, 6 Apr 2017 10:23:59 +0200
> Auger Eric wrote:
>
>> Hi Alex,
>>
>> On 03/04/2017 22:02, Alex Williamson wrote:
>>> If the mmap_sem is contented then the vfio type1 IOMMU backend will
>>> defer locked page
Hi Alex,
On 06/04/2017 16:43, Alex Williamson wrote:
> On Thu, 6 Apr 2017 10:23:59 +0200
> Auger Eric wrote:
>
>> Hi Alex,
>>
>> On 03/04/2017 22:02, Alex Williamson wrote:
>>> If the mmap_sem is contented then the vfio type1 IOMMU backend will
>>> defer locked page accounting updates to a
From: "Steven Rostedt (VMware)"
The function tracer needs to be more careful than other subsystems when it
comes to freeing data. Especially if that data is actually executable code.
When a single function is traced, a trampoline can be dynamically allocated
which is called
From: "Steven Rostedt (VMware)"
The updates to the trace_active per cpu variable can be updated with the
this_cpu_*() functions as it only gets updated on the CPU that the variable
is on.
Signed-off-by: Steven Rostedt (VMware)
---
From: "Steven Rostedt (VMware)"
The function tracer needs to be more careful than other subsystems when it
comes to freeing data. Especially if that data is actually executable code.
When a single function is traced, a trampoline can be dynamically allocated
which is called to jump to the
From: "Steven Rostedt (VMware)"
The updates to the trace_active per cpu variable can be updated with the
this_cpu_*() functions as it only gets updated on the CPU that the variable
is on.
Signed-off-by: Steven Rostedt (VMware)
---
kernel/trace/trace_stack.c | 23 +++
1
From: "Paul E. McKenney"
The tracing subsystem started using rcu_irq_entry() and rcu_irq_exit()
(with my blessing) to allow the current _rcuidle alternative tracepoint
name to be dispensed with while still maintaining good performance.
Unfortunately, this causes RCU's
From: "Paul E. McKenney"
The tracing subsystem started using rcu_irq_entry() and rcu_irq_exit()
(with my blessing) to allow the current _rcuidle alternative tracepoint
name to be dispensed with while still maintaining good performance.
Unfortunately, this causes RCU's dyntick-idle entry code's
From: "Steven Rostedt (VMware)"
There are certain parts of the kernel that can not let stack tracing
proceed (namely in RCU), because the stack tracer uses RCU, and parts of RCU
internals can not handle having RCU read side locks taken.
Add stack_tracer_disable() and
From: "Steven Rostedt (VMware)"
There are certain parts of the kernel that can not let stack tracing
proceed (namely in RCU), because the stack tracer uses RCU, and parts of RCU
internals can not handle having RCU read side locks taken.
Add stack_tracer_disable() and stack_tracer_enable()
Paul, can you take a quick look at these patches. Namely patch 1, 3 and 4.
I modified your patch to use the updated name for stack_tracer_disable().
If all looks well, can you give them your ack.
Thanks!
-- Steve
Paul E. McKenney (1):
rcu: Fix dyntick-idle tracing
Steven Rostedt
Paul, can you take a quick look at these patches. Namely patch 1, 3 and 4.
I modified your patch to use the updated name for stack_tracer_disable().
If all looks well, can you give them your ack.
Thanks!
-- Steve
Paul E. McKenney (1):
rcu: Fix dyntick-idle tracing
Steven Rostedt
On Thu, Apr 06, 2017 at 06:22:44PM +0200, Juergen Gross wrote:
> On 06/04/17 18:06, Daniel Kiper wrote:
> > Hi Julien,
> >
> > On Thu, Apr 06, 2017 at 04:39:13PM +0100, Julien Grall wrote:
> >> Hi Daniel,
> >>
> >> On 06/04/17 16:20, Daniel Kiper wrote:
> >>> On Thu, Apr 06, 2017 at 04:38:24PM
On Thu, Apr 06, 2017 at 06:22:44PM +0200, Juergen Gross wrote:
> On 06/04/17 18:06, Daniel Kiper wrote:
> > Hi Julien,
> >
> > On Thu, Apr 06, 2017 at 04:39:13PM +0100, Julien Grall wrote:
> >> Hi Daniel,
> >>
> >> On 06/04/17 16:20, Daniel Kiper wrote:
> >>> On Thu, Apr 06, 2017 at 04:38:24PM
On Thu, Apr 06, 2017 at 05:21:56PM +0100, Lorenzo Pieralisi wrote:
> Ok, so:
>
> (1) I can do asm-generic/ioremap-nopost.h, which I assume you want to
> contain something like
>
> static inline void __iomem *ioremap_nopost(phys_addr_t offset, size_t size)
> {
> return
On Thu, Apr 06, 2017 at 05:21:56PM +0100, Lorenzo Pieralisi wrote:
> Ok, so:
>
> (1) I can do asm-generic/ioremap-nopost.h, which I assume you want to
> contain something like
>
> static inline void __iomem *ioremap_nopost(phys_addr_t offset, size_t size)
> {
> return
On Thu, Apr 06, 2017 at 08:16:19AM -0700, Linus Torvalds wrote:
> In theory x86 could use monitor/mwait for it too, in practice I think
> it tends to still be too high latency (because it was originally just
> designed for the idle loop). mwait got extended to actually be useful,
> but I'm not
On Thu, Apr 06, 2017 at 08:16:19AM -0700, Linus Torvalds wrote:
> In theory x86 could use monitor/mwait for it too, in practice I think
> it tends to still be too high latency (because it was originally just
> designed for the idle loop). mwait got extended to actually be useful,
> but I'm not
On Wed, Apr 05, 2017 at 12:18:31PM -0700, Stephen Boyd wrote:
> If a page is marked read only we should print out that fact,
> instead of printing out that there was a page fault. Right now we
> get a cryptic error message that something went wrong with an
> unhandled fault, but we don't evaluate
On Wed, Apr 05, 2017 at 12:18:31PM -0700, Stephen Boyd wrote:
> If a page is marked read only we should print out that fact,
> instead of printing out that there was a page fault. Right now we
> get a cryptic error message that something went wrong with an
> unhandled fault, but we don't evaluate
On Thu, Apr 06, 2017 at 08:33:38AM +0300, Sagi Grimberg wrote:
>
> >>Note that the nvme completion queues are still on the host memory, so
> >>this means we have lost the ordering between data and completions as
> >>they go to different pcie targets.
> >
> >Hmm, in this simple up/down case with a
On Thu, Apr 06, 2017 at 08:33:38AM +0300, Sagi Grimberg wrote:
>
> >>Note that the nvme completion queues are still on the host memory, so
> >>this means we have lost the ordering between data and completions as
> >>they go to different pcie targets.
> >
> >Hmm, in this simple up/down case with a
On Thu, Apr 06, 2017 at 07:50:58PM +0530, Laxman Dewangan wrote:
> Use macro DIV_ROUND_CLOSEST_ULL() for 64bit division to closet one
"closest"
Thierry
> instead of implementing the same locally. This increase readability.
>
> Signed-off-by: Laxman Dewangan
> ---
>
On Thu, Apr 06, 2017 at 07:50:58PM +0530, Laxman Dewangan wrote:
> Use macro DIV_ROUND_CLOSEST_ULL() for 64bit division to closet one
"closest"
Thierry
> instead of implementing the same locally. This increase readability.
>
> Signed-off-by: Laxman Dewangan
> ---
> Changes from V1:
> None
>
On Thu, Apr 06, 2017 at 07:50:59PM +0530, Laxman Dewangan wrote:
> The rate of the PWM calculated as follows:
> hz = NSEC_PER_SEC / period_ns;
> rate = (rate + (hz / 2)) / hz;
>
> This has the precision loss in lower PWM rate.
> Changing this to have more precision as:
> hz =
On Thu, Apr 06, 2017 at 07:50:59PM +0530, Laxman Dewangan wrote:
> The rate of the PWM calculated as follows:
> hz = NSEC_PER_SEC / period_ns;
> rate = (rate + (hz / 2)) / hz;
>
> This has the precision loss in lower PWM rate.
> Changing this to have more precision as:
> hz =
Hi Daniel,
On Tue, Apr 04, 2017 at 06:18:08PM +0100, Marc Zyngier wrote:
> Marc Zyngier (18):
> arm64: Allow checking of a CPU-local erratum
> arm64: Add CNTVCT_EL0 trap handler
> arm64: Define Cortex-A73 MIDR
> arm64: cpu_errata: Allow an erratum to be match for all revisions of a
>
Hi Daniel,
On Tue, Apr 04, 2017 at 06:18:08PM +0100, Marc Zyngier wrote:
> Marc Zyngier (18):
> arm64: Allow checking of a CPU-local erratum
> arm64: Add CNTVCT_EL0 trap handler
> arm64: Define Cortex-A73 MIDR
> arm64: cpu_errata: Allow an erratum to be match for all revisions of a
>
On Sat, Mar 25, 2017 at 05:57:55PM +0530, Arushi Singhal wrote:
> This patch removes typedefs from struct and renames it from "typedef struct
> field_t" to "struct field" as per kernel coding standards."
>
> Signed-off-by: Arushi Singhal
> ---
>
On Sat, Mar 25, 2017 at 05:57:55PM +0530, Arushi Singhal wrote:
> This patch removes typedefs from struct and renames it from "typedef struct
> field_t" to "struct field" as per kernel coding standards."
>
> Signed-off-by: Arushi Singhal
> ---
> net/netfilter/nf_conntrack_h323_asn1.c | 68
>
On Thu, Apr 06, 2017 at 06:21:55PM +0200, Michal Hocko wrote:
> On Thu 06-04-17 10:46:53, Reza Arbab wrote:
> > On Thu, Apr 06, 2017 at 05:41:28PM +0200, Michal Hocko wrote:
> > >On Thu 06-04-17 10:24:49, Reza Arbab wrote:
> > >>On Thu, Apr 06, 2017 at 03:08:46PM +0200, Michal Hocko wrote:
> >
On Thu, Apr 06, 2017 at 06:21:55PM +0200, Michal Hocko wrote:
> On Thu 06-04-17 10:46:53, Reza Arbab wrote:
> > On Thu, Apr 06, 2017 at 05:41:28PM +0200, Michal Hocko wrote:
> > >On Thu 06-04-17 10:24:49, Reza Arbab wrote:
> > >>On Thu, Apr 06, 2017 at 03:08:46PM +0200, Michal Hocko wrote:
> >
On Thu, Apr 06, 2017 at 07:50:59PM +0530, Laxman Dewangan wrote:
> The rate of the PWM calculated as follows:
> hz = NSEC_PER_SEC / period_ns;
> rate = (rate + (hz / 2)) / hz;
>
> This has the precision loss in lower PWM rate.
> Changing this to have more precision as:
> hz =
On Thu, Apr 06, 2017 at 07:50:59PM +0530, Laxman Dewangan wrote:
> The rate of the PWM calculated as follows:
> hz = NSEC_PER_SEC / period_ns;
> rate = (rate + (hz / 2)) / hz;
>
> This has the precision loss in lower PWM rate.
> Changing this to have more precision as:
> hz =
On 06/04/17 18:06, Daniel Kiper wrote:
> Hi Julien,
>
> On Thu, Apr 06, 2017 at 04:39:13PM +0100, Julien Grall wrote:
>> Hi Daniel,
>>
>> On 06/04/17 16:20, Daniel Kiper wrote:
>>> On Thu, Apr 06, 2017 at 04:38:24PM +0200, Juergen Gross wrote:
On 06/04/17 16:27, Daniel Kiper wrote:
> On
On 06/04/17 18:06, Daniel Kiper wrote:
> Hi Julien,
>
> On Thu, Apr 06, 2017 at 04:39:13PM +0100, Julien Grall wrote:
>> Hi Daniel,
>>
>> On 06/04/17 16:20, Daniel Kiper wrote:
>>> On Thu, Apr 06, 2017 at 04:38:24PM +0200, Juergen Gross wrote:
On 06/04/17 16:27, Daniel Kiper wrote:
> On
On Thu 06-04-17 10:46:53, Reza Arbab wrote:
> On Thu, Apr 06, 2017 at 05:41:28PM +0200, Michal Hocko wrote:
> >On Thu 06-04-17 10:24:49, Reza Arbab wrote:
> >>On Thu, Apr 06, 2017 at 03:08:46PM +0200, Michal Hocko wrote:
> >>>OK, so after recent change mostly driven by testing from Reza Arbab
>
On Thu 06-04-17 10:46:53, Reza Arbab wrote:
> On Thu, Apr 06, 2017 at 05:41:28PM +0200, Michal Hocko wrote:
> >On Thu 06-04-17 10:24:49, Reza Arbab wrote:
> >>On Thu, Apr 06, 2017 at 03:08:46PM +0200, Michal Hocko wrote:
> >>>OK, so after recent change mostly driven by testing from Reza Arbab
>
On Thu, Apr 06, 2017 at 02:07:27PM +0100, Russell King - ARM Linux wrote:
> On Thu, Apr 06, 2017 at 01:59:07PM +0200, Luis R. Rodriguez wrote:
> > On Thu, Apr 06, 2017 at 12:38:45PM +0100, Lorenzo Pieralisi wrote:
> > > Ok but where ? linux/io.h or asm-generic/io.h ? As I replied to Russell,
> > >
On Thu, Apr 06, 2017 at 02:07:27PM +0100, Russell King - ARM Linux wrote:
> On Thu, Apr 06, 2017 at 01:59:07PM +0200, Luis R. Rodriguez wrote:
> > On Thu, Apr 06, 2017 at 12:38:45PM +0100, Lorenzo Pieralisi wrote:
> > > Ok but where ? linux/io.h or asm-generic/io.h ? As I replied to Russell,
> > >
This patch documents the devicetree binding in use for ARM SPE.
Cc: Mark Rutland
Cc: Rob Herring
Signed-off-by: Will Deacon
---
Documentation/devicetree/bindings/arm/spe-pmu.txt | 20
1 file changed, 20
This patch documents the devicetree binding in use for ARM SPE.
Cc: Mark Rutland
Cc: Rob Herring
Signed-off-by: Will Deacon
---
Documentation/devicetree/bindings/arm/spe-pmu.txt | 20
1 file changed, 20 insertions(+)
create mode 100644
Perf PMU drivers using AUX buffers cannot be built as modules unless
the AUX helpers are exported.
This patch exports perf_aux_output_{begin,end,skip} and perf_get_aux to
modules.
Cc: Peter Zijlstra
Signed-off-by: Will Deacon
---
Perf PMU drivers using AUX buffers cannot be built as modules unless
the AUX helpers are exported.
This patch exports perf_aux_output_{begin,end,skip} and perf_get_aux to
modules.
Cc: Peter Zijlstra
Signed-off-by: Will Deacon
---
kernel/events/ring_buffer.c | 4
1 file changed, 4
In preparation for adding more flags to perf AUX records, introduce a
separate API for setting the flags for a session, rather than appending
more bool arguments to perf_aux_output_end. This allows to set each
flag at the time a corresponding condition is detected, instead of
tracking it in each
The ARMv8.2 architecture introduces the optional Statistical Profiling
Extension (SPE).
SPE can be used to profile a population of operations in the CPU pipeline
after instruction decode. These are either architected instructions (i.e.
a dynamic instruction trace) or CPU-specific uops and the
In preparation for adding more flags to perf AUX records, introduce a
separate API for setting the flags for a session, rather than appending
more bool arguments to perf_aux_output_end. This allows to set each
flag at the time a corresponding condition is detected, instead of
tracking it in each
The ARMv8.2 architecture introduces the optional Statistical Profiling
Extension (SPE).
SPE can be used to profile a population of operations in the CPU pipeline
after instruction decode. These are either architected instructions (i.e.
a dynamic instruction trace) or CPU-specific uops and the
On Wed, Feb 15, 2017 at 10:45:31PM +0800, Yang Ling wrote:
> Add support for the PWM controller present in Loongson1 family of SoCs.
>
> Signed-off-by: Yang Ling
>
> ---
> V2:
> Remove ls1x_pwm_channel.
> Remove period_ns/duty_ns check.
> Add return values check.
> ---
On Wed, Feb 15, 2017 at 10:45:31PM +0800, Yang Ling wrote:
> Add support for the PWM controller present in Loongson1 family of SoCs.
>
> Signed-off-by: Yang Ling
>
> ---
> V2:
> Remove ls1x_pwm_channel.
> Remove period_ns/duty_ns check.
> Add return values check.
> ---
>
The ARM SPE architecture permits an implementation to ignore a sample
if the sample is due to be taken whilst another sample is already being
produced. In this case, it is desirable to report the collision to
userspace, as they may want to lower the sample period.
This patch adds a
On sama5d2, VDD core may be cut while suspending to RAM. This means the
AIC5 registers content is lost. Restore it at resume time.
Signed-off-by: Alexandre Belloni
---
drivers/irqchip/irq-atmel-aic5.c | 17 +++--
1 file changed, 15
Any modular driver using cluster-affine PPIs needs to be able to call
irq_get_percpu_devid_partition so that it can enable the IRQ on the
correct subset of CPUs.
This patch exports the symbol so that it can be called from within a
module.
Acked-by: Marc Zyngier
Acked-by:
The ARM SPE architecture permits an implementation to ignore a sample
if the sample is due to be taken whilst another sample is already being
produced. In this case, it is desirable to report the collision to
userspace, as they may want to lower the sample period.
This patch adds a
On sama5d2, VDD core may be cut while suspending to RAM. This means the
AIC5 registers content is lost. Restore it at resume time.
Signed-off-by: Alexandre Belloni
---
drivers/irqchip/irq-atmel-aic5.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git
Any modular driver using cluster-affine PPIs needs to be able to call
irq_get_percpu_devid_partition so that it can enable the IRQ on the
correct subset of CPUs.
This patch exports the symbol so that it can be called from within a
module.
Acked-by: Marc Zyngier
Acked-by: Thomas Gleixner
Hi all,
This is the fourth posting of the patches previously posted here:
rfcv1:
http://lists.infradead.org/pipermail/linux-arm-kernel/2017-January/476450.html
rfcv2:
http://lists.infradead.org/pipermail/linux-arm-kernel/2017-January/479387.html
v1:
Hi all,
This is the fourth posting of the patches previously posted here:
rfcv1:
http://lists.infradead.org/pipermail/linux-arm-kernel/2017-January/476450.html
rfcv2:
http://lists.infradead.org/pipermail/linux-arm-kernel/2017-January/479387.html
v1:
Hallo,
Mein Name ist Brinda Khaled, ich werde gerne mehr über dich wissen, ich
möchte nur meine Ansicht mit dir teilen, wenn es dir nichts ausmacht. Ich
werde mehr erzählen, wenn ich von dir antworte. Danke und ich warte auf
deine Antwort.
Brinda
Hallo,
Mein Name ist Brinda Khaled, ich werde gerne mehr über dich wissen, ich
möchte nur meine Ansicht mit dir teilen, wenn es dir nichts ausmacht. Ich
werde mehr erzählen, wenn ich von dir antworte. Danke und ich warte auf
deine Antwort.
Brinda
STM32 DAC has built-in noise or triangle waveform generator.
- "wavetype" extended attribute selects noise or triangle.
- "amplitude" extended attribute selects amplitude for waveform generator
A DC offset can be added to waveform generator output. This can be done
using out_voltage[1/2]_offset
STM32 DAC has built-in noise or triangle waveform generator.
- "wavetype" extended attribute selects noise or triangle.
- "amplitude" extended attribute selects amplitude for waveform generator
A DC offset can be added to waveform generator output. This can be done
using out_voltage[1/2]_offset
Add 'set_trigger' callback to iio info structure. This allows device
to be notified when a trigger (or no trigger) has been assigned. This
maybe useful for instance in non buffered mode (e.g. event triggered).
This is called, after trigger and device side validate callbacks have
been called.
Add 'set_trigger' callback to iio info structure. This allows device
to be notified when a trigger (or no trigger) has been assigned. This
maybe useful for instance in non buffered mode (e.g. event triggered).
This is called, after trigger and device side validate callbacks have
been called.
This patchset adds support for the STM32H7 DAC controller
It's a 12-bit, voltage output digital-to-analog converter. It has two
output channels, each with its own converter, trigger sources and
waveform generator.
Each channel can be used independently, so common resources are managed
in
This patchset adds support for the STM32H7 DAC controller
It's a 12-bit, voltage output digital-to-analog converter. It has two
output channels, each with its own converter, trigger sources and
waveform generator.
Each channel can be used independently, so common resources are managed
in
STM32 DAC supports triggers to synchronize conversions. When trigger
occurs, data is transferred from DHR (data holding register) to DOR
(data output register) so output voltage is updated.
Both hardware and software triggers are supported.
Signed-off-by: Fabrice Gasnier
STM32 DAC supports triggers to synchronize conversions. When trigger
occurs, data is transferred from DHR (data holding register) to DOR
(data output register) so output voltage is updated.
Both hardware and software triggers are supported.
Signed-off-by: Fabrice Gasnier
---
Changes in v2:
- Fix
Document STMicroelectronics STM32 DAC (digital-to-analog converter).
Signed-off-by: Fabrice Gasnier
---
Changes in v2:
- use 'reg' instead of 'st,dac-channel' property
- remove alignment from description
---
.../devicetree/bindings/iio/dac/st,stm32-dac.txt | 61
Document STMicroelectronics STM32 DAC (digital-to-analog converter).
Signed-off-by: Fabrice Gasnier
---
Changes in v2:
- use 'reg' instead of 'st,dac-channel' property
- remove alignment from description
---
.../devicetree/bindings/iio/dac/st,stm32-dac.txt | 61 ++
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