Alexey Budankov writes:
>> You probably also want to explain this change, for example change the
>> @group_list description, saying that something else links into it now.
>>
>
> The whole patch as a single commit, attached to patch v5 4/4, may provide
> the complete view of suggested changes.
N
Hi,
On 18.07.2017 18:08, Alexander Shishkin wrote:
> Alexey Budankov writes:
>
>> Ok. I see. So what are the next steps needs to be taken towards the upstream
>> of this work?
>> What do I need to do more to have this stuff included into the kernel?
>> Could you please clarify this?
>
> Well,
Seunghun,
On Tue, 18 Jul 2017, Seunghun Han wrote:
first of all thanks for the patch and the analysis.
> I'm Seunghun Han, and I work for National Security Research Institute of
> South Korea.
While I appreciate your detailed description of the problem, please try to
follow the rules for change
On 7/18/2017 8:20 AM, Paul E. McKenney wrote:
3.2) how to determine if the idle is short or long. My current proposal is to
use a tunable value via /sys, while Peter prefers an auto-adjust mechanism. I
didn't get the details of an auto-adjust mechanism yet
the most obvious way to do this (for
On 18.07.2017 18:23, Alexander Shishkin wrote:
> Alexey Budankov writes:
>
>>> You probably also want to explain this change, for example change the
>>> @group_list description, saying that something else links into it now.
>>>
>>
>> The whole patch as a single commit, attached to patch v5 4/4, m
On 07/18/2017 07:31 AM, Alexey Brodkin wrote:
Current implementation relies on L1 line length which might easily
be smaller than L2 line (which is usually the case BTW).
Imagine this typical case: L2 line is 128 bytes while L1 line is
64-bytes. Now we want to allocate small buffer and later use
On Tue, 2017-07-18 at 08:39 -0600, Jeffrey Hugo wrote:
> On 7/17/2017 3:59 PM, Toshi Kani wrote:
> > The ghes_edac driver was introduced in 2013 [1], but it has not
> > been enabled by any distro yet.
>
> Ubuntu is expected to enable this soon.
Interesting. I was told from other distro that t
On Tue, Jul 18, 2017 at 11:26:51AM +0800, Bob Liu wrote:
> On 2017/7/14 5:15, Jérôme Glisse wrote:
> > Sorry i made horrible mistake on names in v4, i completly miss-
> > understood the suggestion. So here i repost with proper naming.
> > This is the only change since v3. Again sorry about the nois
On Tue, Jul 18, 2017 at 02:32:11PM +0300, Alexey Khoroshilov wrote:
> clk_disable_unprepare(info->clk) is missed in of_platform_serial_probe(),
> while irq_dispose_mapping(port->irq) is missed in of_platform_serial_setup().
>
> Found by Linux Driver Verification project (linuxtesting.org).
>
> Si
Commit-ID: afabde6986911394c95c596f96d2ac833eef04cc
Gitweb: http://git.kernel.org/tip/afabde6986911394c95c596f96d2ac833eef04cc
Author: Seunghun Han
AuthorDate: Tue, 18 Jul 2017 18:20:44 +0900
Committer: Thomas Gleixner
CommitDate: Tue, 18 Jul 2017 17:39:54 +0200
x86/ioapic: Pass the co
Em Tue, Jul 18, 2017 at 07:19:45PM +1000, Michael Ellerman escreveu:
> Arnaldo Carvalho de Melo writes:
>
> > Em Mon, Jul 17, 2017 at 04:02:22PM +0530, Ravi Bangoria escreveu:
> >> Commit 801bc8193463 ("perf probe: Allow placing uprobes in
> >> alternate namespaces.") is causing a build failure o
On Tue, 2017-07-18 at 07:34 +0200, Borislav Petkov wrote:
> On Mon, Jul 17, 2017 at 03:59:10PM -0600, Toshi Kani wrote:
> > ACPI OEM ID / OEM Table ID / Revision can be used to identify
> > platform type based on ACPI firmware. acpi_blacklisted(),
> > intel_pstate_platform_pwr_mgmt_exists() and so
Em Wed, Jul 19, 2017 at 04:31:32AM +0800, Jin Yao escreveu:
> Currently perf has supported a mode to query inline stack. It works
> well for finding the user space inline function but it doesn't work
> for finding kernel inline function due to some unnecessary checking.
>
> This patch removes thes
Em Tue, Jul 18, 2017 at 07:31:37PM +1000, Michael Ellerman escreveu:
> Jin Yao writes:
>
> > It is often useful to know the branch types while analyzing branch
> > data. For example, a call is very different from a conditional branch.
> >
> > Currently we have to look it up in binary while the bi
On Fri, 2017-06-30 at 20:09 +0300, Andy Shevchenko wrote:
> The series brings a bit of order to arch/x86/include/asm/io.h by re-
> using
> definitions in the generic header.
>
> The series has been tested on Intel Broxton hardware in 32- and 64-bit
> modes.
Any comments?
Shall I resend this?
>
On Tue, Jul 18, 2017 at 6:45 PM, Johan Hovold wrote:
> On Tue, Jul 18, 2017 at 02:32:11PM +0300, Alexey Khoroshilov wrote:
>> clk_disable_unprepare(info->clk) is missed in of_platform_serial_probe(),
>> while irq_dispose_mapping(port->irq) is missed in of_platform_serial_setup().
>> +err_register
On Mon, Jul 10, 2017 at 01:53:43PM -0700, John Stultz wrote:
> From: Antonio Borneo
>
> Commit 36387a2b1f62b5c087c5fe6f0f7b23b94f722ad7 ("k3dma: Fix
> memory handling in preparation for cyclic mode") broke the
> logic around ds_run/ds_done in case of non-cyclic DMA.
>
> This went unnoticed as th
On Mon, Jul 17, 2017 at 09:39:00PM +0530, Arvind Yadav wrote:
> pci_device_id are not supposed to change at runtime. All functions
> working with pci_device_id provided by work with
> const pci_device_id. So mark the non-const structs as const.
>
> File size before:
>text data bs
On Tue, 18 Jul 2017 13:48:04 +0200,
Arnd Bergmann wrote:
>
> The compiler sees that the format string might overflow for the longname:
>
> sound/isa/als100.c: In function 'snd_als100_pnp_detect':
> sound/isa/als100.c:225:27: error: ', dma ' directive writing 6 bytes into a
> region of size betwe
On 07/17/2017 02:10 PM, David Miller wrote:
> From: Andrew Lunn
> Date: Mon, 17 Jul 2017 23:04:05 +0200
>
>> On Mon, Jul 17, 2017 at 01:45:49PM -0700, David Miller wrote:
>>> From: Vivien Didelot
>>> Date: Mon, 17 Jul 2017 15:32:52 -0400
>>>
Hi Andrew,
Andrew Lunn writes:
>>
On Tue, 2017-07-18 at 17:49 +0800, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> Signed-off-by: Chenglin Xu
> Signed-off-by: Sean Wang
> Acked-by: Rob Herring
> ---
> Documentation/devicetree/bindings/soc/mediatek/pwrap.txt | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/D
Seeing there is no dedicated hardware for this, we simply add
these as entries in the shared memory window. Thus, we could support
any number of them but 128 seems like enough, for now.
Signed-off-by: Logan Gunthorpe
Reviewed-by: Stephen Bates
Reviewed-by: Kurt Schwemmer
---
drivers/ntb/hw/msc
We export the class pointer symbol and add an extern define in the
Switchtec header file.
Signed-off-by: Logan Gunthorpe
Reviewed-by: Stephen Bates
Reviewed-by: Kurt Schwemmer
Acked-by: Bjorn Helgaas
---
drivers/pci/switch/switchtec.c | 4 +++-
include/linux/switchtec.h | 2 ++
2 files c
On Tue, Jul 18, 2017 at 7:36 AM, Leonard Crestez
wrote:
> On Wed, 2017-06-14 at 18:12 -0700, Thomas Garnier wrote:
>> Ensure the address limit is a user-mode segment before returning to
>> user-mode. Otherwise a process can corrupt kernel-mode memory and
>> elevate privileges [1].
>>
>> The set_fs
After the link tests, there is a race on one side of the test for
the link coming up. It's possible, in some cases, for the test script
to write to the 'peer_trans' files before the link has come up.
To fix this, we simply use the link event file to ensure both sides
see the link as up before cont
The switchtec_ntb driver has a couple requirements on the switchec's
hardware configuration so we add these notes to the documentation.
Signed-off-by: Logan Gunthorpe
Reviewed-by: Stephen Bates
Reviewed-by: Kurt Schwemmer
---
Documentation/switchtec.txt | 12
1 file changed, 12 in
Seeing the Switchtec NTB hardware shares the same endpoint as the
management endpoint we utilize the class_interface API to register
an NTB driver for every Switchtec device in the system that has the
NTB class code.
Signed-off-by: Logan Gunthorpe
Reviewed-by: Stephen Bates
Reviewed-by: Kurt Sch
The Switchtec hardware has two types of memory windows: LUTs and Direct.
The first area in each BAR is for LUT windows and the remaining area is
for the direct region. The total number of LUT entries is set by a
configuration setting in hardware and they all must be the same
size. (This is fixed by
switchtec_ntb checks for a link by looking at the shared memory
window. If the magic number is correct and the otherside indicates
their link is enabled then we take the link to be up.
Whenever we change our local link status we send a msg to the
otherside to check whether it's up and change their
Pretty straightforward implementation of doorbell registers.
The shift and mask were setup in an earlier patch and this just hooks
up the appropriate portion of the IDB register as the local doorbells
and the opposite portion of ODB as the peer doorbells. The DB mask is
protected by a spinlock to a
Set up some hardware registers and creates interrupt service routines
for the doorbells and messages.
There are 64 doorbells in the switch that are shared between all
partitions. The upper 4 doorbells are also shared with the messages
and are there for not used. Thus, this provides 28 doorbells fo
Add a skeleton NTB driver which will be filled out in subsequent patches.
Signed-off-by: Logan Gunthorpe
Reviewed-by: Stephen Bates
Reviewed-by: Kurt Schwemmer
---
drivers/ntb/hw/mscc/switchtec_ntb.c | 148 +++-
include/linux/ntb.h | 3 +
2 fil
In order for the Switchtec NTB code to handle link change events we
create a notifier callback in the switchtec code which gets called
whenever an appropriate event interrupt occurs.
In order to preserve userspace's ability to follow these events,
we compare the event count with a stored copy from
On 07/10/2017 04:10 AM, Juergen Gross wrote:
> When setting up the Xenstore watch for the memory target size the new
> watch will fire at once. Don't try to reach the configured target size
> by onlining new memory in this case, as the current memory size will
> be smaller in almost all cases due t
Changes since v1:
- Rebased onto latest ntb-next branch (with v4.13-rc1)
- Reworked ntb_mw_count() function so that it can be called all the
time (per discussion with Allen)
- Various spelling and formatting cleanups from Bjorn
- Added request_module() call such that the NTB module is automatica
Create the switchtec.h header in include/linux with hardware defines
and the switchtec_dev structure. Both moved directly from switchtec.c.
This is a prep patch for creating an NTB driver for Switchtec.
Signed-off-by: Logan Gunthorpe
Reviewed-by: Stephen Bates
Reviewed-by: Kurt Schwemmer
Acked-
With Switchtec hardware it's impossible to get the alignment parameters
for a peer's memory window until the peer's driver has configured it's
windows. Strictly speaking, the link doesn't have to be up for this,
but the link being up is the only way the client can tell that
the otherside has been c
There are two additional regions: ctrl and dbmsg. The first is
for generic NTB control and memory windows. The second is for doorbells
and message registers. This patch also adds a number of related
constants for using these registers.
Signed-off-by: Logan Gunthorpe
Reviewed-by: Stephen Bates
Re
Hi Taeung,
On Fri, Jul 14, 2017 at 02:45:44AM +0900, Taeung Song wrote:
> Hello,
>
> Currently the --show-total-period option of perf-annotate
> is different from perf-report's.
>
> It has two problem like below:
> (Reported by Namhyung Kim and Milian Wolff)
>
> 1) Wrong column i.e. 'Percent'
Add the code to initialize the memory windows in the hardware.
This includes setting up the requester ID table, and figuring out
which bar corresponds to which memory window. (Seeing the switch
can be configured with any number of bars.)
Also, seeing the device doesn't have hardware for scratchpad
Adds a comment and a check to ntb_mw_get_align() so that it always fails
if the function is called before the link is up.
Also adds a comment to ntb_mw_count() to note that it may return 0 if
it is called before the link is up.
This is to prevent accidental mis-use in clients that are testing
on
Pages are added into lru lists via per-cpu page vectors in order
to combine these insertions and reduce lru lock contention.
These pending pages cannot be isolated and moved into another lru.
This breaks in some cases page activation and makes mlock-munlock
much more complicated.
Also this breaks
On 07/18/2017 10:57 AM, Vivek Goyal wrote:
On Tue, Jul 18, 2017 at 09:21:22AM -0400, Stefan Berger wrote:
On 07/18/2017 08:30 AM, Vivek Goyal wrote:
On Tue, Jul 18, 2017 at 08:05:18AM -0400, Stefan Berger wrote:
On 07/18/2017 07:48 AM, Vivek Goyal wrote:
On Mon, Jul 17, 2017 at 04:50:22PM -04
On 18/07/17 18:08, Boris Ostrovsky wrote:
> On 07/10/2017 04:10 AM, Juergen Gross wrote:
>> When setting up the Xenstore watch for the memory target size the new
>> watch will fire at once. Don't try to reach the configured target size
>> by onlining new memory in this case, as the current memory s
On Thu, Jun 29, 2017 at 10:30:57PM -0400, Sinan Kaya wrote:
> @@ -410,7 +410,40 @@ static int hidma_alloc_chan_resources(struct dma_chan
> *dmach)
> return NULL;
>
> hidma_ll_set_transfer_params(mdma->lldev, mdesc->tre_ch,
> - src, dest, len,
On Mon, 2017-07-17 at 16:12 +0100, Suzuki K Poulose wrote:
> On 16/07/17 14:56, Ben Hutchings wrote:
> > 3.16.46-rc1 review patch. If anyone has any objections, please let me know.
> >
> > --
> >
> > From: Suzuki K Poulose
> >
[...]
> There is a follow up patch for this one to mak
On Fri, Jul 14, 2017 at 02:46:16AM +0900, Taeung Song wrote:
> Cc: Namhyung Kim
> Cc: Milian Wolff
> Cc: Jiri Olsa
> Signed-off-by: Taeung Song
Hmm.. IIUC there're 3 modes of annotation view: percent, period and
sample, right? The existing 't' hotkey seems to toggle between
percent and period
On Tue, Jul 18, 2017 at 12:48 AM, Elena Reshetova
wrote:
> atomic_as_refcounter.cocci script allows detecting
> cases when refcount_t type and API should be used
> instead of atomic_t.
>
> Signed-off-by: Elena Reshetova
> ---
> scripts/coccinelle/api/atomic_as_refcounter.cocci | 102
> +
From: Chao Yu
This patch add new flag F2FS_EXTRA_ATTR storing in inode.i_inline
to indicate that on-disk structure of current inode is extended.
In order to extend, we changed the inode structure a bit:
Original one:
struct f2fs_inode {
...
struct f2fs_extent i_ext;
__l
From: Chao Yu
This patch tries to make below macros calculating max inline size,
inline dentry field size considerring reserving size-changeable
space:
- MAX_INLINE_DATA
- NR_INLINE_DENTRY
- INLINE_DENTRY_BITMAP_SIZE
- INLINE_RESERVED_SIZE
Then, when inline_{data,dentry} options is enabled, it a
From: Chao Yu
This patch adds to support plain project quota.
Signed-off-by: Chao Yu
---
v2: rebase codes.
Documentation/filesystems/f2fs.txt | 1 +
fs/f2fs/f2fs.h | 29 +
fs/f2fs/file.c | 13 -
fs/f2fs/inode.c
On Thu, Jun 29, 2017 at 10:30:58PM -0400, Sinan Kaya wrote:
> Introducing memset test into dmatest. This change allows us to test
> memset capable HW using the dmatest test procedure. The new dmatest
> value for memset is 2 and it is not the default value.
>
> Memset support patch shares the same
On 7/18/2017 9:36 AM, Kani, Toshimitsu wrote:
On Tue, 2017-07-18 at 08:39 -0600, Jeffrey Hugo wrote:
On 7/17/2017 3:59 PM, Toshi Kani wrote:
The ghes_edac driver was introduced in 2013 [1], but it has not
been enabled by any distro yet.
Ubuntu is expected to enable this soon.
Interesting.
On Fri, Jul 14, 2017 at 02:46:20AM +0900, Taeung Song wrote:
> Currently the percentages of perf-annotate are calculated
> with number of samples, not the sample period.
> So fix it to correspond with perf-report using the sample period
> for the calculation.
Not sure someone still wants the old b
From: Chao Yu
This patch introduce a new option 'project_quota' for enabling project
quota functionality during mkfs.
Signed-off-by: Chao Yu
---
v2:
- rebases codes
- use '-O project_quota' option instead of '-p' for enabling project quota.
fsck/mount.c| 4
include/f2fs_fs.h
From: Chao Yu
This patch adds an option 'extra_attr' in mkfs for enabling v2 f2fs
inode format in kernel codes.
Also this patch makes fsck to support recognize v2 inode format,
below is v2 format description:
Original one:
struct f2fs_inode {
...
struct f2fs_extent i_ext;
[Resend due to bad mail format, sorry about the noise if you got two]
On Tue, 2017-07-18 at 17:49 +0800, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> fixup those warnings such as lines over 80 words and parenthesis
> alignment which would be complained by checkpatch.pl.
>
> Signed-off-b
Hi Vinod,
On 7/18/2017 12:19 PM, Vinod Koul wrote:
> On Thu, Jun 29, 2017 at 10:30:57PM -0400, Sinan Kaya wrote:
>
>> @@ -410,7 +410,40 @@ static int hidma_alloc_chan_resources(struct dma_chan
>> *dmach)
>> return NULL;
>>
>> hidma_ll_set_transfer_params(mdma->lldev, mdesc->t
The iHome keypad also requires the same tweak we are doing for other
Ortek devices.
Reported-by: Mairin Duffy
Signed-off-by: Benjamin Tissoires
---
drivers/hid/hid-core.c | 1 +
drivers/hid/hid-ids.h | 1 +
drivers/hid/hid-ortek.c | 6 --
3 files changed, 6 insertions(+), 2 deletions(-)
On 06/22/2017 11:32 AM, YT Shen wrote:
This adds basic chip support for Mediatek 2712
Signed-off-by: YT Shen
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 32 ++
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 172 +++
On Wed, 2017-07-19 at 00:26 +0800, Yingjoe Chen wrote:
> [Resend due to bad mail format, sorry about the noise if you got two]
>
>
> On Tue, 2017-07-18 at 17:49 +0800, sean.w...@mediatek.com wrote:
> > From: Sean Wang
> >
> > fixup those warnings such as lines over 80 words and parenthesis
> >
On 07/18/2017 12:12 PM, Juergen Gross wrote:
> On 18/07/17 18:08, Boris Ostrovsky wrote:
>> On 07/10/2017 04:10 AM, Juergen Gross wrote:
>>> When setting up the Xenstore watch for the memory target size the new
>>> watch will fire at once. Don't try to reach the configured target size
>>> by onlini
On 07/06/2017 08:43 AM, Zhi Mao wrote:
On Thu, 2017-07-06 at 14:16 +0800, Zhi Mao wrote:
On Wed, 2017-07-05 at 13:09 +0200, Matthias Brugger wrote:
On 06/30/2017 08:05 AM, Zhi Mao wrote:
In original code, the pwm output frequency is not correct
when set bit<3>=1 to PWMCON register.
Signed-
On Tue, Jul 18, 2017 at 08:29:40AM -0700, Arjan van de Ven wrote:
>
> the most obvious way to do this (for me, maybe I'm naive) is to add another
> C state, lets call it "C1-lite" with its own thresholds and power levels etc,
> and just let that be picked naturally based on the heuristics.
> (if w
On Tue 18 Jul 01:45 PDT 2017, Oleksij Rempel wrote:
> Hallo Bjorn,
>
> On 11.07.2017 00:14, Bjorn Andersson wrote:
> > On Mon 10 Jul 07:42 PDT 2017, Oleksij Rempel wrote:
> >
> > > Signed-off-by: Oleksij Rempel
> > > ---
> > > .../devicetree/bindings/remoteproc/imx-rproc.txt | 44
> > >
On 7/18/2017 9:36 AM, Peter Zijlstra wrote:
On Tue, Jul 18, 2017 at 08:29:40AM -0700, Arjan van de Ven wrote:
the most obvious way to do this (for me, maybe I'm naive) is to add another
C state, lets call it "C1-lite" with its own thresholds and power levels etc,
and just let that be picked nat
On Tue, Jul 18, 2017 at 03:48:54PM +, Kani, Toshimitsu wrote:
> This patch defines 'struct acpi_oemlist' in "include/linux/acpi.h" as a
I see that.
> common structure, and replaces this specific 'struct acpi_blacklist'.
And what makes acpi_oemlist "common" and acpi_blacklist "specific"?
So
On Tue, 2017-07-18 at 10:24 -0600, Jeffrey Hugo wrote:
> On 7/18/2017 9:36 AM, Kani, Toshimitsu wrote:
> > On Tue, 2017-07-18 at 08:39 -0600, Jeffrey Hugo wrote:
> > > On 7/17/2017 3:59 PM, Toshi Kani wrote:
> > > > The ghes_edac driver was introduced in 2013 [1], but it has not
> > > > been enable
On Tue, Jul 18, 2017 at 12:26:14PM -0400, Sinan Kaya wrote:
> Hi Vinod,
>
> On 7/18/2017 12:19 PM, Vinod Koul wrote:
> > On Thu, Jun 29, 2017 at 10:30:57PM -0400, Sinan Kaya wrote:
> >
> >> @@ -410,7 +410,40 @@ static int hidma_alloc_chan_resources(struct dma_chan
> >> *dmach)
> >>re
On Tue 18 Jul 02:58 PDT 2017, Varadarajan Narayanan wrote:
> On Mon, Jul 17, 2017 at 03:07:18PM -0700, Bjorn Andersson wrote:
> > On Mon 17 Jul 05:04 PDT 2017, Varadarajan Narayanan wrote:
[..]
> >
> > Can you confirm that this is actually version 4 of this block? Or are we
> > just incrementing a
On Tue, Jul 18, 2017 at 02:56:47PM +0800, Li, Aubrey wrote:
> 3) for tick nohz idle, we want to skip if the coming idle is short. If we can
> skip the tick nohz idle, we then skip all the items depending on it. But,
> there
> are two hard points:
>
> 3.1) how to compute the period of the coming
On 07/17/2017 06:39 AM, Geert Uytterhoeven wrote:
> All low-level PM/SMP code using virt_to_phys() should actually use
> __pa_symbol() against kernel symbols. Update the documentation to move
> away from virt_to_phys().
>
> Cfr. commit 6996cbb2372189f7 ("ARM: 8641/1: treewide: Replace uses of
> v
Hi Keerthy,
On 07/18/2017 05:57 AM, Keerthy wrote:
> Use the devm version of gpiochip_add_data and pass on the
> return value. Reset the static variables to 0 before returning.
>
> Signed-off-by: Keerthy
> ---
> drivers/gpio/gpio-davinci.c | 10 --
> 1 file changed, 8 insertions(+), 2 d
> "JT" == Johannes Thumshirn writes:
JT> This is fixed with: commit 68c59fcea1f2c6a54c62aa896cc623c1b5bc9b47
Hmm, well, I just pulled and built mainline, which does appear to
contain that patch (though it wasn't there when I first started
investigating this last week) and the problem is stil
Hi Keerthy,
On 07/18/2017 05:57 AM, Keerthy wrote:
> Currently davinci_gpio_irq_setup return value is ignored. Handle the
> return value appropriately.
>
> Signed-off-by: Keerthy
> ---
> drivers/gpio/gpio-davinci.c | 18 +-
> 1 file changed, 13 insertions(+), 5 deletions(-)
>
>
This patch adds generic io{read|write}64[be]{_lo_hi|_hi_lo} macros if
they are not already defined by the architecture. (As they are provided
by the generic iomap library).
The patch also points io{read|write}64[be] to the variant specified by the
header name.
This is because new drivers are enco
Subsequent patches in this series makes use of the readq and writeq
defines in iomap.h. However, as is, they get missed on the powerpc
platform seeing the include comes before the define. This patch
moves the include down to fix this.
Signed-off-by: Logan Gunthorpe
Cc: Benjamin Herrenschmidt
Cc:
In order to provide non-atomic functions for io{read|write}64 that will
use readq and writeq when appropriate. We define a number of variants
of these functions in the generic iomap that will do non-atomic
operations on pio but atomic operations on mmio.
These functions are only defined if readq a
Now that ioread64 and iowrite64 are available in io-64-nonatomic,
we can remove the hack at the top of ntb_hw_intel.c and replace it
with an include.
Signed-off-by: Logan Gunthorpe
Cc: Jon Mason
Cc: Allen Hubbe
Acked-by: Dave Jiang
---
drivers/ntb/hw/intel/ntb_hw_intel.c | 30 +---
Alexey Budankov writes:
> I see. Do you personally have some more issues that needs to be addressed?
> My intention is that this patch v5 4/4 addresses all your comments raised in
> the previous reviews.
I don't know yet, I haven't started on the actual content of the
patchset, it being hard to
From: Horia Geantă
We can now make use of the io-64-nonatomic-lo-hi header to always
provide 64 bit IO operations. So this patch cleans up the extra
CONFIG_64BIT ifdefs.
To be consistent with CAAM engine HW spec: in case of 64-bit registers,
irrespective of device endianness, the lower address s
On Tue, Jul 18, 2017 at 4:10 AM, Jose Abreu wrote:
> Hi John,
>
>
> On 18-07-2017 05:22, John Stultz wrote:
>> Currently the hikey dsi logic cannot generate accurate byte
>> clocks values for all pixel clock values. Thus if a mode clock
>> is selected that cannot match the calculated byte clock, t
On Tue, Jul 18, 2017 at 7:06 AM, Eric W. Biederman
wrote:
> struct siginfo is a union and the kernel since 2.4 has been hiding a union
> tag in the high 16bits of si_code using the values:
> __SI_KILL
> __SI_TIMER
> __SI_POLL
> __SI_FAULT
> __SI_CHLD
> __SI_RT
> __SI_MESGQ
> __SI_SYS
>
> While thi
This is version four of my patchset to enable drivers to use
io{read|write}64 on all arches.
Changes since v3:
- I noticed powerpc didn't use the appropriate functions seeing
readq/writeq were not defined when iomap.h was included. Thus I've
included a patch to adjust this
- Fixed some mistakes w
On Tue 18 Jul 01:54 PDT 2017, Varadarajan Narayanan wrote:
> On Mon, Jul 17, 2017 at 03:30:47PM -0700, Bjorn Andersson wrote:
[..]
> >
> > This would be the case for any existing dts files, so you're not allowed
> > to treat this as an error.
>
> Since, there are no dts files that presently enable
From: Christoffer Dall
Set the initial exception level of the guest to EL2 if nested
virtualization feature is enabled.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_host.h | 2 +-
arch/arm64/include/uapi/asm/kvm.h | 1 +
arch/arm64/kvm/reset.c
To support the virtual EL2 execution, we need to maintain the EL2
special registers such as SPSR_EL2, ELR_EL2 and SP_EL2 in vcpu context.
Note that SP_EL2 is not accessible in EL2, so we don't need a trap
handler for this register.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_host.
When running in virtual EL2 we use the shadow EL1 systerm register array
for the save/restore process, so that hardware and especially the memory
subsystem behaves as code written for EL2 expects while really running
in EL1.
This works great for EL1 system register accesses that we trap, because
t
From: Christoffer Dall
We were not allowing userspace to set a more privileged mode for the VCPU
than EL1, but now that we support nesting with a virtual EL2 mode, do
allow this!
Signed-off-by: Christoffer Dall
---
arch/arm64/kvm/guest.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/ar
On Mon, Jul 17, 2017 at 10:41:38PM -0700, Tony Lindgren wrote:
> * Paul E. McKenney [170717 05:40]:
> > On Sun, Jul 16, 2017 at 11:08:07PM -0700, Tony Lindgren wrote:
> > > * Alex Shi [170716 16:25]:
> > > > I reused the rcu_irq_enter_irqson() from RCU_NONIDLE to avoid this
> > > > issue.
> > >
Forward traps due to FP/ASIMD register accesses to the virtual EL2 if
virtual CPTR_EL2.TFP is set. Note that if TFP bit is set, then even
accesses to FP/ASIMD register from EL2 as well as NS EL0/1 will trap to
EL2. So, we don't check the VM's exception level.
Signed-off-by: Jintack Lim
---
arch/
On VHE systems, EL0 of the host kernel is considered as a part of 'VHE
host'; The execution of EL0 is affected by system registers set by the
VHE kernel including the hypervisor. To emulate this for a VM, we use
the same set of system registers (i.e. shadow registers) for the virtual
EL2 and EL0 ex
Forward ELR_EL1, SPSR_EL1 and VBAR_EL1 traps to the virtual EL2 if the
virtual HCR_EL2.NV bit is set.
This is for recursive nested virtualization.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_arm.h | 1 +
arch/arm64/kvm/sys_regs.c| 18 ++
2 files changed, 1
Forward traps due to HCR_EL2.NV bit to the virtual EL2 if they are not
coming from the virtual EL2 and the virtual HCR_EL2.NV bit is set.
This is for recursive nested virtualization.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_arm.h| 1 +
arch/arm64/include/asm/kvm_coproc.h |
Forward CPACR_EL1 traps to the virtual EL2 if virtual CPTR_EL2 is
configured to trap CPACR_EL1 accesses from EL1.
This is for recursive nested virtualization.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/kvm/sys_reg
When the virtual E2H bit is set, we can support EL2 register accesses
via EL1 registers from the virtual EL2 by doing trap-and-emulate. A
better alternative, however, is to allow the virtual EL2 to access EL2
register states without trap. This can be easily achieved by not traping
EL1 registers sin
Forward the EL1 virtual memory register traps to the virtual EL2 if they
are not coming from the virtual EL2 and the virtual HCR_EL2.TVM or TRVM
bit is set.
This is for recursive nested virtualization.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c | 24
1 fil
In addition to EL2 register accesses, setting NV bit will also make EL12
register accesses trap to EL2. To emulate this for the virtual EL2,
forword traps due to EL12 register accessses to the virtual EL2 if the
virtual HCR_EL2.NV bit is set.
This is for recursive nested virtualization.
Signed-of
With HCR_EL2.NV bit set, accesses to EL12 registers in the virtual EL2
trap to EL2. Handle those traps just like we do for EL1 registers.
One exception is CNTKCTL_EL12. We don't trap on CNTKCTL_EL1 for non-VHE
virtual EL2 because we don't have to. However, accessing CNTKCTL_EL12
will trap since it
While the EL1 virtual memory control registers can be accessed in the
virtual EL2 with VHE without trap to manuplate the virtual EL2 states,
we can't do that for CPTR_EL2 for an unfortunate reason.
This is because the top bit of CPTR_EL2, which is TCPAC, will be ignored
if it is accessed via CPACR
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