Hi Adam,
On Mon, Jul 23, 2018 at 12:42 PM Adam Borowski wrote:
> On Mon, Jul 23, 2018 at 10:53:29AM +0200, Geert Uytterhoeven wrote:
> > On Sat, Jul 21, 2018 at 11:39 PM Adam Borowski wrote:
> > > Technically, every console can be made to blink by drawing/clearing
> > > affected
> > > character
On Mon, 2018-07-23 at 11:41 +0200, Lucas Stach wrote:
> As this doesn't depend on any other patch in this series, I think it
> would be fine if Philipp takes this patch through the reset tree.
>
> Regards,
> Lucas
>
> Am Freitag, den 20.07.2018, 15:47 +0300 schrieb Leonard Crestez:
> > Right now
Add support for the display clock controller found on SDM845
based devices. This would allow display drivers to probe and
control their clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig | 10 +
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/dispcc-sdm845.c | 687
[v5]
* Initialize pll config before assigining l/alpha values for
pll configure.
* Add module description.
[v4]
* Add comments for the RCGs/CBCRs using the CLK_GET_RATE_NOCACHE flag.
[v3]
* Move frequency table macro to common file,
add the patch along to maintain dependency.
On Wed, Jun 20, 2018 at 10:32:54PM +0530, Srikar Dronamraju wrote:
> Currently resetting the migrate rate limit is under a spinlock.
> The spinlock will only serialize the migrate rate limiting and something
> similar can actually be achieved by a simpler xchg.
You're again not explaining things r
Am Dienstag, den 24.07.2018, 01:46 +0800 schrieb Robin Gong:
> If multi-bds used in one transfer, all bds should be consisten
> memory.To easily follow it, enlarge the dma pool size into 20 bds,
> and it will report error if the number of bds is over than 20. For
> dmatest, the max count for single
Fix sparse warning: Using plain integer as NULL pointer
Signed-off-by: Laurence Rochfort
---
drivers/staging/most/dim2/dim2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/staging/most/dim2/dim2.c b/drivers/staging/most/dim2/dim2.c
index fe90a7c..31fbc1a 100644
---
On Fri 20-07-18 14:34:21, David Hildenbrand wrote:
> The reserved bit once was used to hinder pages from getting swapped. While
> this still works,
Does it? There is no single PageReserved check in the reclaim path. I
have no idea when we stopped checking but it must be lng ago.
> the semanti
Am Sonntag, 8. Juli 2018, 17:19:55 CEST schrieb Christoph Hellwig:
> Hi Masahiro,
>
> what do you think about the series below, which moves the includes
> of all the architecture independ Kconfig files to the top-level
> Kconfig instead of duplicating the includes in all architectures?
>
> Note t
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
On 23/07/18 05:46, Stephen Rothwell wrote:
> Hi all,
>
> Today's linux-next merge of the kvm-arm tree got a conflict in:
>
> arch/arm64/include/asm/cpucaps.h
>
> between commit:
>
> 314d53d29798 ("arm64: Handle mismatched cache type")
>
> from t
On Mon 23-07-18 10:56:13, 禹舟键 wrote:
> Hi Michal
> OK, thanks. Is there any problems for V14?
I do not know of any. Both patches are sitting in the mmotm tree so they
should be merged in a forseeable future as long as nobody finds any
problems.
--
Michal Hocko
SUSE Labs
On Mon, Jul 23, 2018 at 06:34:36PM +0800, shaochun chen wrote:
> I have a question: we will try_module_get in __netlink_dump_start(),
> but why we need to call try_module_get again in nft_netlink_dump_start ??
Because they refer to two different modules. nfnetlink is multiplexing
all netfilter su
The SID controller on H3 is one of it's kind (at least from what we
know).
Add a compatible string for it in the SoC dtsi.
Signed-off-by: Emmanuel Vadot
---
arch/arm/boot/dts/sun8i-h3.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts
The SID controller on H5 look the same as the one present in the A64.
But in case we find some difference one day at a compatible string
of it's own and a fallback to the A64 one.
Signed-off-by: Emmanuel Vadot
---
.../devicetree/bindings/nvmem/allwinner,sunxi-sid.txt| 1 +
arch/arm64/boo
Both H3 and H5 and a SID controller at the same address.
They are know to be different, the H5 one is the same as the A64 so add
a node in the common dtsi and we will override the compatible string in
the SoC dts.
Signed-off-by: Emmanuel Vadot
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 4
1 f
The A64 have a SID controller which consist on EFUSE (starting at 0x200)
and three registers to read/write the efuses.
Signed-off-by: Emmanuel Vadot
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64
On Mon, Jul 23, 2018 at 10:53:29AM +0200, Geert Uytterhoeven wrote:
> On Sat, Jul 21, 2018 at 11:39 PM Adam Borowski wrote:
> > Technically, every console can be made to blink by drawing/clearing affected
> > characters a few times per second, but that'd be quite a waste of coding
> > time and ker
Am Dienstag, 17. Juli 2018, 18:06:06 CEST schrieb Enric Balletbo i Serra:
> Enable the Rockchip sound driver with MAX98357A/RT5514/DA7219 codecs
> needed for the Samsung Chromebook Plus.
>
> Signed-off-by: Enric Balletbo i Serra
applied all 5 for 4.19.
As Olof requested less granularity for def
On Wed, Jun 20, 2018 at 10:32:52PM +0530, Srikar Dronamraju wrote:
> Since task migration under numa balancing can happen in parallel, more
> than one task might choose to move to the same node at the same time.
> This can cause load imbalances at the node level.
>
> The problem is more likely if
On 2018-07-21 05:07, kbuild test robot wrote:
Hi Girish,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on spi/for-next]
[also build test ERROR on v4.18-rc5 next-20180720]
[if your patch is applied to the wrong git tree, please drop us a note
to help improve the syste
On Sat, Jul 21, 2018 at 10:06:23AM +, Marcel Ziswiler wrote:
> On Sat, 2018-07-21 at 10:56 +0100, Mark Brown wrote:
> > > > > - dev_err(&pdev->dev, "no codec-sync GPIO
> > > > > supplied\n");
> > > > > + ret = ac97->sync_gpio;
> And here I assign ret with that return v
On Sat, Jul 21, 2018 at 07:23:31AM -0400, Peter Geis wrote:
> Re-sending due to email address typo.
>
> SW2 and SW4 use a shared table to provide voltage to the cpu core and
> devices on Tegra hardware.
> Added this table to the cpcap regulator driver as the first step to
> supporting this device
Wrap the mei header boilerplate initialization code in
mei_msg_hdr_init function. On the way remove 'completed'
field from mei_cl_cb structure as this information
is already included in the header and is local to particular
fragment.
Signed-off-by: Tomas Winkler
---
drivers/misc/mei/client.c |
The host buffer depth is hardware specific so it's better to
handle it inside the me and txe hw modules. In me the depth
is read from register in txe it's a constant number.
The value is now retrieved via mei_hbuf_depth accessor,
while it replaces mei_hbuf_max_len.
Signed-off-by: Tomas Winkler
--
Cleanup conversions between slots and data.
Define MEI_SLOT_SIZE instead of using 4 or sizeof(u32) across
the source code.
Signed-off-by: Tomas Winkler
---
drivers/misc/mei/client.c | 2 +-
drivers/misc/mei/hw-me.c | 8
drivers/misc/mei/hw-txe.c | 8
drivers/misc/mei/mei_de
> On Jul 22, 2018, at 20:16, Souptick Joarder wrote:
>
> Use new return type vm_fault_t for page_mkwrite
> and fault handler.
>
> vmf_error() is the newly introduce inline function
> in 4.17
>
> Signed-off-by: Souptick Joarder
> Reviewed-by: Matthew Wilcox
> ---
> fs/ceph/addr.c | 62 +
On 07/23/2018 10:16 AM, Marc Kleine-Budde wrote:
> On 06/25/2018 09:59 AM, Marcel Ziswiler wrote:
>> From: Marcel Ziswiler
>>
>> CAN2 currently fails on probe as follows:
>>
>> mcp251x spi1.1: Probe failed, err=19
>>
>> Fix this by enabling input on pin mux of resp. SPI4 pins.
>>
>> Signed-off-by:
On Fri, 20 Jul 2018, Kamalesh Babulal wrote:
> livepatch module author can pass module name/old function name with more
> than the defined character limit. With obj->name length greater than
> MODULE_NAME_LEN, the livepatch module gets loaded but waits forever on
> the module specified by obj->nam
On Thu, Jul 19, 2018 at 12:21:44AM +0200, Thomas Gleixner wrote:
> On Tue, 17 Jul 2018, Kirill A. Shutemov wrote:
>
> > Per-KeyID direct mappings require changes into how we find the right
> > virtual address for a page and virt-to-phys address translations.
> >
> > page_to_virt() definition over
As SD Host Controller Specification v4.10 documents:
Host Controller Version 4.10 defines this "Auto CMD Auto Select" mode.
Selection of Auto CMD depends on setting of CMD23 Enable in the Host
Control 2 register which indicates whether card supports CMD23. If CMD23
Enable =1, Auto CMD23 is used and
From: Chunyan Zhang
This patch adds the device-tree binding documentation for Spreadtrum
SDHCI driver.
Signed-off-by: Chunyan Zhang
---
.../devicetree/bindings/mmc/sdhci-sprd.txt | 41 ++
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/
Dear Jörg,
On 07/20/18 14:31, Jörg Rödel wrote:
> On Tue, Jul 17, 2018 at 06:02:07PM +0200, Paul Menzel wrote:
>> $ dmesg
>> […]
>> [0.145696] calling pci_iommu_init+0x0/0x3f @ 1
>> [0.145719] AMD-Vi: Unable to write to IOMMU perf counter.
>
> This is likely a firmware issue. Either th
Host Controller Version 4.10 re-defines SDMA System Address register
as 32-bit Block Count for v4 mode, and SDMA uses ADMA System
Address register (05Fh-058h) instead if v4 mode is enabled. Also
when using 32-bit block count, 16-bit block count register need
to be set to zero.
Signed-off-by: Chuny
For SD host controller version 4.00 or later ones, there're two
modes of implementation - Version 3.00 compatible mode or
Version 4 mode. This patch introduced an interface to enable
v4 mode.
Signed-off-by: Chunyan Zhang
---
drivers/mmc/host/sdhci.c | 28
drivers/mm
From: Chunyan Zhang
This patch adds the initial support of Secure Digital Host Controller
Interface compliant controller found in some latest Spreadtrum chipsets.
This patch has been tested on the version of SPRD-R11 controller.
R11 is a variant based on SD v4.0 specification.
With this driver,
According to the SD host controller specification version 4.10, when
Host Version 4 is enabled, SDMA uses ADMA System Address register
(05Fh-058h) instead of using SDMA System Address register to
support both 32-bit and 64-bit addressing.
Signed-off-by: Chunyan Zhang
---
drivers/mmc/host/sdhci.c
ADMA2 64-bit addressing support is divided into V3 mode and V4 mode.
So there are two kinds of descriptors for ADMA2 64-bit addressing
i.e. 96-bit Descriptor for V3 mode, and 128-bit Descriptor for V4
mode. 128-bit Descriptor is aligned to 8-byte.
For V4 mode, ADMA2 64-bit addressing is enabled vi
>From the SD host controller version 4.0 on, SDHCI implementation either
is version 3 compatible or version 4 mode. This patch-set covers those
changes which are common for SDHCI 4.0 version, regardless of whether
they are used with SD or eMMC storage devices.
This patchset also added a new sdhci
On Wed, Jul 18, 2018 at 05:01:37PM -0700, Dave Hansen wrote:
> On 07/17/2018 04:20 AM, Kirill A. Shutemov wrote:
> > arch/x86/include/asm/mktme.h | 8 +
> > arch/x86/mm/init_64.c| 10 +
> > arch/x86/mm/mktme.c | 437 +++
> > 3 files changed, 455
Below is the list of build error/warning regressions/improvements in
v4.18-rc6[1] compared to v4.17[2].
Summarized:
- build errors: +2/-1
- build warnings: +222/-46421
JFYI, when comparing v4.18-rc6[1] to v4.18-rc5[3], the summaries are:
- build errors: +0/-104
- build warnings: +77/-63
Hi Sayali,
On 7/13/2018 3:22 PM, Sayali Lokhande wrote:
This change adds the use of devfreq to MMC.
Both eMMC and SD card will use it.
For some workloads, such as video playback, it isn't
necessary for these cards to run at high speed.
Running at lower frequency, for example 52MHz, in such
cases
Hi all,
Changes since 20180720:
Dropped trees: xarray, ida (complex conflicts)
The drm-msm tree gained a conflict against the drm tree and a build
failure due to an interaction with the drm tree for which I added a
merge fix patch.
The kvm-arm tree gained a conflict against the arm64 tree.
The
On Mon, Jul 16, 2018 at 12:30:05PM +0100, Mark Rutland wrote:
> Hi Ingo,
Sorry to ping, but are you happy to pick this up?
Mark.
> Are you happy to pick this series? Both Will and Peter are happy with v3, and
> since then I've only made a minor cleanup to the commit messages for patches
> 8-10 (
Viele Grüße von mir. Wie geht es Ihnen heute? Verzeih mir, dass ich deinen
Frieden gestört habe, ich verstehe meine Herangehensweise vielleicht sehr
ungeschickt und unhöflich, bitte ich bitte, dass du mir verzeihst, ein
Eindringling zu sein. Ich bin Wesley mit Namen, ich bin aus dem Vereinigten
Viele Grüße von mir. Wie geht es Ihnen heute? Verzeih mir, dass ich deinen
Frieden gestört habe, ich verstehe meine Herangehensweise vielleicht sehr
ungeschickt und unhöflich, bitte ich bitte, dass du mir verzeihst, ein
Eindringling zu sein. Ich bin Wesley mit Namen, ich bin aus dem Vereinigten
On Wed, Jul 18, 2018 at 04:53:27PM -0700, Dave Hansen wrote:
> The description doesn't mention the potential performance implications
> of this patch. That's criminal at this point.
>
> > --- a/arch/x86/mm/mktme.c
> > +++ b/arch/x86/mm/mktme.c
> > @@ -1,4 +1,5 @@
> > #include
> > +#include
> >
On Fri, Jun 29, 2018 at 02:09:47PM +0200, Alessio Balsini wrote:
Joel nailed it wrt the Changelog, that needs improvement.
> diff --git a/kernel/sched/deadline.c b/kernel/sched/deadline.c
> index fbfc3f1d368a..f75a4169cd47 100644
> --- a/kernel/sched/deadline.c
> +++ b/kernel/sched/deadline.c
>
On 06/25/2018 09:59 AM, Marcel Ziswiler wrote:
> From: Marcel Ziswiler
>
> CAN2 currently fails on probe as follows:
>
> mcp251x spi1.1: Probe failed, err=19
>
> Fix this by enabling input on pin mux of resp. SPI4 pins.
>
> Signed-off-by: Marcel Ziswiler
I can take this via the linux-can tre
On Wed, Jul 18, 2018 at 04:40:14PM -0700, Dave Hansen wrote:
> > --- a/arch/x86/mm/mktme.c
> > +++ b/arch/x86/mm/mktme.c
> > @@ -1,3 +1,4 @@
> > +#include
> > #include
> >
> > phys_addr_t mktme_keyid_mask;
> > @@ -37,3 +38,14 @@ struct page_ext_operations page_mktme_ops = {
> > .need = ne
On Mon, Jul 23, 2018 at 11:42:28AM +0200, Florian Westphal wrote:
> Pablo Neira Ayuso wrote:
> > > As David pointed out, once ->start() returns 0 we set cb_running, i.e.
> > > only after successful ->start() netlink core will call ->dump() again.
> > >
> > > So I see no problem setting ->data to
On 06/28/2018 07:41 PM, Gustavo A. R. Silva wrote:
> In preparation to enabling -Wimplicit-fallthrough, mark switch cases
> where we are expecting to fall through.
>
> Signed-off-by: Gustavo A. R. Silva
applied to linux-can-next.
Tnx,
Marc
--
Pengutronix e.K. | Marc Kleine-Bu
If multi-bds used in one transfer, all bds should be consisten
memory.To easily follow it, enlarge the dma pool size into 20 bds,
and it will report error if the number of bds is over than 20. For
dmatest, the max count for single transfer is NUM_BD *
SDMA_BD_MAX_CNT = 20 * 65535 = ~1.28MB.
Signed
Add MEMCPY capability for imx-sdma driver.
Signed-off-by: Robin Gong
---
drivers/dma/imx-sdma.c | 93 --
1 file changed, 90 insertions(+), 3 deletions(-)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index e3d5e73..b4ec2d2 100644
--
On Wed, Jul 18, 2018 at 04:38:02PM -0700, Dave Hansen wrote:
> On 07/17/2018 04:20 AM, Kirill A. Shutemov wrote:
> > Store KeyID in bits 31:16 of extended page flags. These bits are unused.
>
> I'd love a two sentence remind of what page_ext is and why you chose to
> use it. Yes, you need this.
Add macro SDMA_BD_MAX_CNT to replace '0x'.
Signed-off-by: Robin Gong
---
drivers/dma/imx-sdma.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 3b622d6..e3d5e73 100644
--- a/drivers/dma/imx-sdma.c
+++ b/dri
This patchset is to add memcpy interface for imx-sdma, besides,to
support dmatest and enable config by default, so that could test dma
easily without any other device support such as uart/audio/spi...
Change from v2:
1. remove 'copy_align' since sdma script for memory_2_memory will handle
s
Hi Andrew,
After merging the akpm tree, today's linux-next build (sparc (32 bit)
defconfig) failed like this:
In file included from kernel/crash_core.c:9:0:
kernel/crash_core.c: In function 'crash_save_vmcoreinfo_init':
include/linux/crash_core.h:44:66: error: lvalue required as unary '&' operand
On Mon, 23 Jul 2018 11:34:43 +0200
Arnd Bergmann wrote:
> On Sun, Jul 22, 2018 at 8:29 AM, Boris Brezillon
> wrote:
> > +Arnd, Rob and the DT ML.
> >
> > On Sat, 21 Jul 2018 14:53:47 -0700
> > Randy Dunlap wrote:
> >
> >> On 07/21/2018 01:00 PM, Anders Roxell wrote:
> >> > JZ4780_NEMC doesn
As this doesn't depend on any other patch in this series, I think it
would be fine if Philipp takes this patch through the reset tree.
Regards,
Lucas
Am Freitag, den 20.07.2018, 15:47 +0300 schrieb Leonard Crestez:
> Right now the only user of reset-imx7 is pci-imx6 and the
> reset_control_assert
On Mon, Jul 23, 2018 at 02:49:27PM +0530, Mukesh Ojha wrote:
> On 7/23/2018 1:57 PM, Mukesh Ojha wrote:
> >
> > Hi All,
> >
> > I wanted to discuss about one of the corner case exists in 4.9 kernel
> > (4.9.x) where
4.9 is over 1 1/2 years old now. Please test this on 4.17 or better
yet, 4.18-r
Hi Leonard,
Am Freitag, den 20.07.2018, 15:47 +0300 schrieb Leonard Crestez:
> On imx7d the pcie-phy power domain is turned off in suspend and this can
> make the system hang after resume when attempting any read from PCI.
>
> Fix this by adding minimal suspend/resume code from the nxp internal
>
Hi Jonathan,
Thanks for your comments.
> -Original Message-
> From: Jonathan Cameron [mailto:ji...@kernel.org]
> Sent: Saturday, July 21, 2018 9:54 PM
> To: Lars-Peter Clausen
> Cc: Manish Narani ; knaac...@gmx.de;
> pme...@pmeerw.net; Michal Simek ; linux-
> i...@vger.kernel.org; linux-
On Sun, Jul 22, 2018 at 8:29 AM, Boris Brezillon
wrote:
> +Arnd, Rob and the DT ML.
>
> On Sat, 21 Jul 2018 14:53:47 -0700
> Randy Dunlap wrote:
>
>> On 07/21/2018 01:00 PM, Anders Roxell wrote:
>> > JZ4780_NEMC doesn't depend on OF, and if OF isn't enabled we get this
>> > error:
>> > drivers/me
From: Liang Chen
This patch add px30-evb.dts for PX30 evaluation board.
Tested on PX30 evb.
Acked-by: Rob Herring
Signed-off-by: Liang Chen
---
Documentation/devicetree/bindings/arm/rockchip.txt | 4 +
arch/arm64/boot/dts/rockchip/Makefile | 1 +
arch/arm64/boot/dts/rockchip/
On 2018-07-23 09:50, Peter De Schrijver wrote:
On Fri, Jul 20, 2018 at 02:45:26PM +0100, Ben Dooks wrote:
The host1x clock according to both tegra2 and tegra3 manuals is
an 8bit divider with lsb being fractional. This is running into
an issue where the host1x is being set on a tegra20a system
From: Liang Chen
This patch adds core dtsi file for Rockchip PX30 SoCs.
Signed-off-by: Liang Chen
---
arch/arm64/boot/dts/rockchip/px30.dtsi | 2043
1 file changed, 2043 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/px30.dtsi
diff --git a/arch
Imitate the ACPI code to parse ACPI tables. Functions are simplified
cause some operations are not needed here.
And also, this method won't influence the initialization of ACPI.
Signed-off-by: Chao Fan
---
arch/x86/boot/compressed/Makefile | 4 +
arch/x86/boot/compressed/acpitb.c | 251 +++
On Mon, 23 Jul 2018 10:56:46 +0200,
Yue Wang wrote:
>
> Thesycon provides solutions to XMOS chips, and has its own device vendor id.
>
> In this patch, we use generic method to detect DSD capability of
> Thesycon-based UAC2
> implementations in order to support a wide range of current and future
On Wed, Jul 04, 2018 at 11:27:27AM +0800, 王贇 wrote:
> @@ -6788,6 +6790,12 @@ static int cpu_cfs_stat_show(struct seq_file *sf, void
> *v)
> seq_printf(sf, "nr_throttled %d\n", cfs_b->nr_throttled);
> seq_printf(sf, "throttled_time %llu\n", cfs_b->throttled_time);
>
> + if (scheds
If 'CONFIG_MEMORY_HOTREMOVE' specified and the account of immovable
memory regions is not zero. Calculate the intersection between memory
regions from e820/efi memory table and immovable memory regions.
Or go on the old code.
Rename process_mem_region to slots_count to match slots_fetch_random,
an
If 'CONFIG_MEMORY_HOTREMOVE' specified, walk the acpi srat memory
tables, store the immovable memory regions, so that kaslr can get
the information abouth where can be selected or not.
If 'CONFIG_MEMORY_HOTREMOVE' not specified, go on the old code.
Signed-off-by: Chao Fan
---
arch/x86/boot/compr
In order to parse ACPI tables, reuse the head file linux/acpi.h,
so that the files in 'compressed' directory can read ACPI table
by including this head file.
Signed-off-by: Chao Fan
---
arch/x86/boot/compressed/acpitb.h | 7 +++
1 file changed, 7 insertions(+)
create mode 100644 arch/x86/bo
***Background:
People reported that kaslr may randomly chooses some positions
which are located in movable memory regions. This will break memory
hotplug feature and make the memory can't be removed.
***Solutions:
There should be a method to limit kaslr to choosing immovable memory
regions, so the
> >> If we determined tsc early in boot using one of the quick methods:
> >> from cpuid/msr/quick_pit, can we assume that frequencies of all other
> >> CPUs will be determined the same way? Or do we still have to fallback
Not on 32bit at least. You can have a mixed slot 1 SMP system such as
an ASU
From: Liang Chen
This patch adds the compatible of dwc2 for PX30 SoCs.
Acked-by: Rob Herring
Signed-off-by: Liang Chen
---
Documentation/devicetree/bindings/usb/dwc2.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt
b/Documentation/devicet
From: Liang Chen
This patch adds the compatible of GRF and PMUGRF for PX30 SoCs.
Acked-by: Rob Herring
Signed-off-by: Liang Chen
---
Documentation/devicetree/bindings/soc/rockchip/grf.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.
From: Liang Chen
Add "rockchip,px30-i2s", "rockchip,rk3066-i2s" for i2s on px30 platform.
Acked-by: Rob Herring
Signed-off-by: Liang Chen
---
Documentation/devicetree/bindings/sound/rockchip-i2s.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/sound/ro
Pablo Neira Ayuso wrote:
> > diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c
> > --- a/net/netfilter/nf_tables_api.c
> > +++ b/net/netfilter/nf_tables_api.c
> > @@ -5010,6 +5013,22 @@ nft_obj_filter_alloc(const struct nlattr * const
> > nla[])
> > return filter;
> >
From: Liang Chen
Add "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc" for
dwmmc on px30 platform.
Acked-by: Rob Herring
Signed-off-by: Liang Chen
---
Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindi
Hi Lars,
> -Original Message-
> From: Lars-Peter Clausen [mailto:l...@metafoo.de]
> Sent: Thursday, July 19, 2018 10:08 PM
> To: Manish Narani ; ji...@kernel.org;
> knaac...@gmx.de; pme...@pmeerw.net; Michal Simek
> ; linux-...@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; linu
From: Liang Chen
Changes in V2:
1. change the subject to format "dt-bindings: module: ..." for the documents.
2. use new property for backlight.
3. remove pinctrl of rk809, because the driver is not ready.
Liang Chen (6):
dt-bindings: usb: dwc2: add description for px30
dt-bindings: mmc: r
wait_for_completion_timeout returns unsigned long not int so an appropriate
variable is declared and the assignment and check fixed up.
Signed-off-by: Nicholas Mc Guire
---
found by experimental coccinelle script
As the timeout returned is always << INT_MAX there is no side-effect with the
type
On Tue, Jul 17, 2018 at 12:08:36PM +0800, Xunlei Pang wrote:
> The trace data corresponds to the last sample period:
> trace entry 1:
> cat-20755 [022] d... 1370.106496: cputime_adjust: task
> tick-based utime 36256000 stime 255100, scheduler rtime 333060702626
>
Adding stable and lkml.
Sorry for spam others.
-Mukesh
On 7/23/2018 1:57 PM, Mukesh Ojha wrote:
Hi All,
I wanted to discuss about one of the corner case exists in 4.9 kernel
(4.9.x) where
If hotplug of one of the CPU fails due to failure in one of the callback,
which is to be called after
firmware_map_add_hotplug() is only called by add_memory_resource(),
which is never called in atomic context.
firmware_map_add_hotplug() calls kzalloc() with GFP_ATOMIC,
which is not necessary.
GFP_ATOMIC can be replaced with GFP_KERNEL.
This is found by a static analysis tool named DCNS written b
Hi Miquel,
> -Original Message-
> From: Miquel Raynal [mailto:miquel.ray...@bootlin.com]
> Sent: Monday, July 23, 2018 1:01 PM
> To: Naga Sureshkumar Relli
> Cc: boris.brezil...@bootlin.com; rich...@nod.at; dw...@infradead.org;
> computersforpe...@gmail.com; marek.va...@gmail.com; f.faine
On Mon, 2018-07-23 at 15:39 +1000, Stephen Rothwell wrote:
> Hi Greg,
>
> After merging the tty tree, today's linux-next build (arm
> multi_v7_defconfig) produced this warning:
>
> drivers/tty/serial/8250/8250_exar.c: In function 'pci_xr17v35x_setup':
> drivers/tty/serial/8250/8250_exar.c:380:31:
The kernel-doc for mempool_init function is missing the description of the
pool parameter. Add it.
Signed-off-by: Mike Rapoport
---
mm/mempool.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/mm/mempool.c b/mm/mempool.c
index b54f2c2..9e16b63 100644
--- a/mm/mempool.c
+++ b/mm/mempool.c
@@
sbp2_scsi_queuecommand() is only set to .queuecommand of
"struct scsi_host_template", and this function pointer is never called
in atomic context.
sbp2_scsi_queuecommand() calls kzalloc() with GFP_ATOMIC,
which is not necessary.
GFP_ATOMIC can be replaced with GFP_KERNEL.
This is found by a stat
Thesycon provides solutions to XMOS chips, and has its own device vendor id.
In this patch, we use generic method to detect DSD capability of Thesycon-based
UAC2
implementations in order to support a wide range of current and future devices.
The patch will enable the SNDRV_PCM_FMTBIT_DSD_U32_BE
On Mon, 23 Jul 2018 10:54:49 +0200,
Yue Wang wrote:
>
> Please ignore this commit. there's something wrong. My apologies again.
Heh, don't worry. BTW, at the next submission, please fix the subject
prefix as well. The usual subject line for ALSA code is like:
ALSA: usb-audio: Blah blah...
Please ignore this commit. there's something wrong. My apologies again.
On Mon, Jul 23, 2018 at 1:53 AM Yue Wang wrote:
>
> Thesycon provides solutions to XMOS chips, and has its own device vendor id.
>
> In this patch, we use generic method to detect DSD capability of
> Thesycon-based UAC2
> imp
Thanks for the comment Jussi. Let's drop this patch, and I will send a
new patch with this generic approach shortly. The new patch will have
a different commit title and message.
On Mon, Jul 23, 2018 at 1:26 AM Jussi Laako wrote:
>
> Hi,
>
> > + case USB_ID(0x152a, 0x8750): /* Topping DX7s */
Hi Adam,
On Sat, Jul 21, 2018 at 11:39 PM Adam Borowski wrote:
> Technically, every console can be made to blink by drawing/clearing affected
> characters a few times per second, but that'd be quite a waste of coding
> time and kernel size. There's a reason browsers dropped support for
> and te
Thesycon provides solutions to XMOS chips, and has its own device vendor id.
In this patch, we use generic method to detect DSD capability of Thesycon-based
UAC2
implementations in order to support a wide range of current and future devices.
The patch will enable the SNDRV_PCM_FMTBIT_DSD_U32_BE
Hi,
The subject should be rtc: rk808: add RK809 and RK817 support
With that fixed:
On 23/07/2018 11:19:04+0800, Tony Xie wrote:
> RK809 and RK817 are power management IC chips for multimedia products.
> Most of their functions and registers are same, including the rtc.
>
> Signed-off-by: Tony X
On Fri, Jul 20, 2018 at 02:45:27PM +0100, Ben Dooks wrote:
> The clocks vde, vi, epp, mpe, 2d and 3d are all fractional
> divisors, and not integer divisors as setup in the current
> kernel. This seems to be the same for tegra2 and tegra3.
>
Same comment as the host1x clock patch.
> Signed-off-b
Hi Bjorn and Keith,
This discussion is to extend the idea of follwing patch.
[PATCH] PCI/AER: Enable SERR# forwarding in non ACPI flow
PCIe Spec
7.6.2.1.3 Command Register (Offset 04h)
SERR# Enable – See Section 7.6.2.1.14.
When Set, this bit enables reporting upstream of Non-fatal and Fatal
e
On Fri, Jul 20, 2018 at 02:45:26PM +0100, Ben Dooks wrote:
> The host1x clock according to both tegra2 and tegra3 manuals is
> an 8bit divider with lsb being fractional. This is running into
> an issue where the host1x is being set on a tegra20a system to
> 266.4MHz but ends up at 222MHz instead.
>
On Mon, Jul 23, 2018 at 01:39:30PM +0800, Chen Lin wrote:
> From: Chen Lin
>
> NUMA balancing has not taken *isolcpus(isolated cpus)* into
> consideration. It may migrate tasks onto isolated cpus and the
> migrated tasks will never escape from the isolated cpus, which will
> break the isolation
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