Re: [PATCH v2 5/6] 9p: Use a slab for allocating requests

Greg Kurz wrote on Mon, Jul 23, 2018: > The patch is quite big and I'm not sure I can find time to review it > carefully, but I'll try to help anyway. No worry, thanks for this already. > > Sorry for coming back to this patch now, I just noticed something that's > > actually probably a fairly

[PATCH 4.4 055/107] x86/bugs: Expose /sys/../spec_store_bypass

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Konrad Rzeszutek Wilk commit c456442cd3a59eeb1d60293c26cbe2ff2c4e42cf upstream Add the sysfs file for the new vulerability. It does not do much except show the words 'Vulnerable' for recent

[PATCH 4.4 050/107] x86/bugs: Concentrate bug reporting into a separate function

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Konrad Rzeszutek Wilk commit d1059518b4789cabe34bb4b714d07e6089c82ca1 upstream Those SysFS functions have a similar preamble, as such make common code to handle them. Suggested-by: Borislav

[PATCH 4.4 051/107] x86/bugs: Read SPEC_CTRL MSR during boot and re-use reserved bits

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Konrad Rzeszutek Wilk commit 1b86883ccb8d5d9506529d42dbe1a5257cb30b18 upstream The 336996-Speculative-Execution-Side-Channel-Mitigations.pdf refers to all the other bits as reserved. The Intel

[PATCH 4.4 023/107] x86/pti: Do not enable PTI on CPUs which are not vulnerable to Meltdown

4.4-stable review patch. If anyone has any objections, please let me know. -- From: David Woodhouse (cherry picked from commit fec9434a12f38d3aeafeb75711b71d8a1fdef621) Also, for CPUs which don't speculate at all, don't report that they're vulnerable to the Spectre variants

[PATCH 4.4 033/107] x86/speculation: Clean up various Spectre related details

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Ingo Molnar commit 21e433bdb95bdf3aa48226fd3d33af608437f293 upstream. Harmonize all the Spectre messages so that a: dmesg | grep -i spectre ... gives us most Spectre related kernel boot

[PATCH 4.4 054/107] x86/cpu/intel: Add Knights Mill to Intel family

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Piotr Luc commit 0047f59834e5947d45f34f5f12eb330d158f700b upstream Add CPUID of Knights Mill (KNM) processor to Intel family list. Signed-off-by: Piotr Luc Reviewed-by: Dave Hansen Cc: Andy

[PATCH 4.4 058/107] x86/bugs/intel: Set proper CPU features and setup RDS

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Konrad Rzeszutek Wilk commit 772439717dbf703b39990be58d8d4e3e4ad0598a upstream Intel CPUs expose methods to: - Detect whether RDS capability is available via CPUID.7.0.EDX[31], - The

[PATCH 4.4 017/107] xhci: Fix perceived dead host due to runtime suspend race with event handler

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Mathias Nyman commit 229bc19fd7aca4f37964af06e3583c1c8f36b5d6 upstream. Don't rely on event interrupt (EINT) bit alone to detect pending port change in resume. If no change event is detected

[PATCH 4.4 014/107] tg3: Add higher cpu clock for 5762.

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Sanjeev Bansal [ Upstream commit 3a498606bb04af603a46ebde8296040b2de350d1 ] This patch has fix for TX timeout while running bi-directional traffic with 100 Mbps using 5762. Signed-off-by:

[PATCH 4.4 015/107] net: Dont copy pfmemalloc flag in __copy_skb_header()

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Stefano Brivio [ Upstream commit 8b7008620b8452728cadead460a36f64ed78c460 ] The pfmemalloc flag indicates that the skb was allocated from the PFMEMALLOC reserves, and the flag is currently

[PATCH 4.4 008/107] ipv4: Return EINVAL when ping_group_range sysctl doesnt map to user ns

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Tyler Hicks [ Upstream commit 70ba5b6db96ff7324b8cfc87e0d0383cf59c9677 ] The low and high values of the net.ipv4.ping_group_range sysctl were being silently forced to the default disabled

[PATCH 4.4 009/107] ipv6: fix useless rol32 call on hash

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Colin Ian King [ Upstream commit 169dc027fb02492ea37a0575db6a658cf922b854 ] The rol32 call is currently rotating hash but the rol'd value is being discarded. I believe the current code is

[PATCH 4.4 007/107] mm: memcg: fix use after free in mem_cgroup_iter()

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Jing Xia commit 9f15bde671355c351cf20d9f879004b234353100 upstream. It was reported that a kernel crash happened in mem_cgroup_iter(), which can be triggered if the legacy cgroup-v1

[PATCH 4.4 002/107] x86/MCE: Remove min interval polling limitation

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Dewet Thibaut commit fbdb328c6bae0a7c78d75734a738b66b86dffc96 upstream. commit b3b7c4795c ("x86/MCE: Serialize sysfs changes") introduced a min interval limitation when setting the check

[PATCH 4.4 004/107] ALSA: rawmidi: Change resized buffers atomically

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Takashi Iwai commit 39675f7a7c7e7702f7d5341f1e0d01db746543a0 upstream. The SNDRV_RAWMIDI_IOCTL_PARAMS ioctl may resize the buffers and the current code is racy. For example, the sequencer

[PATCH 4.4 043/107] x86/speculation: Remove Skylake C2 from Speculation Control microcode blacklist

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Alexander Sergeyev commit e3b3121fa8da94cb20f9e0c64ab7981ae47fd085 upstream. In accordance with Intel's microcode revision guidance from March 6 MCU rev 0xc2 is cleared on both Skylake H/S and

Re: [PATCH] cpufreq: qcom-kryo: add NULL entry to the end of_device_id array

On Mon, Jul 23, 2018 at 3:38 PM YueHaibing wrote: > > Make sure of_device_id tables are NULL terminated > Found by coccinelle spatch "misc/of_table.cocci" > > Signed-off-by: YueHaibing > --- > drivers/cpufreq/qcom-cpufreq-kryo.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git

[PATCH 4.4 011/107] net/ipv4: Set oif in fib_compute_spec_dst

4.4-stable review patch. If anyone has any objections, please let me know. -- From: David Ahern [ Upstream commit e7372197e15856ec4ee66b668020a662994db103 ] Xin reported that icmp replies may not use the address on the device the echo request is received if the destination

[PATCH 4.4 016/107] skbuff: Unconditionally copy pfmemalloc in __skb_clone()

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Stefano Brivio [ Upstream commit e78bfb0751d4e312699106ba7efbed2bab1a53ca ] Commit 8b7008620b84 ("net: Don't copy pfmemalloc flag in __copy_skb_header()") introduced a different handling for

[PATCH 4.4 013/107] ptp: fix missing break in switch

4.4-stable review patch. If anyone has any objections, please let me know. -- From: "Gustavo A. R. Silva" [ Upstream commit 9ba8376ce1e2cbf4ce44f7e4bee1d0648e10d594 ] It seems that a *break* is missing in order to avoid falling through to the default case. Otherwise, checking

[PATCH 4.4 012/107] net: phy: fix flag masking in __set_phy_supported

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Heiner Kallweit [ Upstream commit df8ed346d4a806a6eef2db5924285e839604b3f9 ] Currently also the pause flags are removed from phydev->supported because they're not included in

[PATCH 4.4 041/107] x86/speculation: Use IBRS if available before calling into firmware

4.4-stable review patch. If anyone has any objections, please let me know. -- From: David Woodhouse commit dd84441a797150dcc49298ec95c459a8891d8bb1 upstream. Retpoline means the kernel is safe because it has no indirect branches. But firmware isn't, so use IBRS for firmware

[PATCH 4.4 038/107] x86/mm: Give each mm TLB flush generation a unique ID

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Andy Lutomirski commit f39681ed0f48498b80455095376f11535feea332 upstream. This adds two new variables to mmu_context_t: ctx_id and tlb_gen. ctx_id uniquely identifies the mm_struct and will

[PATCH 4.4 042/107] x86/speculation: Move firmware_restrict_branch_speculation_*() from C to CPP

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Ingo Molnar commit d72f4e29e6d84b7ec02ae93088aa459ac70e733b upstream. firmware_restrict_branch_speculation_*() recently started using preempt_enable()/disable(), but those are relatively high

[PATCH 4.4 032/107] x86/speculation: Correct Speculation Control microcode blacklist again

4.4-stable review patch. If anyone has any objections, please let me know. -- From: David Woodhouse commit d37fc6d360a404b208547ba112e7dabb6533c7fc upstream. Arjan points out that the Intel document only clears the 0xc2 microcode on *some* parts with CPUID 506E3

[PATCH 4.4 035/107] x86/speculation: Add dependency

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Peter Zijlstra commit ea00f301285ea2f07393678cd2b6057878320c9d upstream. Joe Konno reported a compile failure resulting from using an MSR without inclusion of , and while the current code

[PATCH 4.4 021/107] x86/cpufeatures: Add AMD feature bits for Speculation Control

4.4-stable review patch. If anyone has any objections, please let me know. -- From: David Woodhouse (cherry picked from commit 5d10cbc91d9eb5537998b65608441b592eec65e7) AMD exposes the PRED_CMD/SPEC_CTRL MSRs slightly differently to Intel. See

[PATCH 4.4 048/107] x86/nospec: Simplify alternative_msr_write()

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Linus Torvalds commit 1aa7a5735a41418d8e01fa7c9565eb2657e2ea3f upstream The macro is not type safe and I did look for why that "g" constraint for the asm doesn't work: it's because the asm is

[PATCH 4.4 031/107] x86/speculation: Update Speculation Control microcode blacklist

4.4-stable review patch. If anyone has any objections, please let me know. -- From: David Woodhouse commit 1751342095f0d2b36fa8114d8e12c5688c455ac4 upstream. Intel have retroactively blessed the 0xc2 microcode on Skylake mobile and desktop parts, and the Gemini Lake 0x22

[PATCH 4.4 037/107] x86/mm: Factor out LDT init from context init

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Dave Hansen commit 39a0526fb3f7d93433d146304278477eb463f8af upstream The arch-specific mm_context_t is a great place to put protection-key allocation state. But, we need to initialize the

[PATCH 4.4 030/107] x86/entry/64/compat: Clear registers for compat syscalls, to reduce speculation attack surface

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Dan Williams commit 6b8cf5cc9965673951f1ab3f0e3cf23d06e3e2ee upstream. At entry userspace may have populated registers with values that could otherwise be useful in a speculative execution

[PATCH 4.4 022/107] x86/msr: Add definitions for new speculation control MSRs

4.4-stable review patch. If anyone has any objections, please let me know. -- From: David Woodhouse (cherry picked from commit 1e340c60d0dd3ae07b5bedc16a0469c14b9f3410) Add MSR and bit definitions for SPEC_CTRL, PRED_CMD and ARCH_CAPABILITIES. See Intel's

[PATCH 4.4 088/107] x86/speculation: Handle HT correctly on AMD

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Thomas Gleixner commit 1f50ddb4f4189243c05926b842dc1a0332195f31 upstream The AMD64_LS_CFG MSR is a per core MSR on Family 17H CPUs. That means when hyperthreading is enabled the SSBD bit

[PATCH 4.4 090/107] x86/speculation: Add virtualized speculative store bypass disable support

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Tom Lendacky commit 11fb0683493b2da112cd64c9dada221b52463bf7 upstream Some AMD processors only support a non-architectural means of enabling speculative store bypass disable (SSBD). To allow

[PATCH 4.4 089/107] x86/bugs, KVM: Extend speculation control for VIRT_SPEC_CTRL

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Thomas Gleixner commit ccbcd2674472a978b48c91c1fbfb66c0ff959f24 upstream AMD is proposing a VIRT_SPEC_CTRL MSR to handle the Speculative Store Bypass Disable via MSR_AMD64_LS_CFG so that

[PATCH 4.4 087/107] x86/cpufeatures: Add FEATURE_ZEN

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Thomas Gleixner commit d1035d971829dcf80e8686ccde26f94b0a069472 upstream Add a ZEN feature bit so family-dependent static_cpu_has() optimizations can be built for ZEN. Signed-off-by: Thomas

[PATCH 4.4 097/107] x86/bugs: Rename SSBD_NO to SSB_NO

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Konrad Rzeszutek Wilk commit 240da953fcc6a9008c92fae5b1f727ee5ed167ab upstream The "336996 Speculative Execution Side Channel Mitigations" from May defines this as SSB_NO, hence lets sync-up.

[PATCH 4.4 093/107] x86/bugs: Expose x86_spec_ctrl_base directly

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Thomas Gleixner commit fa8ac4988249c38476f6ad678a4848a736373403 upstream x86_spec_ctrl_base is the system wide default value for the SPEC_CTRL MSR. x86_spec_ctrl_get_default() returns

[PATCH 4.4 095/107] x86/bugs: Rework spec_ctrl base and mask logic

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Thomas Gleixner commit be6fcb5478e95bb1c91f489121238deb3abca46a upstream x86_spec_ctrL_mask is intended to mask out bits from a MSR_SPEC_CTRL value which are not to be modified. However the

[PATCH 4.4 092/107] x86/bugs: Unify x86_spec_ctrl_{set_guest, restore_host}

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Borislav Petkov commit cc69b34989210f067b2c51d5539b5f96ebcc3a01 upstream Function bodies are very similar and are going to grow more almost identical code. Add a bool arg to determine whether

[PATCH 4.4 094/107] x86/bugs: Remove x86_spec_ctrl_set()

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Thomas Gleixner commit 4b59bdb569453a60b752b274ca61f009e37f4dae upstream x86_spec_ctrl_set() is only used in bugs.c and the extra mask checks there provide no real value as both call sites can

[PATCH 4.4 091/107] x86/speculation: Rework speculative_store_bypass_update()

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Thomas Gleixner commit 0270be3e34efb05a88bc4c422572ece038ef3608 upstream The upcoming support for the virtual SPEC_CTRL MSR on AMD needs to reuse speculative_store_bypass_update() to avoid

Re: [RFC PATCH] sched/deadline: sched_getattr() returns absolute dl-task information

On 23-Jul 11:49, Peter Zijlstra wrote: [...] > > -void __getparam_dl(struct task_struct *p, struct sched_attr *attr) > > +void __getparam_dl(struct task_struct *p, struct sched_attr *attr, > > + unsigned int flags) > > { > > struct sched_dl_entity *dl_se = >dl; > > > >

[PATCH 4.4 057/107] x86/bugs: Provide boot parameters for the spec_store_bypass_disable mitigation

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Konrad Rzeszutek Wilk commit 24f7fc83b9204d20f878c57cb77d261ae825e033 upstream Contemporary high performance processors use a common industry-wide optimization known as "Speculative Store

[PATCH 4.4 059/107] x86/bugs: Whitelist allowed SPEC_CTRL MSR values

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Konrad Rzeszutek Wilk commit 1115a859f33276fe8afb31c60cf9d8e657872558 upstream Intel and AMD SPEC_CTRL (0x48) MSR semantics may differ in the future (or in fact use different MSRs for the same

[PATCH 4.4 027/107] x86/cpuid: Fix up "virtual" IBRS/IBPB/STIBP feature bits on Intel

4.4-stable review patch. If anyone has any objections, please let me know. -- From: David Woodhouse (cherry picked from commit 7fcae1118f5fd44a862aa5c3525248e35ee67c3b) Despite the fact that all the other code there seems to be doing it, just using set_cpu_cap() in

[PATCH 4.4 029/107] x86/asm/entry/32: Simplify pushes of zeroed pt_regs->REGs

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Denys Vlasenko commit 778843f934e362ed4ed734520f60a44a78a074b4 upstream Use of a temporary R8 register here seems to be unnecessary. "push %r8" is a two-byte insn (it needs REX prefix to

[PATCH 4.4 024/107] x86/cpufeature: Blacklist SPEC_CTRL/PRED_CMD on early Spectre v2 microcodes

4.4-stable review patch. If anyone has any objections, please let me know. -- From: David Woodhouse (cherry picked from commit a5b2966364538a0e68c9fa29bc0a3a1651799035) This doesn't refuse to load the affected microcodes; it just refuses to use the Spectre v2 mitigation

[PATCH 4.4 026/107] x86/cpufeatures: Clean up Spectre v2 related CPUID flags

4.4-stable review patch. If anyone has any objections, please let me know. -- From: David Woodhouse (cherry picked from commit 2961298efe1ea1b6fc0d7ee8b76018fa6c0bcef2) We want to expose the hardware features simply in /proc/cpuinfo as "ibrs", "ibpb" and "stibp". Since AMD

[PATCH 4.4 028/107] x86/pti: Mark constant arrays as __initconst

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Arnd Bergmann (cherry picked from commit 4bf5d56d429cbc96c23d809a08f63cd29e1a702e) I'm seeing build failures from the two newly introduced arrays that are marked 'const' and '__initdata',

[PATCH 4.4 061/107] x86/speculation: Create spec-ctrl.h to avoid include hell

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Thomas Gleixner commit 28a2775217b17208811fa43a9e96bd1fdf417b86 upstream Having everything in nospec-branch.h creates a hell of dependencies when adding the prctl based switching mechanism.

[PATCH 4.17 12/63] x86/MCE: Remove min interval polling limitation

4.17-stable review patch. If anyone has any objections, please let me know. -- From: Dewet Thibaut commit fbdb328c6bae0a7c78d75734a738b66b86dffc96 upstream. commit b3b7c4795c ("x86/MCE: Serialize sysfs changes") introduced a min interval limitation when setting the check

[PATCH 4.17 11/63] x86/events/intel/ds: Fix bts_interrupt_threshold alignment

4.17-stable review patch. If anyone has any objections, please let me know. -- From: Hugh Dickins commit 2c991e408df6a407476dbc453d725e1e975479e7 upstream. Markus reported that BTS is sporadically missing the tail of the trace in the perf_event data buffer: [decode error (1):

Re: [PATCH 1/2] security/keys/secure_key: Adds the secure key support based on CAAM.

Hi, On Sat, 2018-07-21 at 14:44 +, Udit Agarwal wrote: > Thanks for sharing the documentation changes and feedback. > > Below are the answers to the questions: > > 1. Currently the secure key patch series has been added to support > only data blobs. > It is not supporting key blobs as of

Re: [PATCH] nohz: don't kick non-idle CPUs in tick_nohz_full_kick_cpu()

On Fri, Jul 20, 2018 at 07:24:00PM +0200, Thomas Gleixner wrote: > On Thu, 19 Jul 2018, Yury Norov wrote: > > While here. I just wonder, on my system IRQs are sent to nohz_full CPUs > > at every incoming ssh connection. The trace is like this: > > [ 206.835533] Call trace: > > [ 206.848411] []

Re: potential deadlock in cpufreq-dt

Hi all, [since Jiada's initial report was based on 4.14.50+] FWIW, I can consistently reproduce this lockdep issue on 4.18.0-rc6: [ 17.119559] == [ 17.119571] WARNING: possible circular locking dependency detected [ 17.119589] 4.18.0-rc6

[PATCH 09/11] touchscreen: raydium_ts: Use octal permissions

WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static DEVICE_ATTR(fw_version, S_IRUGO, raydium_i2c_fw_ver_show, NULL); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static

[PATCH 10/11] touchscreen: sun4i_ts: Use octal permissions

WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static DEVICE_ATTR(temp1_input, S_IRUGO, show_temp, NULL); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static DEVICE_ATTR(temp1_label,

[PATCH 08/11] touchscreen: melfas: Use octal permissions

WARNING: Symbolic permissions 'S_IWUSR' are not preferred. Consider using octal permissions '0200'. +static DEVICE_ATTR(update_fw, S_IWUSR, NULL, mip4_sysfs_fw_update); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static

[PATCH 07/11] touchscreen: mc13783: Use octal permissions

WARNING: Symbolic permissions 'S_IRUGO | S_IWUSR' are not preferred. Consider using octal permissions '0644'. +module_param(sample_tolerance, uint, S_IRUGO | S_IWUSR); Signed-off-by: Harshit Jain --- drivers/input/touchscreen/mc13783_ts.c | 4 ++-- 1 file changed, 2 insertions(+), 2

[PATCH 02/11] touchscreen: ad7877: Use octal permissions

WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static DEVICE_ATTR(name, S_IRUGO, name ## _show, NULL); Signed-off-by: Harshit Jain --- drivers/input/touchscreen/ad7877.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCH 05/11] touchscreen: elants: Use octal permissions

WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static DEVICE_ATTR(iap_mode, S_IRUGO, show_iap_mode, NULL); WARNING: Symbolic permissions 'S_IWUSR' are not preferred. Consider using octal permissions '0200'. +static DEVICE_ATTR(update_fw,

[PATCH 11/11] touchscreen: tsc200x: Use octal permissions

WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static DEVICE_ATTR(selftest, S_IRUGO, tsc200x_selftest_show, NULL); Signed-off-by: Harshit Jain --- drivers/input/touchscreen/tsc200x-core.c | 2 +- 1 file changed, 1 insertion(+), 1

[PATCH 06/11] touchscreen: ili210x: Use octal permissions

WARNING: Symbolic permissions 'S_IWUSR' are not preferred. Consider using octal permissions '0200'. +static DEVICE_ATTR(calibrate, S_IWUSR, NULL, ili210x_calibrate); Signed-off-by: Harshit Jain --- drivers/input/touchscreen/ili210x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff

[PATCH 01/11] touchscreen: ft5x06: Use octal permissions

WARNING: Symbolic permissions 'S_IWUSR | S_IRUGO' are not preferred. Consider using octal permissions '0644'. +static EDT_ATTR(gain, S_IWUSR | S_IRUGO, WORK_REGISTER_GAIN, WARNING: Symbolic permissions 'S_IWUSR | S_IRUGO' are not preferred. Consider using octal permissions '0644'. +static

Re: [PATCH v2 3/7] iio: tsl2772: add support for reading power settings from device tree

On Sun, Jul 22, 2018 at 11:17 AM Jonathan Cameron wrote: > > On Sun, 22 Jul 2018 12:37:20 + > Brian Masney wrote: > > > On Sat, Jul 21, 2018 at 06:37:16PM +0100, Jonathan Cameron wrote: > > > On Fri, 20 Jul 2018 11:36:35 -0600 > > > Rob Herring wrote: > > > > > > > On Tue, Jul 17, 2018 at

Re: [PATCH 05/11] touchscreen: elants: Use octal permissions

On Mon, Jul 23, 2018 at 06:49:20PM +0530, dev-harsh1998 wrote: > WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using > octal permissions '0444'. > +static DEVICE_ATTR(iap_mode, S_IRUGO, show_iap_mode, NULL); > > WARNING: Symbolic permissions 'S_IWUSR' are not preferred.

[PATCH v3] tg: show the sum wait time of an task group

Although we can rely on cpuacct to present the cpu usage of task group, it is hard to tell how intense the competition is between these groups on cpu resources. Monitoring the wait time of each process or sched_debug could cost too much, and there is no good way to accurately represent the

Re: [PATCH V2 0/2] firmware: ti_sci: Add host-id as an optional parameter

On 17:13-20180716, Nishanth Menon wrote: > Please find attached series to enable host-id as an optional dt property. > > This is a minor update to V1 -> Mostly to pick up Greet's feedback and Rob's > Ack. > > V1: https://patchwork.ozlabs.org/cover/931822/ > > The series is based on v4.18-rc1

Re: [PATCH 02/10] mm: workingset: tell cache transitions from workingset thrashing

On Thu, Jul 12, 2018 at 7:29 PM, Johannes Weiner wrote: > How many page->flags does this leave us with on 32-bit? > > 20 bits are always page flags > > 21 if you have an MMU > > 23 with the zone bits for DMA, Normal, HighMem, Movable > > 29 with the sparsemem

Re: [PATCH v2 02/12] sched/core: uclamp: map TASK's clamp values into CPU's clamp groups

On 20-Jul 17:25, Suren Baghdasaryan wrote: [...] > > ---8<--- > > > > /* Uclamp flags */ > > #define SCHED_FLAG_UTIL_CLAMP_STRICT0x11 /* Roll-back on failure */ > > #define SCHED_FLAG_UTIL_CLAMP_MIN 0x12 /* Update util_min */ > > #define SCHED_FLAG_UTIL_CLAMP_MAX 0x14 /* Update

[PATCH RESEND] kthread, tracing: Don't expose half-written comm when creating kthreads

There was a window for racing when task->comm was being written. The vsnprintf function writes 16 bytes, then counts the rest, then null terminates. In the meantime, other threads could see the non-terminated comm value. In our case, it got into the trace system's saved cmdlines and could cause

[PATCH 4.4 019/107] x86/cpufeatures: Add CPUID_7_EDX CPUID leaf

4.4-stable review patch. If anyone has any objections, please let me know. -- From: David Woodhouse (cherry picked from commit 95ca0ee8636059ea2800dfbac9ecac6212d6b38f) This is a pure feature bits leaf. There are two AVX512 feature bits in it already which were handled as

[PATCH 4.4 003/107] fat: fix memory allocation failure handling of match_strdup()

4.4-stable review patch. If anyone has any objections, please let me know. -- From: OGAWA Hirofumi commit 35033ab988c396ad7bce3b6d24060c16a9066db8 upstream. In parse_options(), if match_strdup() failed, parse_options() leaves opts->iocharset in unexpected state (i.e. still

[PATCH 4.4 006/107] ARC: mm: allow mprotect to make stack mappings executable

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Vineet Gupta commit 93312b6da4df31e4102ce5420e6217135a16c7ea upstream. mprotect(EXEC) was failing for stack mappings as default vm flags was missing MAYEXEC. This was triggered by glibc test

[PATCH 4.4 018/107] x86/paravirt: Make native_save_fl() extern inline

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Nick Desaulniers commit d0a8d9378d16eb3c69bd8e6d23779fbdbee3a8c7 upstream. native_save_fl() is marked static inline, but by using it as a function pointer in arch/x86/kernel/paravirt.c, it

[PATCH 4.4 000/107] 4.4.144-stable review

This is the start of the stable review cycle for the 4.4.144 release. There are 107 patches in this series, all will be posted as a response to this one. If anyone has any issues with these being applied, please let me know. Responses should be made by Wed Jul 25 12:23:53 UTC 2018. Anything

[PATCH 4.4 049/107] x86/bugs: Concentrate bug detection into a separate function

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Konrad Rzeszutek Wilk commit 4a28bfe3267b68e22c663ac26185aa16c9b879ef upstream Combine the various logic which goes through all those x86_cpu_id matching structures in one function.

[PATCH 4.4 047/107] x86/amd: dont set X86_BUG_SYSRET_SS_ATTRS when running under Xen

4.4-stable review patch. If anyone has any objections, please let me know. -- From: David Woodhouse commit def9331a1290cc6132d79f8e6565871e8e38 upstream When running as Xen pv guest X86_BUG_SYSRET_SS_ATTRS must not be set on AMD cpus. This bug/feature bit is kind of

[PATCH 4.4 034/107] x86/speculation: Fix up array_index_nospec_mask() asm constraint

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Dan Williams commit be3233fbfcb8f5acb6e3bcd0895c3ef9e100d470 upstream. Allow the compiler to handle @size as an immediate value or memory directly rather than allocating a register.

[PATCH 4.4 046/107] xen: set cpu capabilities from xen_start_kernel()

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Juergen Gross Upstream commit: 0808e80cb760de2733c0527d2090ed2205a1eef8 ("xen: set cpu capabilities from xen_start_kernel()") There is no need to set the same capabilities for each cpu

[PATCH 4.4 036/107] x86/xen: Zero MSR_IA32_SPEC_CTRL before suspend

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Juergen Gross commit 71c208dd54ab971036d83ff6d9837bae4976e623 upstream. Older Xen versions (4.5 and before) might have problems migrating pv guests with MSR_IA32_SPEC_CTRL having a non-zero

[PATCH 4.4 005/107] ARC: Fix CONFIG_SWAP

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Alexey Brodkin commit 6e3761145a9ba3ce267c330b6bff51cf6a057b06 upstream. swap was broken on ARC due to silly copy-paste issue. We encode offset from swapcache page in __swp_entry() as (off <<

[PATCH 4.4 066/107] x86/process: Allow runtime control of Speculative Store Bypass

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Thomas Gleixner commit 885f82bfbc6fefb6664ea27965c3ab9ac4194b8c upstream The Speculative Store Bypass vulnerability can be mitigated with the Reduced Data Speculation (RDS) feature. To allow

[PATCH 4.4 101/107] clk: tegra: Fix PLL_U post divider and initial rate on Tegra30

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Lucas Stach commit 797097301860c64b63346d068ba4fe4992bd5021 upstream. The post divider value in the frequency table is wrong as it would lead to the PLL producing an output rate of 960 MHz

[PATCH 4.4 067/107] x86/speculation: Add prctl for Speculative Store Bypass mitigation

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Thomas Gleixner commit a73ec77ee17ec556fe7f165d00314cb7c047b1ac upstream Add prctl based control for Speculative Store Bypass mitigation and make it the default mitigation for Intel and AMD.

[PATCH 4.4 100/107] block: do not use interruptible wait anywhere

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Alan Jenkins commit 1dc3039bc87ae7d19a990c3ee71cfd8a9068f428 upstream. When blk_queue_enter() waits for a queue to unfreeze, or unset the PREEMPT_ONLY flag, do not allow it to be interrupted

Re: INFO: task hung in fuse_reverse_inval_entry

On Mon, Jul 23, 2018 at 2:33 PM, Miklos Szeredi wrote: On Mon, Jul 23, 2018 at 9:59 AM, syzbot wrote: > Hello, > > syzbot found the following crash on: > > HEAD commit:d72e90f33aa4 Linux 4.18-rc6 > git tree: upstream > console output:

[PATCH 4.4 103/107] ubi: Rework Fastmap attach base code

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Richard Weinberger commit fdf10ed710c0aa177e8dfcd84e65e4e5e8e0956b upstream. Introduce a new list to the UBI attach information object to be able to deal better with old and corrupted Fastmap

[PATCH 4.4 084/107] x86/cpufeatures: Disentangle MSR_SPEC_CTRL enumeration from IBRS

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Thomas Gleixner commit 7eb8956a7fec3c1f0abc2a5517dada99ccc8a961 upstream The availability of the SPEC_CTRL MSR is enumerated by a CPUID bit on Intel and implied by IBRS or STIBP support on

[PATCH 4.4 099/107] x86/cpu: Re-apply forced caps every time CPU caps are re-read

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Andy Lutomirski commit 60d3450167433f2d099ce2869dc52dd9e7dc9b29 upstream. Calling get_cpu_cap() will reset a bunch of CPU features. This will cause the system to lose track of force-set and

[PATCH 4.4 086/107] x86/cpu/AMD: Fix erratum 1076 (CPB bit)

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Borislav Petkov commit f7f3dc00f61261cdc9ccd8b886f21bc4dffd6fd9 upstream CPUID Fn8000_0007_EDX[CPB] is wrongly 0 on models up to B1. But they do support CPB (AMD's Core Performance Boosting

[PATCH 4.4 065/107] x86/process: Optimize TIF_NOTSC switch

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Thomas Gleixner commit 5a920155e388ec22a22e0532fb695b9215c9b34d upstream Provide and use a toggle helper instead of doing it with a branch. x86_64: arch/x86/kernel/process.o text data

[PATCH 4.4 025/107] x86/speculation: Add basic IBPB (Indirect Branch Prediction Barrier) support

4.4-stable review patch. If anyone has any objections, please let me know. -- From: David Woodhouse (cherry picked from commit 20ffa1caecca4db8f79fe665acdeaa5af815a24d) Expose indirect_branch_prediction_barrier() for use in subsequent patches. [ tglx: Add IBPB status to

[PATCH 4.4 102/107] ubi: Introduce vol_ignored()

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Richard Weinberger commit 243a4f8126fcf7facb04b324dbb7c85d10b11ce9 upstream. This makes the logic more easy to follow. Signed-off-by: Richard Weinberger Signed-off-by: Greg Kroah-Hartman

[PATCH 4.4 060/107] x86/bugs/AMD: Add support to disable RDS on Fam[15, 16, 17]h if requested

4.4-stable review patch. If anyone has any objections, please let me know. -- From: David Woodhouse commit 764f3c21588a059cd783c6ba0734d4db2d72822d upstream AMD does not need the Speculative Store Bypass mitigation to be enabled. The parameters for this are already available

[PATCH 4.4 081/107] x86/bugs: Fix the parameters alignment and missing void

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Konrad Rzeszutek Wilk commit ffed645e3be0e32f8e9ab068d257aee8d0fe8eec upstream Fixes: 7bb4d366c ("x86/bugs: Make cpu_show_common() static") Fixes: 24f7fc83b ("x86/bugs: Provide boot parameters

[PATCH 4.4 096/107] x86/speculation, KVM: Implement support for VIRT_SPEC_CTRL/LS_CFG

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Thomas Gleixner commit 47c61b3955cf712cadfc25635bf9bc174af030ea upstream Add the necessary logic for supporting the emulated VIRT_SPEC_CTRL MSR to x86_virt_spec_ctrl(). If either

[PATCH 4.4 105/107] ubi: Fix races around ubi_refill_pools()

4.4-stable review patch. If anyone has any objections, please let me know. -- From: Richard Weinberger commit 2e8f08deabbc7eefe4c5838aaa6aa9a23a8acf2e upstream. When writing a new Fastmap the first thing that happens is refilling the pools in memory. At this stage it is

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