On Fri, 10 Aug 2018 11:35:54 -0400
Steven Rostedt wrote:
> Investigating it, it's that when we register more than one event, the
> tracepoint code calls "release_probes" when adding new tracepoints (as
> it updated the tracepoint array), and this is done very early in boot
> up, causing this
Hi,
On Fri, Aug 10, 2018 at 9:29 AM, wrote:
> Here are my couple of cents:
> SPI controller maximum frequency can be lesser than or equal to Clock
> framework's maximum
> frequency, so should not rely on the Clock framework.
You could make that argument on other SoCs perhaps, but from what
On 8/10/18 3:46 AM, Vlastimil Babka wrote:
On 08/10/2018 01:36 AM, Yang Shi wrote:
Unmapping vmas, which have VM_HUGETLB | VM_PFNMAP flag set or
have uprobes set, need get done with write mmap_sem held since
they may update vm_flags.
So, it might be not safe enough to deal with these kind
On Wed, Aug 1, 2018 at 1:33 PM Venkata Narendra Kumar Gutta
wrote:
>
> Cache error reporting controller is to detect and report single
> and double bit errors on Last Level Cache Controller (LLCC) cache.
> Add required support to register LLCC EDAC driver as platform driver,
> from LLCC driver.
>
Am 10.08.2018 um 19:34 schrieb Rob Herring:
> On Sun, Aug 5, 2018 at 5:27 PM Andreas Färber wrote:
>>
>> This is to allow using serdev.
>>
>> Signed-off-by: Andreas Färber
>> ---
>> drivers/tty/serial/sc16is7xx.c | 25 +
>> 1 file changed, 25 insertions(+)
>>
>> diff
On Fri, Aug 10, 2018 at 11:00 PM, Michal Hocko wrote:
> On Fri 10-08-18 16:55:40, Rashmica Gupta wrote:
> [...]
>> Most memory hotplug/hotremove seems to be block or section based, and
>> always adds and removes memory at the same place.
>
> Yes and that is hard wired to the memory hotplug code.
This is another ashmem lockdep splat. Forwarding to the appropriate ashmem
people.
On Fri, Aug 10, 2018 at 04:59:02AM -0700, syzbot wrote:
> Hello,
>
> syzbot found the following crash on:
>
> HEAD commit:4110b42356f3 Add linux-next specific files for 20180810
> git
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On 08/10/2018 07:16 AM, Cornelia Huck wrote:
On Fri, 10 Aug 2018 12:49:08 +0200
Pierre Morel wrote:
On 10/08/2018 11:14, Cornelia Huck wrote:
On Wed, 8 Aug 2018 10:44:27 -0400
Tony Krowiak wrote:
From: Tony Krowiak
Let's call PAPQ(ZAPQ) to zeroize a queue:
* For each queue
Hi Peter,
On 8/8/2018 10:33 AM, Reinette Chatre wrote:
> On 8/8/2018 12:51 AM, Peter Zijlstra wrote:
>> On Tue, Aug 07, 2018 at 03:47:15PM -0700, Reinette Chatre wrote:
- I don't much fancy people accessing the guts of events like that;
would not an inline function like:
The patch
regulator: add QCOM RPMh regulator driver
has been applied to the regulator tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and
The patch
spi: davinci: fix a NULL pointer dereference
has been applied to the spi tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to
From: "Steven Rostedt (VMware)"
When enabling trace events via the kernel command line, I hit this warning:
WARNING: CPU: 0 PID: 13 at kernel/rcu/srcutree.c:236
check_init_srcu_struct+0xe/0x61
Modules linked in:
CPU: 0 PID: 13 Comm: watchdog/0 Not tainted 4.18.0-rc6-test+ #6
Hardware name:
On Thu, Aug 9, 2018 at 12:29 AM Palmer Dabbelt wrote:
>
> On Wed, 08 Aug 2018 16:32:07 PDT (-0700), robh...@kernel.org wrote:
> > On Wed, Aug 8, 2018 at 1:38 PM Palmer Dabbelt wrote:
> >>
> >> On Wed, 08 Aug 2018 07:16:14 PDT (-0700), robh...@kernel.org wrote:
> >> > On Tue, Aug 7, 2018 at 8:17
Em Fri, Aug 10, 2018 at 03:14:01PM +0200, Jiri Olsa escreveu:
> On Fri, Aug 10, 2018 at 09:00:10AM -0400, Steven Rostedt wrote:
> > On Fri, 10 Aug 2018 11:21:37 +0200
> > Jiri Olsa wrote:
> >
> >
> > > > This is not complete. It is only one of many preparations to make
> > > > libtraceevent
Reviewed-by: Rob Springer
On Fri, Aug 10, 2018 at 9:56 AM Rob Springer wrote:
>
> Revewed-by: Rob Springer
>
> On Thu, Aug 9, 2018 at 8:21 PM Todd Poynor wrote:
>>
>> From: Todd Poynor
>>
>> A debug log in gasket_alloc_dev() is issued regardless of whether the
>> device pointer used returned
Add devicetree support for HiKey970 development board which
based on Hi3670 SoC and is also one of the 96Boards Consumer
Edition and AI platform.
Only UART6 is enabled which is the default console required
by the 96Boards Consumer Edition Specification.
This patch has been tested on HiKey970
Add devicetree binding for Hi3670 SoC.
Signed-off-by: Manivannan Sadhasivam
---
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
This patchset adds support for Hi3670 SoC and HiKey970 board. Hi3670 SoC
is very similar to the Hi3660 SoC with additional NPU support. For now,
only UART6 has been enabled which is configured by the bootloader for
console support.
HiKey970 board is one of the 96Boards Consumer Edition and AI
Add initial devicetree support for Hisilicon Hi3670 SoC which
is similar to Hi3660 SoC with NPU support.
This SoC has Octal core BigLittle CPUs in two clusters(4 * A53 & 4 * A73).
Only UART6 has been added for console support which is
pre configured by the bootloader. A fixed clock is sourcing
Add devicetree binding for HiKey970 board.
Signed-off-by: Manivannan Sadhasivam
---
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
Add SDHCI inbound and outbound SDHCI sampling trimmer values for
Tegra186.
Signed-off-by: Aapo Vienamo
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
Add SDHCI inbound and outbound SDHCI sampling trimmer values for
Tegra210.
Signed-off-by: Aapo Vienamo
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
On p2180 sdmmc4 is powered from a fixed 1.8 V regulator.
Signed-off-by: Aapo Vienamo
Reviewed-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
Add pad voltage configuration nodes for sdmmc pads with configurable
voltages on Tegra210.
Signed-off-by: Aapo Vienamo
Reviewed-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git
Set nvquirks to enable higher speed modes.
Signed-off-by: Aapo Vienamo
---
drivers/mmc/host/sdhci-tegra.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 8cfa8f4..2d775ad 100644
---
Add the calibration offset properties used for automatic pad drive
strength calibration.
Signed-off-by: Aapo Vienamo
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
Set SDHCI_QUIRK2_TUNE_SKIP_XFERMODE_REG_PROG on Tegra210 and Tegra186.
This prevents the controller from hanging during tuning. This bug does
not seem to be documented but it's handled in a similar way in the
downstream kernel.
Signed-off-by: Aapo Vienamo
---
drivers/mmc/host/sdhci-tegra.c | 6
Add the calibration offset properties used for automatic pad drive
strength calibration.
Signed-off-by: Aapo Vienamo
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
Add a quirk to disable card clock when the tuning command is sent.
This has to be done to prevent the SDHCI controller from hanging on
Tegra210. Without the quirk enabled there appears to be around 10%
chance that the tuning sequence will fail and time out due to the
controller locking up.
Configure sdmmc4 parent clock to pllc4 and sdmmc1 to pllp_out0 by
setting the assigned-clocks device tree properties. pllc4 offer
better jitter performance and should be used with higher speed
modes like HS200 and HS400.
Signed-off-by: Aapo Vienamo
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi |
Use assigned-clock properties to configure pllc4 as the parent clock
for sdmmc4 on Tegra210. pllc4 offers better jitter perfomance than
the default pllp and is required by HS200 and HS400 modes.
Signed-off-by: Aapo Vienamo
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 8
1 file
Hi Baolin,
On 08/10/2018 05:26 PM, Baolin Wang wrote:
> Hi Jacek,
>
> On 9 August 2018 at 21:21, Jacek Anaszewski
> wrote:
>> Hi Baolin,
>>
>> On 08/09/2018 07:48 AM, Baolin Wang wrote:
>> [...]
>>> +static int pattern_trig_start_pattern(struct pattern_trig_data *data,
>>> +
Your photos need editing. We can do it for you.
We do editing for e-commerce photos, jewelries images and portrait photos
etc.
This will include cutout and clipping path etc , also retouching if needed.
Let;s know if you want to send photos for working.
We can do test on your photos.
Thanks,
Add pad voltage configuration nodes for sdmmc pads with configurable
voltages on Tegra186.
Signed-off-by: Aapo Vienamo
Reviewed-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 40
1 file changed, 40 insertions(+)
diff --git
Set regulator-min-microvolt property of ldo2 to 1.8 V in
tegra210-p2180.dtsi. ldo2 is used by the sdmmc1 SDHCI controller and its
voltage needs to be adjusted down to 1.8 V to support faster signaling
modes. It appears that the comment about the SDHCI driver requesting
invalid voltages no longer
Allow sdmmc1 to set the signaling voltage to 1.8 V in order to support
faster signaling modes.
Signed-off-by: Aapo Vienamo
---
arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
Check for compiler support of -fpatchable-function-entry and use it
to intercept functions immediately on entry, saving the LR in x9.
Disable ftracing in efi/libstub, because this triggers cross-section
linker errors now (-pg used to be disabled already).
Add an ftrace_caller which can handle LR
On Tue, Aug 07, 2018 at 01:27:49PM -0700, Tadeusz Struk wrote:
> Currently the TPM driver only supports blocking calls, which doesn't allow
> asynchronous IO operations to the TPM hardware.
> This patch changes it and adds support for nonblocking write and a new poll
> function to enable
On Fri, Aug 10, 2018 at 07:36:00AM +0800, Yang Shi wrote:
> +static inline bool addr_ok(unsigned long start, size_t len)
Maybe munmap_range_ok()? Otherwise some of the conditions here don't make
sense for such a generic sounding function.
> {
> - unsigned long end;
> - struct
This prevents a possible hardware hang during tuning.
Signed-off-by: Aapo Vienamo
---
drivers/mmc/host/sdhci-tegra.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 3a53593..0959102 100644
---
Add SDHCI_QUIRK2_TUNE_SKIP_XFERRMODE_REG_PROG to skip programming the
SDHCI_TRANSFER_MODE in sdhci_set_transfer_mode() if tuning command is
being sent.
On Tegra210 and Tegra186 the tuning sequence hangs if the SDHCI
transfer mode register is touched.
Signed-off-by: Aapo Vienamo
---
Automatic pad drive strength calibration is performed on a separate pad
identical to the ones used for driving the actual bus. Power on the
calibration pad during the calibration procedure and power it off
afterwards to save power.
Signed-off-by: Aapo Vienamo
Reviewed-by: Mikko Perttunen
---
Parse the default inbound and outbound sampling trimmer values from
the device tree.
Signed-off-by: Aapo Vienamo
---
drivers/mmc/host/sdhci-tegra.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index
Set the default inbound timing adjustment tap value on reset and on
non-tunable modes.
The default tap value is not programmed on tunable modes because the
tuning sequence is used instead to determine the tap value.
Signed-off-by: Aapo Vienamo
---
drivers/mmc/host/sdhci-tegra.c | 132
Parse the pad drive strength calibration offsets from the device tree.
Program the calibration offsets in accordance with the current signaling
mode.
Signed-off-by: Aapo Vienamo
---
drivers/mmc/host/sdhci-tegra.c | 152 -
1 file changed, 151
Run the automatic pad calibration after voltage switching if
tegra_host->pad_calib_required is set.
Signed-off-by: Aapo Vienamo
---
drivers/mmc/host/sdhci-tegra.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index
Disable the card clock during automatic pad drive strength calibration
and re-enable it afterwards.
Signed-off-by: Aapo Vienamo
---
drivers/mmc/host/sdhci-tegra.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/mmc/host/sdhci-tegra.c
Configure the voltage reference used by the automatic pad drive strength
calibration procedure. The value is a magic number from the TRM.
Signed-off-by: Aapo Vienamo
---
drivers/mmc/host/sdhci-tegra.c | 56 +-
1 file changed, 33 insertions(+), 23
Register a pinctrl device and implement get and set functions for
PIN_CONFIG_LOW_POWER_MODE and PIN_CONFIG_POWER_SOURCE parameters.
Signed-off-by: Aapo Vienamo
Acked-by: Jon Hunter
---
drivers/soc/tegra/pmc.c | 187 +++-
1 file changed, 185
Make tegra_io_pad_set_voltage() and tegra_io_pad_get_voltage() static
and remove the prototypes from pmc.h. Remove enum tegra_io_pad_voltage
and use the defines from
instead.
These functions aren't used outside of the pmc driver and new use cases
should use the pinctrl interface instead.
Factor out the the code to calculate the correct DPD register and bit
number for a given pad. This logic will be needed to query the status
register.
Signed-off-by: Aapo Vienamo
Acked-by: Jon Hunter
---
drivers/soc/tegra/pmc.c | 20 +---
1 file changed, 17 insertions(+), 3
Document the Tegra SDHCI inbound and outbound sampling trimmer values.
Signed-off-by: Aapo Vienamo
---
.../devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 11 +++
1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
Parse the pinctrl state and nvidia,only-1-8-v properties from the device
tree. Validate the pinctrl and regulator configuration before unmasking
UHS modes. Implement pad voltage state reconfiguration in the mmc
start_signal_voltage_switch() callback. Add NVQUIRK_NEEDS_PAD_CONTROL
and add set it
Add a new sdhci_ops struct for Tegra210 and Tegra186 which doesn't
set the custom tuning callback used on previous SoC generations.
Signed-off-by: Aapo Vienamo
---
drivers/mmc/host/sdhci-tegra.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git
Set nvquirks to enable higher speed modes.
Signed-off-by: Aapo Vienamo
---
drivers/mmc/host/sdhci-tegra.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 0959102..8cfa8f4 100644
---
Program the outbound sampling trim value in tegra_sdhci_reset(). Unlike
the outbound tap value this does not depend on the signaling mode and
needs to be only programmed once.
Signed-off-by: Aapo Vienamo
---
drivers/mmc/host/sdhci-tegra.c | 7 ++-
1 file changed, 6 insertions(+), 1
Add quirk to disable the card clock during configuration of the tap
value in tegra_sdhci_set_tap() and issue sdhci_reset() after value
change. This is a workaround to avoid propagation of a potential
glitch caused by setting the tap value.
Signed-off-by: Aapo Vienamo
---
Set NVQUIRK_HAS_PADCALIB on Tegra210 and Tegra186 to enable automatic
pad drive strength calibration.
Signed-off-by: Aapo Vienamo
---
drivers/mmc/host/sdhci-tegra.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci-tegra.c
Implement polling with 10 ms timeout for automatic pad drive strength
calibration.
Signed-off-by: Aapo Vienamo
---
drivers/mmc/host/sdhci-tegra.c | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/host/sdhci-tegra.c
On Fri, 10 Aug 2018, Denis Efremov wrote:
> > Do you mean that there is an error in the behavior of coccicheck or that
> > coccicheck finds an error in the source code?
>
> An error in the source code.
>
> Here is an example of how the patch changes the behavior of 'make
> coccicheck' (my
Currently we support only platform data for specifying the interconnect
endpoints. As now the endpoints are hard-coded into the consumer driver
this may lead to complications when a single driver is used by multiple
SoCs, which may have different interconnect topology.
To avoid cluttering the
On some Qualcomm SoCs, there is a remote processor, which controls some of
the Network-On-Chip interconnect resources. Other CPUs express their needs
by communicating with this processor. Add a driver to handle communication
with this remote processor.
Signed-off-by: Georgi Djakov
Reviewed-by:
Note: It is a part time job that won't interrupt your present work or business.
Looking forward to your response.
Best Regards,
Liu Nianzu
HR(Representative Manager)
Beijing Shougang Company Ltd.
No 15,Pingguoyuan Road,Shijingshan District,Beijing
Website: www.sggf.com.cn
Hi,
On Fri, Aug 10, 2018 at 3:52 AM, Mark Brown wrote:
> On Thu, Aug 09, 2018 at 11:03:55AM -0700, Doug Anderson wrote:
>> On Fri, Aug 3, 2018 at 5:18 AM, wrote:
>
>> > Also, spi core framework will set the transfer speed to controller max
>> > frequency
>> > if transfer frequency is greater
On Fri, Aug 10, 2018 at 08:40:17AM -0700, Doug Anderson wrote:
> On Fri, Aug 10, 2018 at 3:52 AM, Mark Brown wrote:
> > This is more about matching the data rate between the two drivers - the
> > clock framework could (and possibly should) reasonably return an error
> > here, we're trying to
On 08/09/2018 01:58 AM, Janosch Frank wrote:
On 08.08.2018 16:44, Tony Krowiak wrote:
From: Tony Krowiak
This patch refactors the code that initializes and sets up the
crypto configuration for a guest. The following changes are
implemented via this patch:
1. Prior to the introduction of AP
Hi,
On Fri, Aug 10, 2018 at 9:13 AM, Mark Brown wrote:
> On Fri, Aug 10, 2018 at 08:40:17AM -0700, Doug Anderson wrote:
>> On Fri, Aug 10, 2018 at 3:52 AM, Mark Brown wrote:
>
>> > This is more about matching the data rate between the two drivers - the
>> > clock framework could (and possibly
On 8/10/18 2:51 AM, Vlastimil Babka wrote:
On 08/10/2018 01:36 AM, Yang Shi wrote:
Unmapping vmas, which have VM_HUGETLB | VM_PFNMAP flag set or
have uprobes set, need get done with write mmap_sem held since
they may update vm_flags.
So, it might be not safe enough to deal with these kind
On Sun, Aug 5, 2018 at 5:27 PM Andreas Färber wrote:
>
> This is to allow using serdev.
>
> Signed-off-by: Andreas Färber
> ---
> drivers/tty/serial/sc16is7xx.c | 25 +
> 1 file changed, 25 insertions(+)
>
> diff --git a/drivers/tty/serial/sc16is7xx.c
Hi all,
with gcc-8 now being out which includes the patchable-function-entries feature,
I can now propose the live patching framework based on it. The series consists
of 3 parts:
1st: Implement ftrace with regs -- uses gcc-8's nop insertions to patch in
ftrace calls.
2nd: "Classic" live
On Fri, Aug 10 2018 at 09:06 -0600, Stephen Boyd wrote:
Quoting Marc Zyngier (2018-08-10 00:45:12)
On Thu, 09 Aug 2018 18:30:53 +0100,
Stephen Boyd wrote:
>
> Quoting Marc Zyngier (2018-08-07 23:26:32)
> >
> > Level interrupts should be taken care of without doing anything, by the
> > very
On Fri, Jul 13, 2018 at 06:50:59PM -0700, David Collins wrote:
> + switch (rpmh_mode) {
> + default:
> + mode = REGULATOR_MODE_INVALID;
> + }
I'm not sure why the break statements are being omitted in default
cases, but I do find myself stopping and trying to figure it
On Fri, 10 Aug 2018 12:30:42 -0400
Steven Rostedt wrote:
Maybe I should say SRCU?
+/* SRCU is initialized at core_initcall */
+postcore_initcall(release_early_probes);
+
static inline void release_probes(struct tracepoint_func *old)
{
if (old) {
struct tp_probes
On Fri, Aug 10, 2018 at 12:30:42PM -0400, Steven Rostedt wrote:
>
> From: "Steven Rostedt (VMware)"
>
> When enabling trace events via the kernel command line, I hit this warning:
>
> WARNING: CPU: 0 PID: 13 at kernel/rcu/srcutree.c:236
> check_init_srcu_struct+0xe/0x61
> Modules linked in:
>
On Wed, Aug 1, 2018 at 1:34 PM Venkata Narendra Kumar Gutta
wrote:
>
> From: Channagoud Kadabi
>
> Add error reporting driver for SBEs and DBEs. As of now, this driver
> supports erp for Last Level Cache Controller (LLCC). This driver takes
> care of dumping registers and adding config options
Just one clarification ...
On 8/10/2018 9:25 AM, Reinette Chatre wrote:
> static inline int x86_perf_event_error_state(struct perf_event *event)
> {
> int ret = 0;
> u64 tmp;
>
> ret = perf_event_read_local(event, , NULL, NULL);
> if (ret < 0)
>
On Fri, Aug 10, 2018 at 5:57 AM Jonathan Corbet wrote:
>
> The objective actually is to have SPDX tags in all files in the kernel.
> That includes documentation, even though people, as always, care less
> about the docs than they do the code.
right, but let's do that as a separate patch set.
In
Document the PMC pinctrl bindings for pad power state and signaling
voltage configuration. Both nvidia,tegra186-pmc.txt and
nvidia,tegra20-pmc.txt are modified as they both cover SoC generations
for which these bindings apply.
Add a header defining Tegra PMC pad voltage configurations.
Hi all,
This series implements support for faster signaling modes on Tegra
SDHCI controllers. This series consist of several parts: changes
requried for 1.8 V signaling and pad control, pad calibration, and
tuning. Following earlies patch sets have been merged into this
larger set: "Tegra PMC
Document the pinctrl bindings used by the SDHCI driver to reconfigure
pad voltages on controllers supporting multiple voltage levels.
Signed-off-by: Aapo Vienamo
Reviewed-by: Mikko Perttunen
Reviewed-by: Rob Herring
---
.../bindings/mmc/nvidia,tegra20-sdhci.txt | 22
On 8/10/2018 7:58 PM, Jerome Brunet wrote:
> On Thu, 2018-08-09 at 16:22 +0800, Jianxin Pan wrote:
>> Try to add basic DT support for the Amlogic's Meson-G12A S905D2 SoC,
>> which describe components as follows: Reserve Memory, CPU, GIC, IRQ,
>> Timer, UART. It's capable of booting up into the
Implement a function to query whether a pad is in deep power down mode.
This is needed by the pinctrl callbacks.
Signed-off-by: Aapo Vienamo
Acked-by: Jon Hunter
---
drivers/soc/tegra/pmc.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/soc/tegra/pmc.c
Refactor the IO pad tables into macro tables so that they can be reused
to generate pinctrl pin descriptors. Also add a name field which is
needed by pinctrl.
Signed-off-by: Aapo Vienamo
---
drivers/soc/tegra/pmc.c | 233 ++--
1 file changed, 127
Add bindings documentation for pad pull up and pull down offset values to be
programmed before executing automatic pad drive strength calibration.
Signed-off-by: Aapo Vienamo
---
.../bindings/mmc/nvidia,tegra20-sdhci.txt | 35 ++
1 file changed, 35 insertions(+)
Implement support for the PMC_IMPL_E_33V_PWR register which replaces
PMC_PWR_DET register interface of the SoC generations preceding
Tegra186. Also add the voltage bit offsets to the tegra186_io_pads[]
table and the AO_HV pad.
Signed-off-by: Aapo Vienamo
Acked-by: Jon Hunter
---
The i82443bxgx_edac driver assigns an invalid negative value when an
unknown DRAM type is detected. Drop the unnecessary '-' that brings
misbehavior.
Fixes: 5a2c675c8919 ("drivers/edac: new i82443bxgz MC driver")
Cc:
Signed-off-by: Takashi Iwai
---
drivers/edac/i82443bxgx_edac.c | 2 +-
1
From: Masayoshi Mizuma
This kernel parameter allows to change the padding used for the physical
memory mapping section when KASLR memory is enabled.
For some systems, the default value, CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING,
is not enough. The option is useful to adjust the padding size to
From: Masayoshi Mizuma
There are some exceptional cases that the padding used for the physical
memory mapping section is not enough.
For example of the cases:
- As Baoquan reported in the following, SGI UV system.
https://lkml.org/lkml/2017/9/7/87
- Each node of physical memory layout has
On 2018-08-10 21:43, Mark Brown wrote:
On Fri, Aug 10, 2018 at 08:40:17AM -0700, Doug Anderson wrote:
On Fri, Aug 10, 2018 at 3:52 AM, Mark Brown
wrote:
> This is more about matching the data rate between the two drivers - the
> clock framework could (and possibly should) reasonably return
Hi,
On Fri, Aug 10, 2018 at 9:43 AM, Mark Brown wrote:
>> IMO the line marked "/* UNNEEDED */" below should be removed:
>
>> ...
>> spi-max-frequency = <5000>; /* UNNEEDED */
>
> This is a line in the device tree (which I agree shouldn't be there),
> not code in the SPI driver?
My
On Fri, Aug 10, 2018 at 09:59:46PM +0530, dk...@codeaurora.org wrote:
> Now the need is, how to communicate the SPI controller maximum frequency to
> SPI core framework?
> Is it by DTSI entry or hardcoding in the SPI controller driver?
If you've got a limit that exists in the IP the hard code it
On Thu, Aug 9, 2018 at 1:19 AM, Icenowy Zheng wrote:
> The bus clocks (AHB/APB) on Allwinner H6 have their second divider start
> at bit 8, according to the user manual and the BSP code. However,
> currently the divider is wrongly set to 16, thus the divider is not
> correctly read and the clock
On Fri, Aug 10, 2018 at 12:35:17PM -0400, Steven Rostedt wrote:
> On Fri, 10 Aug 2018 12:30:42 -0400
> Steven Rostedt wrote:
>
> Maybe I should say SRCU?
That would be an improvement. What, me read comments? ;-)
Thanx, Paul
> +/* SRCU is
Add the HS400 DQS trim value for Tegra210 SDMMC4.
Signed-off-by: Aapo Vienamo
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 14da98a..f8e5f09 100644
---
Add the HS400 DQS trim value for Tegra186 SDMMC4.
Signed-off-by: Aapo Vienamo
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 6e9ef26..9e07bc6 100644
---
Enable HS400 signaling on Tegra186 SDMMC4 controller.
Signed-off-by: Aapo Vienamo
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 9e07bc6..2f3c8e2 100644
Hi all,
This series implements support for HS400 signaling on Tegra210 and
Tegra186. This includes programming the DQS trimmer values, implementing
enhanced strobe and HS400 delay line calibration.
This series depends on the "Tegra SDHCI add support for HS200 and UHS
signaling" series.
Implement eMMC HS400 enhanced strobe. Enhanced strobe is an alternative
mechanism to the HS400 tuning procedure.
Signed-off-by: Aapo Vienamo
---
drivers/mmc/host/sdhci-tegra.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/mmc/host/sdhci-tegra.c
Parse and program the HS400 DQS trim value from DT. Program a fallback
value in case the property is missing.
Signed-off-by: Aapo Vienamo
---
drivers/mmc/host/sdhci-tegra.c | 32 +---
1 file changed, 29 insertions(+), 3 deletions(-)
diff --git
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