[PATCH] perf util: Fix bad memory access in trace info.
From: Chris Phlipot
In the write to the output_fd in the error condition of
record_saved_cmdline(), we are writing 8 bytes from a memory location
on the stack that contains a primitive that is only 4 bytes in size.
Change the primitive to 8 bytes in size to match the size of the write
in order to avoid reading unknown memory from the stack.
Signed-off-by: Chris Phlipot
---
tools/perf/util/trace-event-info.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/perf/util/trace-event-info.c
b/tools/perf/util/trace-event-info.c
index c85d0d1a65ed..7b0ca7cbb7de 100644
--- a/tools/perf/util/trace-event-info.c
+++ b/tools/perf/util/trace-event-info.c
@@ -377,7 +377,7 @@ static int record_ftrace_printk(void)
static int record_saved_cmdline(void)
{
- unsigned int size;
+ unsigned long long size;
char *path;
struct stat st;
int ret, err = 0;
--
2.17.1
Deadlock in md
I have not rebooted my system since recovering my data off of an old
raid5 array with an external journal which broke after a crash in
write-back mode (https://www.spinics.net/lists/raid/msg61331.html) and I
noticed this in my kernel log. I had the array assembled in read-only
mode without a journal. When I was done getting my data, I had stopped
the array and zeroed the first 1GiB of each raid member. After this I
modified the partition tables of the disks, but fdisk reported my
/dev/sdb to be in use by the kernel, as did partprobe, presumably due to
a reference leaked from the deadlock.
This is v4.15.67 with an assortment of debugging features enabled, but I
didn't have kmemleak on because I was copying a lot of files (too many
"soft lockups" when it ran).
[203283.385588] md0: detected capacity change from 8796094070784 to 0
[203283.385610] md: md0 stopped.
[203283.430869] ==
[203283.430870] WARNING: possible circular locking dependency detected
[203283.430872] 4.14.67-gentoo-debug #3 Not tainted
[203283.430873] --
[203283.430875] kworker/13:1/480 is trying to acquire lock:
[203283.430876] (kn->count#82){}, at: []
kernfs_remove+0x1a/0x30
[203283.430883]
but task is already holding lock:
[203283.430885] ((>del_work)){+.+.}, at: []
process_one_work+0x255/0x740
[203283.430889]
which lock already depends on the new lock.
[203283.430891]
the existing dependency chain (in reverse order) is:
[203283.430892]
-> #5 ((>del_work)){+.+.}:
[203283.430896] lock_acquire+0xa6/0x160
[203283.430898] process_one_work+0x2af/0x740
[203283.430900] worker_thread+0x43/0x690
[203283.430902] kthread+0x18f/0x260
[203283.430905] ret_from_fork+0x27/0x50
[203283.430906]
-> #4 ("md_misc"){+.+.}:
[203283.430910] lock_acquire+0xa6/0x160
[203283.430911] flush_workqueue+0xa6/0xa00
[203283.430914] __md_stop_writes+0x19/0x130
[203283.430916] do_md_stop+0x18d/0x700
[203283.430917] md_ioctl+0xcfb/0x2290
[203283.430920] blkdev_ioctl+0x6a8/0x1020
[203283.430922] block_ioctl+0x52/0xa0
[203283.430924] do_vfs_ioctl+0xc4/0x990
[203283.430926] SyS_ioctl+0x91/0xa0
[203283.430928] do_syscall_64+0x83/0x260
[203283.430930] entry_SYSCALL_64_after_hwframe+0x42/0xb7
[203283.430931]
-> #3 (>open_mutex){+.+.}:
[203283.430934] lock_acquire+0xa6/0x160
[203283.430936] __mutex_lock+0x74/0xc60
[203283.430938] md_open+0x6c/0x140
[203283.430939] __blkdev_get+0xce/0x560
[203283.430941] blkdev_get+0x27f/0x500
[203283.430943] do_dentry_open+0x293/0x4c0
[203283.430945] path_openat+0x5a3/0xf30
[203283.430947] do_filp_open+0xb7/0x150
[203283.430948] do_sys_open+0x1d1/0x2c0
[203283.430950] do_syscall_64+0x83/0x260
[203283.430952] entry_SYSCALL_64_after_hwframe+0x42/0xb7
[203283.430953]
-> #2 (>bd_mutex){+.+.}:
[203283.430956] lock_acquire+0xa6/0x160
[203283.430957] __mutex_lock+0x74/0xc60
[203283.430959] __blkdev_get+0x54/0x560
[203283.430960] blkdev_get+0x27f/0x500
[203283.430962] blkdev_get_by_dev+0x38/0x60
[203283.430963] lock_rdev+0x43/0xb0
[203283.430965] md_import_device+0xf7/0x290
[203283.430966] add_new_disk+0xe1/0x782
[203283.430968] md_ioctl+0x1664/0x2290
[203283.430969] blkdev_ioctl+0x6a8/0x1020
[203283.430971] block_ioctl+0x52/0xa0
[203283.430972] do_vfs_ioctl+0xc4/0x990
[203283.430974] SyS_ioctl+0x91/0xa0
[203283.430976] do_syscall_64+0x83/0x260
[203283.430978] entry_SYSCALL_64_after_hwframe+0x42/0xb7
[203283.430978]
-> #1 (>reconfig_mutex){+.+.}:
[203283.430982] lock_acquire+0xa6/0x160
[203283.430983] __mutex_lock+0x74/0xc60
[203283.430985] array_state_store+0xcf/0x4e0
[203283.430986] md_attr_store+0xa5/0x130
[203283.430988] kernfs_fop_write+0x1ad/0x300
[203283.430990] __vfs_write+0x64/0x2c0
[203283.430991] vfs_write+0xf1/0x2e0
[203283.430993] SyS_write+0x4e/0xc0
[203283.430994] do_syscall_64+0x83/0x260
[203283.430996] entry_SYSCALL_64_after_hwframe+0x42/0xb7
[203283.430997]
-> #0 (kn->count#82){}:
[203283.431000] __lock_acquire+0x14c7/0x1c50
[203283.431002] lock_acquire+0xa6/0x160
[203283.431004] __kernfs_remove+0x26d/0x390
[203283.431005] kernfs_remove+0x1a/0x30
[203283.431008] kobject_del.part.0+0x21/0x70
[203283.431010] mddev_delayed_delete+0x1f/0x30
[203283.431012] process_one_work+0x2bc/0x740
[203283.431013] worker_thread+0x43/0x690
[203283.431015] kthread+0x18f/0x260
[203283.431017] ret_from_fork+0x27/0x50
[203283.431018]
other info that might help
Re: [PATCH 10/25] ubifs: add helper functions for authentication support
Hi Richard,
On Mon, Aug 27, 2018 at 02:50:37PM +0200, Richard Weinberger wrote:
> Am Mittwoch, 4. Juli 2018, 14:41:22 CEST schrieb Sascha Hauer:
> > This patch adds the various helper functions needed for authentication
> > support. We need functions to hash nodes, to embed HMACs into a node and
> > to compare hashes and HMACs. Most functions first check if this
> > filesystem is authenticated and bail out early if not, which makes the
> > functions safe to be called with disabled authentication.
> >
> > Signed-off-by: Sascha Hauer
> > ---
> > +void ubifs_prepare_auth_node(struct ubifs_info *c, void *node,
> > +struct shash_desc *inhash)
> > +{
> > + SHASH_DESC_ON_STACK(hash_desc, c->hash_tfm);
> > + struct ubifs_auth_node *auth = node;
> > + u8 hash[crypto_shash_descsize(c->hash_tfm)];
>
> Doesn't this introduce a new VLA?
> Not that me make Kees unhappy. ;-)
/me just read https://lwn.net/Articles/749064/ and now realizes why this
is considered harmful.
Thanks for the review. I'll look into this and all the other points. I
guess that'll keep me busy for some time.
Thanks
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
[PATCH V7 4/9] mmc: sdhci: Add ADMA2 64-bit addressing support for V4 mode
ADMA2 64-bit addressing support is divided into V3 mode and V4 mode.
So there are two kinds of descriptors for ADMA2 64-bit addressing
i.e. 96-bit Descriptor for V3 mode, and 128-bit Descriptor for V4
mode. 128-bit Descriptor is aligned to 8-byte.
For V4 mode, ADMA2 64-bit addressing is enabled via Host Control 2
register.
Signed-off-by: Chunyan Zhang
---
drivers/mmc/host/sdhci.c | 92 +++-
drivers/mmc/host/sdhci.h | 12 +--
2 files changed, 78 insertions(+), 26 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 6fb70da..17345b6 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -266,6 +266,52 @@ static void sdhci_set_default_irqs(struct sdhci_host *host)
sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
}
+static void sdhci_config_dma(struct sdhci_host *host)
+{
+ u8 ctrl;
+ u16 ctrl2;
+
+ if (host->version < SDHCI_SPEC_200)
+ return;
+
+ ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
+
+ /*
+* Always adjust the DMA selection as some controllers
+* (e.g. JMicron) can't do PIO properly when the selection
+* is ADMA.
+*/
+ ctrl &= ~SDHCI_CTRL_DMA_MASK;
+ if (!(host->flags & SDHCI_REQ_USE_DMA))
+ goto out;
+
+ /* Note if DMA Select is zero then SDMA is selected */
+ if (host->flags & SDHCI_USE_ADMA)
+ ctrl |= SDHCI_CTRL_ADMA32;
+
+ if (host->flags & SDHCI_USE_64_BIT_DMA) {
+ /*
+* If v4 mode, all supported DMA can be 64-bit addressing if
+* controller supports 64-bit system address, otherwise only
+* ADMA can support 64-bit addressing.
+*/
+ if (host->v4_mode) {
+ ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ ctrl2 |= SDHCI_CTRL_64BIT_ADDR;
+ sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
+ } else if (host->flags & SDHCI_USE_ADMA) {
+ /*
+* Don't need to undo SDHCI_CTRL_ADMA32 in order to
+* set SDHCI_CTRL_ADMA64.
+*/
+ ctrl |= SDHCI_CTRL_ADMA64;
+ }
+ }
+
+out:
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+}
+
static void sdhci_init(struct sdhci_host *host, int soft)
{
struct mmc_host *mmc = host->mmc;
@@ -913,7 +959,6 @@ static void sdhci_set_timeout(struct sdhci_host *host,
struct mmc_command *cmd)
static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command
*cmd)
{
- u8 ctrl;
struct mmc_data *data = cmd->data;
host->data_timeout = 0;
@@ -1009,25 +1054,7 @@ static void sdhci_prepare_data(struct sdhci_host *host,
struct mmc_command *cmd)
}
}
- /*
-* Always adjust the DMA selection as some controllers
-* (e.g. JMicron) can't do PIO properly when the selection
-* is ADMA.
-*/
- if (host->version >= SDHCI_SPEC_200) {
- ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
- ctrl &= ~SDHCI_CTRL_DMA_MASK;
- if ((host->flags & SDHCI_REQ_USE_DMA) &&
- (host->flags & SDHCI_USE_ADMA)) {
- if (host->flags & SDHCI_USE_64_BIT_DMA)
- ctrl |= SDHCI_CTRL_ADMA64;
- else
- ctrl |= SDHCI_CTRL_ADMA32;
- } else {
- ctrl |= SDHCI_CTRL_SDMA;
- }
- sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
- }
+ sdhci_config_dma(host);
if (!(host->flags & SDHCI_REQ_USE_DMA)) {
int flags;
@@ -3511,6 +3538,19 @@ static int sdhci_allocate_bounce_buffer(struct
sdhci_host *host)
return 0;
}
+static inline bool sdhci_can_64bit_dma(struct sdhci_host *host)
+{
+ /*
+* According to SD Host Controller spec v4.10, bit[27] added from
+* version 4.10 in Capabilities Register is used as 64-bit System
+* Address support for V4 mode.
+*/
+ if (host->version >= SDHCI_SPEC_410 && host->v4_mode)
+ return host->caps & SDHCI_CAN_64BIT_V4;
+
+ return host->caps & SDHCI_CAN_64BIT;
+}
+
int sdhci_setup_host(struct sdhci_host *host)
{
struct mmc_host *mmc;
@@ -3582,7 +3622,7 @@ int sdhci_setup_host(struct sdhci_host *host)
* SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
* implement.
*/
- if (host->caps & SDHCI_CAN_64BIT)
+ if (sdhci_can_64bit_dma(host))
host->flags |= SDHCI_USE_64_BIT_DMA;
if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
@@ -3616,8 +3656,8 @@ int sdhci_setup_host(struct sdhci_host *host)
*/
if
[PATCH V7 6/9] mmc: sdhci: Add Auto CMD Auto Select support
As SD Host Controller Specification v4.10 documents:
Host Controller Version 4.10 defines this "Auto CMD Auto Select" mode.
Selection of Auto CMD depends on setting of CMD23 Enable in the Host
Control 2 register which indicates whether card supports CMD23. If CMD23
Enable =1, Auto CMD23 is used and if CMD23 Enable =0, Auto CMD12 is
used. In case of Version 4.10 or later, use of Auto CMD Auto Select is
recommended rather than use of Auto CMD12 Enable or Auto CMD23
Enable.
This patch add this new mode support.
Signed-off-by: Chunyan Zhang
---
drivers/mmc/host/sdhci.c | 49 ++--
drivers/mmc/host/sdhci.h | 2 ++
2 files changed, 41 insertions(+), 10 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 604bf4c..62d843ac90 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1095,6 +1095,43 @@ static inline bool sdhci_auto_cmd12(struct sdhci_host
*host,
!mrq->cap_cmd_during_tfr;
}
+static inline void sdhci_auto_cmd_select(struct sdhci_host *host,
+struct mmc_command *cmd,
+u16 *mode)
+{
+ bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) &&
+(cmd->opcode != SD_IO_RW_EXTENDED);
+ bool use_cmd23 = cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23);
+ u16 ctrl2;
+
+ /*
+* In case of Version 4.10 or later, use of 'Auto CMD Auto
+* Select' is recommended rather than use of 'Auto CMD12
+* Enable' or 'Auto CMD23 Enable'.
+*/
+ if (host->version >= SDHCI_SPEC_410 && (use_cmd12 || use_cmd23)) {
+ *mode |= SDHCI_TRNS_AUTO_SEL;
+
+ ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ if (use_cmd23)
+ ctrl2 |= SDHCI_CMD23_ENABLE;
+ else
+ ctrl2 &= ~SDHCI_CMD23_ENABLE;
+ sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
+
+ return;
+ }
+
+ /*
+* If we are sending CMD23, CMD12 never gets sent
+* on successful completion (so no Auto-CMD12).
+*/
+ if (use_cmd12)
+ *mode |= SDHCI_TRNS_AUTO_CMD12;
+ else if (use_cmd23)
+ *mode |= SDHCI_TRNS_AUTO_CMD23;
+}
+
static void sdhci_set_transfer_mode(struct sdhci_host *host,
struct mmc_command *cmd)
{
@@ -1123,17 +1160,9 @@ static void sdhci_set_transfer_mode(struct sdhci_host
*host,
if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
- /*
-* If we are sending CMD23, CMD12 never gets sent
-* on successful completion (so no Auto-CMD12).
-*/
- if (sdhci_auto_cmd12(host, cmd->mrq) &&
- (cmd->opcode != SD_IO_RW_EXTENDED))
- mode |= SDHCI_TRNS_AUTO_CMD12;
- else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
- mode |= SDHCI_TRNS_AUTO_CMD23;
+ sdhci_auto_cmd_select(host, cmd, );
+ if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23))
sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
- }
}
if (data->flags & MMC_DATA_READ)
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index f7a1079..4a19ff8 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -42,6 +42,7 @@
#define SDHCI_TRNS_BLK_CNT_EN 0x02
#define SDHCI_TRNS_AUTO_CMD12 0x04
#define SDHCI_TRNS_AUTO_CMD23 0x08
+#define SDHCI_TRNS_AUTO_SEL 0x0C
#define SDHCI_TRNS_READ 0x10
#define SDHCI_TRNS_MULTI 0x20
@@ -185,6 +186,7 @@
#define SDHCI_CTRL_DRV_TYPE_D0x0030
#define SDHCI_CTRL_EXEC_TUNING0x0040
#define SDHCI_CTRL_TUNED_CLK 0x0080
+#define SDHCI_CMD23_ENABLE0x0800
#define SDHCI_CTRL_V4_MODE0x1000
#define SDHCI_CTRL_64BIT_ADDR 0x2000
#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
--
2.7.4
[PATCH V7 8/9] mmc: sdhci-sprd: Add Spreadtrum's initial host controller
From: Chunyan Zhang
This patch adds the initial support of Secure Digital Host Controller
Interface compliant controller found in some latest Spreadtrum chipsets.
This patch has been tested on the version of SPRD-R11 controller.
R11 is a variant based on SD v4.0 specification.
With this driver, R11 mmc can be initialized, can be mounted, read and
written.
Original-by: Billows Wu
Signed-off-by: Chunyan Zhang
---
drivers/mmc/host/Kconfig | 13 ++
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/sdhci-sprd.c | 498 ++
3 files changed, 512 insertions(+)
create mode 100644 drivers/mmc/host/sdhci-sprd.c
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index d09feb6..cf984f0 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -593,6 +593,19 @@ config MMC_SDRICOH_CS
To compile this driver as a module, choose M here: the
module will be called sdricoh_cs.
+config MMC_SDHCI_SPRD
+ tristate "Spreadtrum SDIO host Controller"
+ depends on ARCH_SPRD
+ depends on MMC_SDHCI_PLTFM
+ select MMC_SDHCI_IO_ACCESSORS
+ help
+ This selects the SDIO Host Controller in Spreadtrum
+ SoCs, this driver supports R11(IP version: R11P0).
+
+ If you have a controller with this interface, say Y or M here.
+
+ If unsure, say N.
+
config MMC_TMIO_CORE
tristate
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index a835d1a..5363d06 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -92,6 +92,7 @@ obj-$(CONFIG_MMC_SDHCI_ST)+= sdhci-st.o
obj-$(CONFIG_MMC_SDHCI_MICROCHIP_PIC32)+= sdhci-pic32.o
obj-$(CONFIG_MMC_SDHCI_BRCMSTB)+= sdhci-brcmstb.o
obj-$(CONFIG_MMC_SDHCI_OMAP) += sdhci-omap.o
+obj-$(CONFIG_MMC_SDHCI_SPRD) += sdhci-sprd.o
obj-$(CONFIG_MMC_CQHCI)+= cqhci.o
ifeq ($(CONFIG_CB710_DEBUG),y)
diff --git a/drivers/mmc/host/sdhci-sprd.c b/drivers/mmc/host/sdhci-sprd.c
new file mode 100644
index 000..decd8cd
--- /dev/null
+++ b/drivers/mmc/host/sdhci-sprd.c
@@ -0,0 +1,498 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Secure Digital Host Controller
+//
+// Copyright (C) 2018 Spreadtrum, Inc.
+// Author: Chunyan Zhang
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "sdhci-pltfm.h"
+
+/* SDHCI_ARGUMENT2 register high 16bit */
+#define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16)
+
+#define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208
+#define SDHCIBSPRD_IT_WR_DLY_INV BIT(5)
+#define SDHCI_SPRD_BIT_CMD_DLY_INVBIT(13)
+#define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21)
+#define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29)
+
+#define SDHCI_SPRD_REG_32_BUSY_POSI0x250
+#define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25)
+#define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24)
+
+#define SDHCI_SPRD_REG_DEBOUNCE0x28C
+#define SDHCI_SPRD_BIT_DLL_BAKBIT(0)
+#define SDHCI_SPRD_BIT_DLL_VALBIT(1)
+
+#define SDHCI_SPRD_INT_SIGNAL_MASK0x1B7F410B
+
+/* SDHCI_HOST_CONTROL2 */
+#define SDHCI_SPRD_CTRL_HS200 0x0005
+#define SDHCI_SPRD_CTRL_HS400 0x0006
+
+/*
+ * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is
+ * reserved, and only used on Spreadtrum's design, the hardware cannot work
+ * if this bit is cleared.
+ * 1 : normal work
+ * 0 : hardware reset
+ */
+#define SDHCI_HW_RESET_CARD BIT(3)
+
+#define SDHCI_SPRD_MAX_CUR 0xFF
+#define SDHCI_SPRD_CLK_MAX_DIV 1023
+
+#define SDHCI_SPRD_CLK_DEF_RATE2600
+
+struct sdhci_sprd_host {
+ u32 version;
+ struct clk *clk_sdio;
+ struct clk *clk_enable;
+ u32 base_rate;
+ int flags; /* backup of host attribute */
+};
+
+#define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host))
+
+static void sdhci_sprd_init_config(struct sdhci_host *host)
+{
+ u16 val;
+
+ /* set dll backup mode */
+ val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE);
+ val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL;
+ sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE);
+}
+
+static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg)
+{
+ if (unlikely(reg == SDHCI_MAX_CURRENT))
+ return SDHCI_SPRD_MAX_CUR;
+
+ return readl_relaxed(host->ioaddr + reg);
+}
+
+static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg)
+{
+ /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */
+ if (unlikely(reg == SDHCI_MAX_CURRENT))
+ return;
+
+ if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE))
+ val = val & SDHCI_SPRD_INT_SIGNAL_MASK;
+
+ writel_relaxed(val,
[PATCH V7 5/9] mmc: sdhci: Add 32-bit block count support for v4 mode
Host Controller Version 4.10 re-defines SDMA System Address register
as 32-bit Block Count for v4 mode, and SDMA uses ADMA System
Address register (05Fh-058h) instead if v4 mode is enabled. Also
when using 32-bit block count, 16-bit block count register need
to be set to zero.
Since using 32-bit Block Count would cause problems for auto-cmd23,
it can be chosen via host->quirk2.
Signed-off-by: Chunyan Zhang
---
drivers/mmc/host/sdhci.c | 14 +-
drivers/mmc/host/sdhci.h | 8
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 17345b6..604bf4c 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1073,7 +1073,19 @@ static void sdhci_prepare_data(struct sdhci_host *host,
struct mmc_command *cmd)
/* Set the DMA boundary value and block size */
sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
SDHCI_BLOCK_SIZE);
- sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
+
+ /*
+* For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count
+* can be supported, in that case 16-bit block count register must be 0.
+*/
+ if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
+ (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) {
+ if (sdhci_readw(host, SDHCI_BLOCK_COUNT))
+ sdhci_writew(host, 0, SDHCI_BLOCK_COUNT);
+ sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT);
+ } else {
+ sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
+ }
}
static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index c5cc513..f7a1079 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -28,6 +28,7 @@
#define SDHCI_DMA_ADDRESS 0x00
#define SDHCI_ARGUMENT2SDHCI_DMA_ADDRESS
+#define SDHCI_32BIT_BLK_CNTSDHCI_DMA_ADDRESS
#define SDHCI_BLOCK_SIZE 0x04
#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
@@ -462,6 +463,13 @@ struct sdhci_host {
* obtainable timeout.
*/
#define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT(1<<17)
+/*
+ * 32-bit block count may not support eMMC where upper bits of CMD23 are used
+ * for other purposes. Consequently we support 16-bit block count by default.
+ * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit
+ * block count.
+ */
+#define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18)
int irq;/* Device IRQ */
void __iomem *ioaddr; /* Mapped address */
--
2.7.4
[PATCH V7 9/9] dt-bindings: sdhci-sprd: Add bindings for the sdhci-sprd controller
From: Chunyan Zhang
This patch adds the device-tree binding documentation for Spreadtrum
SDHCI driver.
Signed-off-by: Chunyan Zhang
---
.../devicetree/bindings/mmc/sdhci-sprd.txt | 41 ++
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-sprd.txt
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-sprd.txt
b/Documentation/devicetree/bindings/mmc/sdhci-sprd.txt
new file mode 100644
index 000..45c9978
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/sdhci-sprd.txt
@@ -0,0 +1,41 @@
+* Spreadtrum SDHCI controller (sdhci-sprd)
+
+The Secure Digital (SD) Host controller on Spreadtrum SoCs provides an
interface
+for MMC, SD and SDIO types of cards.
+
+This file documents differences between the core properties in mmc.txt
+and the properties used by the sdhci-sprd driver.
+
+Required properties:
+- compatible: Should contain "sprd,sdhci-r11".
+- reg: physical base address of the controller and length.
+- interrupts: Interrupts used by the SDHCI controller.
+- clocks: Should contain phandle for the clock feeding the SDHCI controller
+- clock-names: Should contain the following:
+ "sdio" - SDIO source clock (required)
+ "enable" - gate clock which used for enabling/disabling the device
(required)
+
+Optional properties:
+- assigned-clocks: the same with "sdio" clock
+- assigned-clock-parents: the default parent of "sdio" clock
+
+Examples:
+
+sdio0: sdio@2060 {
+ compatible = "sprd,sdhci-r11";
+ reg = <0 0x2060 0 0x1000>;
+ interrupts = ;
+
+ clock-names = "sdio", "enable";
+ clocks = <_clk CLK_EMMC_2X>,
+<_gate CLK_EMMC_EB>;
+ assigned-clocks = <_clk CLK_EMMC_2X>;
+ assigned-clock-parents = < CLK_RPLL_390M>;
+
+ bus-width = <8>;
+ non-removable;
+ no-sdio;
+ no-sd;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
--
2.7.4
[PATCH V7 7/9] mmc: sdhci: SDMA may use Auto-CMD23 in v4 mode
When Host Version 4 Enable is set to 1, SDMA uses ADMA System Address
register (05Fh-058h) instead of using register (000h-004h) to indicate
its system address of data location. The register (000h-004h) is
re-assigned to 32-bit Block Count and Auto CMD23 argument, so then SDMA
may use Auto CMD23.
Signed-off-by: Chunyan Zhang
---
drivers/mmc/host/sdhci.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 62d843ac90..ac92e0f 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -3834,10 +3834,14 @@ int sdhci_setup_host(struct sdhci_host *host)
if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
host->flags |= SDHCI_AUTO_CMD12;
- /* Auto-CMD23 stuff only works in ADMA or PIO. */
+ /*
+* For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO;
+* For v4 mode, SDMA may use Auto-CMD23 as well.
+*/
if ((host->version >= SDHCI_SPEC_300) &&
((host->flags & SDHCI_USE_ADMA) ||
-!(host->flags & SDHCI_USE_SDMA)) &&
+(!host->v4_mode && !(host->flags & SDHCI_USE_SDMA)) ||
+(host->v4_mode && (host->flags & SDHCI_USE_SDMA))) &&
!(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
host->flags |= SDHCI_AUTO_CMD23;
DBG("Auto-CMD23 available\n");
--
2.7.4
[PATCH V7 1/9] mmc: sdhci: Add version V4 definition
Added definitions for v400, v410, v420.
Signed-off-by: Chunyan Zhang
---
drivers/mmc/host/sdhci.c | 2 +-
drivers/mmc/host/sdhci.h | 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 97e4efa..01bf88c 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -3508,7 +3508,7 @@ int sdhci_setup_host(struct sdhci_host *host)
override_timeout_clk = host->timeout_clk;
- if (host->version > SDHCI_SPEC_300) {
+ if (host->version > SDHCI_SPEC_420) {
pr_err("%s: Unknown controller version (%d). You may experience
problems.\n",
mmc_hostname(mmc), host->version);
}
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 732d82f..dbd48a8 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -270,6 +270,9 @@
#define SDHCI_SPEC_100 0
#define SDHCI_SPEC_200 1
#define SDHCI_SPEC_300 2
+#define SDHCI_SPEC_400 3
+#define SDHCI_SPEC_410 4
+#define SDHCI_SPEC_420 5
/*
* End of controller registers.
--
2.7.4
[PATCH V7 3/9] mmc: sdhci: Change SDMA address register for v4 mode
According to the SD host controller specification version 4.10, when
Host Version 4 is enabled, SDMA uses ADMA System Address register
(05Fh-058h) instead of using SDMA System Address register to
support both 32-bit and 64-bit addressing.
Signed-off-by: Chunyan Zhang
---
drivers/mmc/host/sdhci.c | 30 --
1 file changed, 20 insertions(+), 10 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 0c61105..6fb70da 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -727,7 +727,7 @@ static void sdhci_adma_table_post(struct sdhci_host *host,
}
}
-static u32 sdhci_sdma_address(struct sdhci_host *host)
+static dma_addr_t sdhci_sdma_address(struct sdhci_host *host)
{
if (host->bounce_buffer)
return host->bounce_addr;
@@ -735,6 +735,17 @@ static u32 sdhci_sdma_address(struct sdhci_host *host)
return sg_dma_address(host->data->sg);
}
+static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr)
+{
+ if (host->v4_mode) {
+ sdhci_writel(host, addr, SDHCI_ADMA_ADDRESS);
+ if (host->flags & SDHCI_USE_64_BIT_DMA)
+ sdhci_writel(host, (u64)addr >> 32,
SDHCI_ADMA_ADDRESS_HI);
+ } else {
+ sdhci_writel(host, addr, SDHCI_DMA_ADDRESS);
+ }
+}
+
static unsigned int sdhci_target_timeout(struct sdhci_host *host,
struct mmc_command *cmd,
struct mmc_data *data)
@@ -994,8 +1005,7 @@ static void sdhci_prepare_data(struct sdhci_host *host,
struct mmc_command *cmd)
SDHCI_ADMA_ADDRESS_HI);
} else {
WARN_ON(sg_cnt != 1);
- sdhci_writel(host, sdhci_sdma_address(host),
-SDHCI_DMA_ADDRESS);
+ sdhci_set_sdma_addr(host, sdhci_sdma_address(host));
}
}
@@ -2830,7 +2840,7 @@ static void sdhci_data_irq(struct sdhci_host *host, u32
intmask)
* some controllers are faulty, don't trust them.
*/
if (intmask & SDHCI_INT_DMA_END) {
- u32 dmastart, dmanow;
+ dma_addr_t dmastart, dmanow;
dmastart = sdhci_sdma_address(host);
dmanow = dmastart + host->data->bytes_xfered;
@@ -2838,12 +2848,12 @@ static void sdhci_data_irq(struct sdhci_host *host, u32
intmask)
* Force update to the next DMA block boundary.
*/
dmanow = (dmanow &
- ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
+ ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1))
+
SDHCI_DEFAULT_BOUNDARY_SIZE;
host->data->bytes_xfered = dmanow - dmastart;
- DBG("DMA base 0x%08x, transferred 0x%06x bytes, next
0x%08x\n",
- dmastart, host->data->bytes_xfered, dmanow);
- sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
+ DBG("DMA base %pad, transferred 0x%06x bytes, next
%pad\n",
+ , host->data->bytes_xfered, );
+ sdhci_set_sdma_addr(host, dmanow);
}
if (intmask & SDHCI_INT_DATA_END) {
@@ -3590,8 +3600,8 @@ int sdhci_setup_host(struct sdhci_host *host)
}
}
- /* SDMA does not support 64-bit DMA */
- if (host->flags & SDHCI_USE_64_BIT_DMA)
+ /* SDMA does not support 64-bit DMA if v4 mode not set */
+ if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode)
host->flags &= ~SDHCI_USE_SDMA;
if (host->flags & SDHCI_USE_ADMA) {
--
2.7.4
[PATCH V7 2/9] mmc: sdhci: Add sd host v4 mode
For SD host controller version 4.00 or later ones, there're two
modes of implementation - Version 3.00 compatible mode or
Version 4 mode. This patch introduced an interface to enable
v4 mode.
Signed-off-by: Chunyan Zhang
---
drivers/mmc/host/sdhci.c | 29 +
drivers/mmc/host/sdhci.h | 3 +++
2 files changed, 32 insertions(+)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 01bf88c..0c61105 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -123,6 +123,29 @@ EXPORT_SYMBOL_GPL(sdhci_dumpregs);
* *
\*/
+static void sdhci_do_enable_v4_mode(struct sdhci_host *host)
+{
+ u16 ctrl2;
+
+ ctrl2 = sdhci_readb(host, SDHCI_HOST_CONTROL2);
+ if (ctrl2 & SDHCI_CTRL_V4_MODE)
+ return;
+
+ ctrl2 |= SDHCI_CTRL_V4_MODE;
+ sdhci_writeb(host, ctrl2, SDHCI_HOST_CONTROL);
+}
+
+/*
+ * This can be called before sdhci_add_host() by Vendor's host controller
+ * driver to enable v4 mode if supported.
+ */
+void sdhci_enable_v4_mode(struct sdhci_host *host)
+{
+ host->v4_mode = true;
+ sdhci_do_enable_v4_mode(host);
+}
+EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode);
+
static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
{
return cmd->data || cmd->flags & MMC_RSP_BUSY;
@@ -252,6 +275,9 @@ static void sdhci_init(struct sdhci_host *host, int soft)
else
sdhci_do_reset(host, SDHCI_RESET_ALL);
+ if (host->v4_mode)
+ sdhci_do_enable_v4_mode(host);
+
sdhci_set_default_irqs(host);
host->cqe_on = false;
@@ -3378,6 +3404,9 @@ void __sdhci_read_caps(struct sdhci_host *host, u16 *ver,
u32 *caps, u32 *caps1)
sdhci_do_reset(host, SDHCI_RESET_ALL);
+ if (host->v4_mode)
+ sdhci_do_enable_v4_mode(host);
+
of_property_read_u64(mmc_dev(host->mmc)->of_node,
"sdhci-caps-mask", _caps_mask);
of_property_read_u64(mmc_dev(host->mmc)->of_node,
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index dbd48a8..61611e3 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -184,6 +184,7 @@
#define SDHCI_CTRL_DRV_TYPE_D0x0030
#define SDHCI_CTRL_EXEC_TUNING0x0040
#define SDHCI_CTRL_TUNED_CLK 0x0080
+#define SDHCI_CTRL_V4_MODE0x1000
#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
#define SDHCI_CAPABILITIES 0x40
@@ -504,6 +505,7 @@ struct sdhci_host {
bool preset_enabled;/* Preset is enabled */
bool pending_reset; /* Cmd/data reset is pending */
bool irq_wake_enabled; /* IRQ wakeup is enabled */
+ bool v4_mode; /* Host Version 4 Enable */
struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */
struct mmc_command *cmd;/* Current command */
@@ -752,6 +754,7 @@ bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask,
int *cmd_error,
int *data_error);
void sdhci_dumpregs(struct sdhci_host *host);
+void sdhci_enable_v4_mode(struct sdhci_host *host);
void sdhci_start_tuning(struct sdhci_host *host);
void sdhci_end_tuning(struct sdhci_host *host);
--
2.7.4
[PATCH V7 0/9] mmc: add support for sdhci 4.0
>From the SD host controller version 4.0 on, SDHCI implementation either is version 3 compatible or version 4 mode. This patch-set covers those changes which are common for SDHCI 4.0 version, regardless of whether they are used with SD or eMMC storage devices. This patchset also added a new sdhci driver for Spreadtrum's controller which supports v4.0 mode. This patchset has been tested on Spreadtrum's mobile phone, emmc can be initialized, mounted, read and written, with these changes for common sdhci framework and sdhci-sprd driver. Changes from V6: - Rebased to the next branch of Ulf' mmc tree; - Replaced SDHCI_QUIRK2_BROKEN_32BIT_BLK_CNT with SDHCI_QUIRK2_USE_32BIT_BLK_CNT, also added a comment to its definition; - Added a 'flags' in sprd_host for recovering host->flags in mmc_host_ops.request. Previous patch series: v6: http://lkml.org/lkml/2018/8/24/205 v5: https://lkml.org/lkml/2018/8/16/122 v4: https://lkml.org/lkml/2018/7/23/269 v3: https://lkml.org/lkml/2018/7/8/239 v2: https://lkml.org/lkml/2018/6/14/936 v1: https://lkml.org/lkml/2018/6/8/108 Chunyan Zhang (9): mmc: sdhci: Add version V4 definition mmc: sdhci: Add sd host v4 mode mmc: sdhci: Change SDMA address register for v4 mode mmc: sdhci: Add ADMA2 64-bit addressing support for V4 mode mmc: sdhci: Add 32-bit block count support for v4 mode mmc: sdhci: Add Auto CMD Auto Select support mmc: sdhci: SDMA may use Auto-CMD23 in v4 mode mmc: sdhci-sprd: Add Spreadtrum's initial host controller dt-bindings: sdhci-sprd: Add bindings for the sdhci-sprd controller .../devicetree/bindings/mmc/sdhci-sprd.txt | 41 ++ drivers/mmc/host/Kconfig | 13 + drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci-sprd.c | 498 + drivers/mmc/host/sdhci.c | 224 +++-- drivers/mmc/host/sdhci.h | 28 +- 6 files changed, 755 insertions(+), 50 deletions(-) create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-sprd.txt create mode 100644 drivers/mmc/host/sdhci-sprd.c -- 2.7.4
Re: [PATCH v1 1/7] extcon: Make static analyzer happy about union assignment
Hi,
On 2018년 08월 28일 00:35, Andy Shevchenko wrote:
> When assign unions we need to supply non-scalar value, otherwise
> static analyzer is not happy:
>
> CHECK drivers/extcon/extcon.c
> drivers/extcon/extcon.c:631:22: warning: cast to non-scalar
>
> Signed-off-by: Andy Shevchenko
> ---
> drivers/extcon/extcon.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/extcon/extcon.c b/drivers/extcon/extcon.c
> index b9d27c8fe57e..c21650a92689 100644
> --- a/drivers/extcon/extcon.c
> +++ b/drivers/extcon/extcon.c
> @@ -628,7 +628,7 @@ int extcon_get_property(struct extcon_dev *edev, unsigned
> int id,
> unsigned long flags;
> int index, ret = 0;
>
> - *prop_val = (union extcon_property_value)(0);
> + *prop_val = (union extcon_property_value){0};
>
> if (!edev)
> return -EINVAL;
>
Applied all patches of this series. Thanks.
--
Best Regards,
Chanwoo Choi
Samsung Electronics
Re: [PATCH v2] x86/dumpstack: don't dump kernel memory based on usermode RIP
On Tue, Aug 28, 2018 at 05:49:01PM +0200, Jann Horn wrote:
> show_opcodes() is used both for dumping kernel instructions and for dumping
> user instructions. If userspace causes #PF by jumping to a kernel address,
> show_opcodes() can be reached with regs->ip controlled by the user,
> pointing to kernel code. Make sure that userspace can't trick us into
> dumping kernel memory into dmesg.
>
> Cc: sta...@vger.kernel.org
> Fixes: 7cccf0725cf7 ("x86/dumpstack: Add a show_ip() function")
> Reviewed-by: Kees Cook
> Signed-off-by: Jann Horn
> ---
> v2: Andy pointed out that I probably shouldn't be doing wrapping
> arithmetic on pointers.
>
> arch/x86/include/asm/stacktrace.h | 2 +-
> arch/x86/kernel/dumpstack.c | 13 ++---
> arch/x86/mm/fault.c | 2 +-
> 3 files changed, 12 insertions(+), 5 deletions(-)
>
> diff --git a/arch/x86/include/asm/stacktrace.h
> b/arch/x86/include/asm/stacktrace.h
> index b6dc698f992a..f335aad404a4 100644
> --- a/arch/x86/include/asm/stacktrace.h
> +++ b/arch/x86/include/asm/stacktrace.h
> @@ -111,6 +111,6 @@ static inline unsigned long caller_frame_pointer(void)
> return (unsigned long)frame;
> }
>
> -void show_opcodes(u8 *rip, const char *loglvl);
> +void show_opcodes(struct pt_regs *regs, const char *loglvl);
> void show_ip(struct pt_regs *regs, const char *loglvl);
> #endif /* _ASM_X86_STACKTRACE_H */
> diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c
> index 9c8652974f8e..14b337582b6f 100644
> --- a/arch/x86/kernel/dumpstack.c
> +++ b/arch/x86/kernel/dumpstack.c
> @@ -89,14 +89,21 @@ static void printk_stack_address(unsigned long address,
> int reliable,
> * Thus, the 2/3rds prologue and 64 byte OPCODE_BUFSIZE is just a random
> * guesstimate in attempt to achieve all of the above.
> */
> -void show_opcodes(u8 *rip, const char *loglvl)
> +void show_opcodes(struct pt_regs *regs, const char *loglvl)
> {
> #define PROLOGUE_SIZE 42
> #define EPILOGUE_SIZE 21
> #define OPCODE_BUFSIZE (PROLOGUE_SIZE + 1 + EPILOGUE_SIZE)
> u8 opcodes[OPCODE_BUFSIZE];
> + u8 *prologue = (u8 *)(regs->ip - PROLOGUE_SIZE);
Just a nitpick:
<--- newline here.
> + /*
> + * Make sure userspace isn't trying to trick us into dumping kernel
> + * memory by pointing the userspace instruction pointer at it.
> + */
> + bool bad_ip = user_mode(regs) &&
> + __range_not_ok(prologue, OPCODE_BUFSIZE, TASK_SIZE_MAX);
Other than that:
Reviewed-by: Borislav Petkov
Thx.
--
Regards/Gruss,
Boris.
SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284
(AG Nürnberg)
--
Re: [PATCH 1/1] axi-i2s: set period size register
Hi, On 27/08/2018 18:51, Lars-Peter Clausen wrote: > On 08/27/2018 06:22 PM, Luca Ceresoli wrote: >> Hi, >> >> thanks for your feedback. >> >> [Adding Michal Simek (Xilinx maintainer) in Cc] >> >> On 27/08/2018 14:27, Lars-Peter Clausen wrote: >>> On 08/24/2018 06:04 PM, Luca Ceresoli wrote: The default value of the PERIOD_LEN register is 0 and results in axi-i2s keeping TLAST always asserted in its AXI Stream output. When the AXI Stream is sent to a Xilinx AXI-DMA, this results in the DMA generating an interrupt flood and ALSA produce a corrupted recording. This is because AXI-DMA raises an interrupt whenever TLAST is active. Fix by setting the PERIOD_LEN register as soon as the period is known. This way TLAST is emitted once per period, and the DMA raises interrupts correctly. >>> >>> The patch looks OK. But I'd prefer not to merge it if possible. >>> >>> We've done some early experiments with the Xilinx AXI-DMA, but it turned out >>> to be to unreliable and we've abandoned support for it. One of the more >>> critical issues was that you can't abort a DMA transfer. That means when >>> audio capture is stopped the DMA will halt, but not complete the current >>> transfer. Then when the next audio capture start the DMA will continue with >>> the previous transfer. The observed effect of this was that the system would >>> just crash randomly (Presumably due to memory corruption). >> >> Strange. I have done many capture experiments with arecord and didn't >> run into such bad issues. I only have a much less serious problem >> (garbage or old samples in the first few buffers), but no crashes. >> >> Michal, are you aware of these problems? >> >>> Have you considered using the ADI AXI-DMAC? That should work just fine. >> >> Not until today, because AXI-DMA is working here. >> >> I'd like to better understand what's going on before changing an IP that >> is working. Do you have additional details about your setup? How do you >> run your tests? > > This was 4-5 years ago. A AXI-DMA with both TX and RX connected to the > AXI-I2S. > > It might be that back then I didn't have buffer prealloc enabled, so a > new DMA buffer gets allocated for each transfer. Then you end up with > use after free and the DMA overwriting freed (and maybe reused) memory. > > It was bad enough that it was a lot easier to add PL330 support to the > I2S peripheral. Not using Xilinx DMA for anything anymore has saved me > from a lot of headache. I kind of understand you. However since AXI-DMA it is working for me with this patch, chances are that bug has been fixed in the meanwhile. -- Luca
Re: [PATCH 0/1] Fix ADI axi-i2s + Xilinx AXI-DMA capture
Hi Mark, On 28/08/2018 20:58, Mark Brown wrote: > On Fri, Aug 24, 2018 at 06:04:29PM +0200, Luca Ceresoli wrote: >> Hi, >> >> here is a fix for a nasty audio capture problem when the axi-i2s >> output stream is fed to a Xilinx AXI-DMA. > > Please don't send cover letters for single patches, if there is anything > that needs saying put it in the changelog of the patch or after the --- > if it's administrative stuff. This reduces mail volume and ensures that > any important information is recorded in the changelog rather than being > lost. OK, will do. Actually I usually do as you suggest, but in this case I thought it deserved a little extra visibility. Sorry about that. -- Luca
[PATCH v2 2/2] iio: adc: sc27xx: Add ADC scale calibration
This patch adds support to read calibration values from the eFuse
controller to calibrate the ADC channel scales, which can make ADC
sample data more accurate.
Signed-off-by: Baolin Wang
---
Changes from v1:
- Use nvmem_cell_read() instead of nvmem_cell_read_u32().
---
.../bindings/iio/adc/sprd,sc27xx-adc.txt |4 ++
drivers/iio/adc/sc27xx_adc.c | 74 +++-
2 files changed, 75 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/iio/adc/sprd,sc27xx-adc.txt
b/Documentation/devicetree/bindings/iio/adc/sprd,sc27xx-adc.txt
index 8aad960..b4daa15 100644
--- a/Documentation/devicetree/bindings/iio/adc/sprd,sc27xx-adc.txt
+++ b/Documentation/devicetree/bindings/iio/adc/sprd,sc27xx-adc.txt
@@ -12,6 +12,8 @@ Required properties:
- interrupts: The interrupt number for the ADC device.
- #io-channel-cells: Number of cells in an IIO specifier.
- hwlocks: Reference to a phandle of a hwlock provider node.
+- nvmem-cells: A phandle to the calibration cells provided by eFuse device.
+- nvmem-cell-names: Should be "big_scale_calib", "small_scale_calib".
Example:
@@ -32,5 +34,7 @@ Example:
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
#io-channel-cells = <1>;
hwlocks = < 4>;
+ nvmem-cells = <_big_scale>, <_small_scale>;
+ nvmem-cell-names = "big_scale_calib",
"small_scale_calib";
};
};
diff --git a/drivers/iio/adc/sc27xx_adc.c b/drivers/iio/adc/sc27xx_adc.c
index 153c311..7940b23 100644
--- a/drivers/iio/adc/sc27xx_adc.c
+++ b/drivers/iio/adc/sc27xx_adc.c
@@ -5,10 +5,12 @@
#include
#include
#include
+#include
#include
#include
#include
#include
+#include
/* PMIC global registers definition */
#define SC27XX_MODULE_EN 0xc08
@@ -87,16 +89,73 @@ struct sc27xx_adc_linear_graph {
* should use the small-scale graph, and if more than 1.2v, we should use the
* big-scale graph.
*/
-static const struct sc27xx_adc_linear_graph big_scale_graph = {
+static struct sc27xx_adc_linear_graph big_scale_graph = {
4200, 3310,
3600, 2832,
};
-static const struct sc27xx_adc_linear_graph small_scale_graph = {
+static struct sc27xx_adc_linear_graph small_scale_graph = {
1000, 3413,
100, 341,
};
+static const struct sc27xx_adc_linear_graph big_scale_graph_calib = {
+ 4200, 856,
+ 3600, 733,
+};
+
+static const struct sc27xx_adc_linear_graph small_scale_graph_calib = {
+ 1000, 833,
+ 100, 80,
+};
+
+static int sc27xx_adc_get_calib_data(u32 calib_data, int calib_adc)
+{
+ return ((calib_data & 0xff) + calib_adc - 128) * 4;
+}
+
+static int sc27xx_adc_scale_calibration(struct sc27xx_adc_data *data,
+ bool big_scale)
+{
+ const struct sc27xx_adc_linear_graph *calib_graph;
+ struct sc27xx_adc_linear_graph *graph;
+ struct nvmem_cell *cell;
+ const char *cell_name;
+ u32 calib_data = 0;
+ void *buf;
+ size_t len;
+
+ if (big_scale) {
+ calib_graph = _scale_graph_calib;
+ graph = _scale_graph;
+ cell_name = "big_scale_calib";
+ } else {
+ calib_graph = _scale_graph_calib;
+ graph = _scale_graph;
+ cell_name = "small_scale_calib";
+ }
+
+ cell = nvmem_cell_get(data->dev, cell_name);
+ if (IS_ERR(cell))
+ return PTR_ERR(cell);
+
+ buf = nvmem_cell_read(cell, );
+ nvmem_cell_put(cell);
+
+ if (IS_ERR(buf))
+ return PTR_ERR(buf);
+
+ memcpy(_data, buf, min(len, sizeof(u32)));
+
+ /* Only need to calibrate the adc values in the linear graph. */
+ graph->adc0 = sc27xx_adc_get_calib_data(calib_data, calib_graph->adc0);
+ graph->adc1 = sc27xx_adc_get_calib_data(calib_data >> 8,
+ calib_graph->adc1);
+
+ kfree(buf);
+ return 0;
+}
+
static int sc27xx_adc_get_ratio(int channel, int scale)
{
switch (channel) {
@@ -209,7 +268,7 @@ static void sc27xx_adc_volt_ratio(struct sc27xx_adc_data
*data,
*div_denominator = ratio & SC27XX_RATIO_DENOMINATOR_MASK;
}
-static int sc27xx_adc_to_volt(const struct sc27xx_adc_linear_graph *graph,
+static int sc27xx_adc_to_volt(struct sc27xx_adc_linear_graph *graph,
int raw_adc)
{
int tmp;
@@ -390,6 +449,15 @@ static int sc27xx_adc_enable(struct sc27xx_adc_data *data)
if (ret)
goto disable_clk;
+ /* ADC channel scales' calibration from nvmem device */
+ ret = sc27xx_adc_scale_calibration(data, true);
+ if (ret)
+ goto disable_clk;
+
+ ret = sc27xx_adc_scale_calibration(data, false);
+ if (ret)
+ goto disable_clk;
+
return 0;
disable_clk:
--
Re: [PATCH] autofs - fix autofs_sbi() does not check super block type
On Mon, 2018-08-27 at 02:03 +0100, Al Viro wrote:
> On Mon, Aug 20, 2018 at 04:37:09PM +0800, Ian Kent wrote:
> > The autofs_sbi() inline function does not check the super block
> > magic number to verify it has been given an autofs super block.
>
> IMO it's the wrong way to fix it. The one and only caller where that
> check might trigger is
>
> if (!fp) {
> if (cmd == AUTOFS_DEV_IOCTL_ISMOUNTPOINT_CMD)
> goto cont;
> err = -EBADF;
> goto out;
> }
>
> sbi = autofs_dev_ioctl_sbi(fp);
> if (!sbi || sbi->magic != AUTOFS_SBI_MAGIC) {
> err = -EINVAL;
> fput(fp);
> goto out;
> }
> with
> static struct autofs_sb_info *autofs_dev_ioctl_sbi(struct file *f)
> {
> struct autofs_sb_info *sbi = NULL;
> struct inode *inode;
>
> if (f) {
> inode = file_inode(f);
> sbi = autofs_sbi(inode->i_sb);
> }
> return sbi;
> }
>
> First of all, what is that `if (f)' doing in there? We have just checked
> that in the only caller.
>
> Next, dereferencing the result of autofs_sbi() does need to be preceded
> by making sure that superblock is autofs one, all right... and what are
> we doing in that first dereferencing, again?
>
> IOW, turn that into
>
> if (!fp) {
>
> goto out;
> }
> sb = file_inode(fp)->i_sb;
> if (sb->s_type != _fs_type)
> bugger off
> sbi = autofs_sbi(sb);
>
>
> and be done with that. Other callers of autofs_sbi() really shouldn't
> happen to other filesystem's superblocks...
Yes, adding it to the inline does add a little extra for other
callers that won't get a non-autofs super block.
I was tempted to just change autofs_dev_ioctl_sbi() in case other
callers were added but your suggestion is somewhat simpler and
really only requires due attention if changes are made.
I'll send a patch to Andrew based on what you recommend.
Thanks
Ian
Re: [PATCH] dt-binding: arm/cpus.txt: fix dynamic-power-coefficient unit
On Tue, 28 Aug 2018 at 16:42, Punit Agrawal wrote: > > Vincent Guittot writes: > > > Hi Amit, > > > > On Wed, 22 Aug 2018 at 12:11, Punit Agrawal wrote: > >> > >> Hi Vincent, > >> > >> Thanks for the patch. One comment about the choice of units below. > >> > >> Vincent Guittot writes: > >> > >> > The unit of dynamic-power-coefficient is described as mW/MHz/uV^2 whereas > >> > its usage in the code assumes that unit is mW/GHz/V^2 > >> > >> Instead of choosing GHz as the base, I'd prefer to use uW/MHz/V^2. It'll > >> avoid introducing fractional GHz value for frequency calculations. > > > > I don't understand your concern about fractional Ghz value for > > frequency calculation ? > > I mean, why it's a problem for frequency with Ghz vs Mhz but not a > > problem for voltage with V vs mV ? > > Don't we have the same "problem" in both case ? > > You're right. It's the same problem in both cases. > > >> > >> > In drivers/thermal/cpu_cooling.c, the code is : > >> > > >> > power = (u64)capacitance * freq_mhz * voltage_mv * voltage_mv; > >> > do_div(power, 10); > >> > > >> > which can be summarized as : > >> > power (mW) = capacitance * freq_mhz/1000 * (voltage_mv/1000)^2 > >> > >> Which would then translate to - > >> > >> power (mW) = power (uW) / 1000 = capacitance * freq_mhz * > >> (voltage_mv/1000)^2 > > > > Not sure that the equation above is correct. If we consider uW/MHz/V^2 > > for the unit, the equation becomes : > > power (mW) = power (uW) / 1000 = capacitance * freq_mhz * > > (voltage_mv/1000)^2 / 1000 > > Yes, I missed the "/ 1000" at the end. > > > which can be rearranged as > > power (mW) = power (uW) / 1000 = capacitance * freq_mhz/ 1000 * > > (voltage_mv/1000)^2 > > > > TBH, I don't really mind between mW/GHz/V^2 or uW/MHz/V^2 as they are > > the same at the end > > but I don't catch your reasoning > > The problem I was thinking of doesn't hold as it's the same issue with > voltage. > > One benefit to go with uW/MHz/V^2 might be the extra resolution that it > provides. I'd prefer to go with uW/MHz/V^2 if there's no compelling > reason to go with anything else. Ok, I'm going to update the patch with uW/MHz/V^2 Thanks > > > [...] > > >> > > >> > Furthermore, if we test basic values like : > >> > voltage_mv = 1000mV = 1V > >> > freq_mhz = 1000Mhz = 1Ghz > >> > > >> > The minimum possible power, when dynamic-power-coefficient equals 1, will > >> > be : > >> > min power = 1 * 1000 * (100)^2 = 10^15 mW > >> > which is not realistic > >> > > >> > With the unit used by the code, the min power is > >> > min power = 1 * 1 * 1^2 = 1mW which is far more realistic > >> > > >> > Signed-off-by: Vincent Guittot > >> > --- > >> > Documentation/devicetree/bindings/arm/cpus.txt | 4 ++-- > >> > 1 file changed, 2 insertions(+), 2 deletions(-) > >> > > >> > diff --git a/Documentation/devicetree/bindings/arm/cpus.txt > >> > b/Documentation/devicetree/bindings/arm/cpus.txt > >> > index 29e1dc5..0148d7d 100644 > >> > --- a/Documentation/devicetree/bindings/arm/cpus.txt > >> > +++ b/Documentation/devicetree/bindings/arm/cpus.txt > >> > @@ -274,7 +274,7 @@ described below. > >> > Usage: optional > >> > Value type: > >> > Definition: A u32 value that represents the running time > >> > dynamic > >> > - power coefficient in units of mW/MHz/uV^2. The > >> > + power coefficient in units of mW/GHz/V^2. The > >> > coefficient can either be calculated from power > >> > measurements or derived by analysis. > >> > > >> > @@ -285,7 +285,7 @@ described below. > >> > > >> > Pdyn = dynamic-power-coefficient * V^2 * f > >> > > >> > - where voltage is in uV, frequency is in MHz. > >> > + where voltage is in V, frequency is in GHz. > >> > > >> > Example 1 (dual-cluster big.LITTLE system 32-bit):
[PATCH]] kvm: selftests: use -pthread instead of -lpthread
I run into the following error testing/selftests/kvm/dirty_log_test.c:285: undefined reference to `pthread_create' testing/selftests/kvm/dirty_log_test.c:297: undefined reference to `pthread_join' collect2: error: ld returned 1 exit status my gcc version is gcc version 4.8.4 "-pthread" would work everywhere Signed-off-by: Lei Yang --- tools/testing/selftests/kvm/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile index 03b0f55..48c970c 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -20,7 +20,7 @@ INSTALL_HDR_PATH = $(top_srcdir)/usr LINUX_HDR_PATH = $(INSTALL_HDR_PATH)/include/ LINUX_TOOL_INCLUDE = $(top_srcdir)tools/include CFLAGS += -O2 -g -std=gnu99 -I$(LINUX_TOOL_INCLUDE) -I$(LINUX_HDR_PATH) -Iinclude -I$(
Re: [PATCH] binder: use standard functions to allocate fds
> config ANDROID_BINDER_IPC > bool "Android Binder IPC Driver" > - depends on MMU > + depends on MMU && !CPU_CACHE_VIVT Thats is a purely arm specific symbol which should not be used in common code. Nevermind that there generally should be no good reason for it. > + fixup->offset = (uintptr_t)fdp - (uintptr_t)t->buffer->data; This looks completely broken. Why would you care at what exact place the fd is placed? Oh, because you share an array with fds with userspace, which is a hell of a bad idea, and then maninpulate that buffer mapped to userspace from kernel threads. I think we just need to rm -rf drivers/android/binder*.c and be done with it, as this piece of crap should never have been merged to start with.
[PATCH v2 1/2] iio: adc: sc27xx: Add raw data support
The headset device will use channel 20 of ADC controller to detect events,
but it needs the raw ADC data to do conversion according to its own formula.
Thus we should configure the channel mask separately and configure channel
20 as IIO_CHAN_INFO_RAW, as well as adding raw data read support.
Signed-off-by: Baolin Wang
---
Changes from v1:
- None.
---
drivers/iio/adc/sc27xx_adc.c | 80 --
1 file changed, 45 insertions(+), 35 deletions(-)
diff --git a/drivers/iio/adc/sc27xx_adc.c b/drivers/iio/adc/sc27xx_adc.c
index 2b60efe..153c311 100644
--- a/drivers/iio/adc/sc27xx_adc.c
+++ b/drivers/iio/adc/sc27xx_adc.c
@@ -273,6 +273,17 @@ static int sc27xx_adc_read_raw(struct iio_dev *indio_dev,
int ret, tmp;
switch (mask) {
+ case IIO_CHAN_INFO_RAW:
+ mutex_lock(_dev->mlock);
+ ret = sc27xx_adc_read(data, chan->channel, scale, );
+ mutex_unlock(_dev->mlock);
+
+ if (ret)
+ return ret;
+
+ *val = tmp;
+ return IIO_VAL_INT;
+
case IIO_CHAN_INFO_PROCESSED:
mutex_lock(_dev->mlock);
ret = sc27xx_adc_read_processed(data, chan->channel, scale,
@@ -315,48 +326,47 @@ static int sc27xx_adc_write_raw(struct iio_dev *indio_dev,
.write_raw = _adc_write_raw,
};
-#define SC27XX_ADC_CHANNEL(index) {\
+#define SC27XX_ADC_CHANNEL(index, mask) { \
.type = IIO_VOLTAGE,\
.channel = index, \
- .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |\
- BIT(IIO_CHAN_INFO_SCALE), \
+ .info_mask_separate = mask | BIT(IIO_CHAN_INFO_SCALE), \
.datasheet_name = "CH##index", \
.indexed = 1, \
}
static const struct iio_chan_spec sc27xx_channels[] = {
- SC27XX_ADC_CHANNEL(0),
- SC27XX_ADC_CHANNEL(1),
- SC27XX_ADC_CHANNEL(2),
- SC27XX_ADC_CHANNEL(3),
- SC27XX_ADC_CHANNEL(4),
- SC27XX_ADC_CHANNEL(5),
- SC27XX_ADC_CHANNEL(6),
- SC27XX_ADC_CHANNEL(7),
- SC27XX_ADC_CHANNEL(8),
- SC27XX_ADC_CHANNEL(9),
- SC27XX_ADC_CHANNEL(10),
- SC27XX_ADC_CHANNEL(11),
- SC27XX_ADC_CHANNEL(12),
- SC27XX_ADC_CHANNEL(13),
- SC27XX_ADC_CHANNEL(14),
- SC27XX_ADC_CHANNEL(15),
- SC27XX_ADC_CHANNEL(16),
- SC27XX_ADC_CHANNEL(17),
- SC27XX_ADC_CHANNEL(18),
- SC27XX_ADC_CHANNEL(19),
- SC27XX_ADC_CHANNEL(20),
- SC27XX_ADC_CHANNEL(21),
- SC27XX_ADC_CHANNEL(22),
- SC27XX_ADC_CHANNEL(23),
- SC27XX_ADC_CHANNEL(24),
- SC27XX_ADC_CHANNEL(25),
- SC27XX_ADC_CHANNEL(26),
- SC27XX_ADC_CHANNEL(27),
- SC27XX_ADC_CHANNEL(28),
- SC27XX_ADC_CHANNEL(29),
- SC27XX_ADC_CHANNEL(30),
- SC27XX_ADC_CHANNEL(31),
+ SC27XX_ADC_CHANNEL(0, BIT(IIO_CHAN_INFO_PROCESSED)),
+ SC27XX_ADC_CHANNEL(1, BIT(IIO_CHAN_INFO_PROCESSED)),
+ SC27XX_ADC_CHANNEL(2, BIT(IIO_CHAN_INFO_PROCESSED)),
+ SC27XX_ADC_CHANNEL(3, BIT(IIO_CHAN_INFO_PROCESSED)),
+ SC27XX_ADC_CHANNEL(4, BIT(IIO_CHAN_INFO_PROCESSED)),
+ SC27XX_ADC_CHANNEL(5, BIT(IIO_CHAN_INFO_PROCESSED)),
+ SC27XX_ADC_CHANNEL(6, BIT(IIO_CHAN_INFO_PROCESSED)),
+ SC27XX_ADC_CHANNEL(7, BIT(IIO_CHAN_INFO_PROCESSED)),
+ SC27XX_ADC_CHANNEL(8, BIT(IIO_CHAN_INFO_PROCESSED)),
+ SC27XX_ADC_CHANNEL(9, BIT(IIO_CHAN_INFO_PROCESSED)),
+ SC27XX_ADC_CHANNEL(10, BIT(IIO_CHAN_INFO_PROCESSED)),
+ SC27XX_ADC_CHANNEL(11, BIT(IIO_CHAN_INFO_PROCESSED)),
+ SC27XX_ADC_CHANNEL(12, BIT(IIO_CHAN_INFO_PROCESSED)),
+ SC27XX_ADC_CHANNEL(13, BIT(IIO_CHAN_INFO_PROCESSED)),
+ SC27XX_ADC_CHANNEL(14, BIT(IIO_CHAN_INFO_PROCESSED)),
+ SC27XX_ADC_CHANNEL(15, BIT(IIO_CHAN_INFO_PROCESSED)),
+ SC27XX_ADC_CHANNEL(16, BIT(IIO_CHAN_INFO_PROCESSED)),
+ SC27XX_ADC_CHANNEL(17, BIT(IIO_CHAN_INFO_PROCESSED)),
+ SC27XX_ADC_CHANNEL(18, BIT(IIO_CHAN_INFO_PROCESSED)),
+ SC27XX_ADC_CHANNEL(19, BIT(IIO_CHAN_INFO_PROCESSED)),
+ SC27XX_ADC_CHANNEL(20, BIT(IIO_CHAN_INFO_RAW)),
+ SC27XX_ADC_CHANNEL(21, BIT(IIO_CHAN_INFO_PROCESSED)),
+ SC27XX_ADC_CHANNEL(22, BIT(IIO_CHAN_INFO_PROCESSED)),
+ SC27XX_ADC_CHANNEL(23, BIT(IIO_CHAN_INFO_PROCESSED)),
+ SC27XX_ADC_CHANNEL(24, BIT(IIO_CHAN_INFO_PROCESSED)),
+ SC27XX_ADC_CHANNEL(25, BIT(IIO_CHAN_INFO_PROCESSED)),
+ SC27XX_ADC_CHANNEL(26, BIT(IIO_CHAN_INFO_PROCESSED)),
+ SC27XX_ADC_CHANNEL(27, BIT(IIO_CHAN_INFO_PROCESSED)),
+ SC27XX_ADC_CHANNEL(28, BIT(IIO_CHAN_INFO_PROCESSED)),
+ SC27XX_ADC_CHANNEL(29, BIT(IIO_CHAN_INFO_PROCESSED)),
+ SC27XX_ADC_CHANNEL(30, BIT(IIO_CHAN_INFO_PROCESSED)),
+ SC27XX_ADC_CHANNEL(31,
Re: [PATCH 1/4] iio: gyro: add support for fxas21002c
On Mon, 2018-08-27 at 18:08 +0100, Jonathan Cameron wrote:
> On Sat, 25 Aug 2018 22:19:07 +0100
> Afonso Bordado wrote:
>
> > FXAS21002C is a 3 axis gyroscope with integrated temperature sensor
> >
> > Signed-off-by: Afonso Bordado
>
> Hi,
>
> Driver is pretty clean so only a few minor comments inline.
> If we were late in a cycle I'd probably just have taken it and fixed
> up
> but as we have lots of time and I'm inherently lazy I'll let you do a
> v2 :)
>
> Good job, thanks!
>
> Jonathan
Great!
> > +
> > +static const struct regmap_access_table fxas21002c_volatile_table
> > = {
> > + .yes_ranges = fxas21002c_volatile_ranges,
> > + .n_yes_ranges = ARRAY_SIZE(fxas21002c_volatile_ranges),
> > +};
> > +
> > +const struct regmap_config fxas21002c_regmap_config = {
> > + .reg_bits = 8,
> > + .val_bits = 8,
> > +
> > + .max_register = FXAS21002C_REG_CTRL_REG3,
> > + // We don't specify a .rd_table because everything is readable
>
> /* ... */
>
> Please run checkpatch as IIRC it complains about this.
I've replaced all instances of C99 comments with ANSI comments.
However, has Joe Perches mentioned. Checkpatch did not warn me about
this.
> > + .wr_table = _writable_table,
> > + .volatile_table = _volatile_table,
> > +};
> > +EXPORT_SYMBOL(fxas21002c_regmap_config);
> > +
> > +#define FXAS21002C_GYRO_CHAN(_axis) {
> > \
> > + .type = IIO_ANGL_VEL,
> > \
> > + .modified = 1,
> > \
> > + .channel2 = IIO_MOD_ ## _axis,
> > \
> > + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
> > \
> > + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
> > \
> > + BIT(IIO_CHAN_INFO_SAMP_FREQ), \
> > + .address = FXAS21002C_REG_OUT_ ## _axis ## _MSB,\
> > +}
> > +
> > +static const struct iio_chan_spec fxas21002c_channels[] = {
> > + {
> > + .type = IIO_TEMP,
> > + .address = FXAS21002C_REG_TEMP,
> > + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
>
> As it currently stands it is IIO_CHAN_PROCESSED but I'd prefer you
> provided
> the scale and kept it as _RAW.
Changed in v2. I'll provide scale + raw.
> > + },
> > + FXAS21002C_GYRO_CHAN(X),
> > + FXAS21002C_GYRO_CHAN(Y),
> > + FXAS21002C_GYRO_CHAN(Z),
> > + IIO_CHAN_SOFT_TIMESTAMP(3),
> > +};
> > +
> > +static int fxas21002c_set_operating_mode(struct fxas21002c_data
> > *data,
> > +enum fxas21002c_operating_mode
> > om)
> > +{
> > + int ret;
> > + int mask = 0;
>
> Might be clearer to not set this here and...
> > +
> > + switch (om) {
> > + case FXAS21002C_OM_STANDBY:
>
> mask = 0;
> > + break;
> > + case FXAS21002C_OM_READY:
> > + mask |= FXAS21002C_READY_BIT;
>
> mask = FXA210002C_READY_BIT;
> > + break;
> > + case FXAS21002C_OM_ACTIVE:
> > + mask |= FXAS21002C_ACTIVE_BIT;
>
> mask = FXA21002C_ACTIVE_BIT;
>
> Slightly more readable I think...
I Agree.
> > +static int fxas21002c_read_oneshot(struct fxas21002c_data *data,
> > + struct iio_chan_spec const *chan,
> > int *val)
> > +{
> > + int ret;
> > + int raw;
> > + __be16 bulk_raw;
> > +
> > + switch (chan->type) {
> > + case IIO_ANGL_VEL:
> > + ret = regmap_bulk_read(data->regmap, chan->address,
> > + _raw, sizeof(bulk_raw));
> > + if (ret)
> > + return ret;
> > +
> > + *val = sign_extend32(be16_to_cpu(bulk_raw), 15);
> > + break;
>
> return IIO_VAL_INT directly here.
Sure
> > + case IIO_TEMP:
> > + ret = regmap_read(data->regmap, chan->address, );
> > + if (ret)
> > + return ret;
> > +
> > + *val = raw * 1000; // Convert to millicelsius
>
> Don't use c++ style comments in kernel code please.
>
> Also I wouldn't do this multiplier in here, I'd provide the scale
> attribute.
> The reason is that we may later have support for buffered reads from
> this
> device - at that point we will want to have nice 8 bit data rather
> than having
> a scaled value that isn't quite a whole number of bits.
This makes sense, I'll put in the SCALE bit for temp.
> > + break;
>
> return IIO_VAL_INT; directly here.
> > + default:
> > + return -EINVAL;
> > + }
> > +
>
> With the above two changes in place this return is never reached.
Changed in v2.
> > + return IIO_VAL_INT;
> > +}
> > +
> > +static int fxas21002c_read_raw(struct iio_dev *indio_dev,
> > + struct iio_chan_spec const *chan, int
> > *val,
> > + int *val2, long mask)
> > +{
> > + struct fxas21002c_data *data = iio_priv(indio_dev);
> > +
> > + switch (mask) {
> >
Re: [PATCH 2/4] iio: gyro: add device tree support for fxas21002c
On Mon, 2018-08-27 at 18:13 +0100, Jonathan Cameron wrote: > On Sat, 25 Aug 2018 22:19:08 +0100 > Afonso Bordado wrote: > > > This patch adds device tree support for the fxas21002c driver, > > including > > bindings. > > > > Signed-off-by: Afonso Bordado > > Now, the devicetree bindings should not reflect just what the driver > uses right now, but rather describe the hardware. > > There are interrupts on there for starters that definitely want to be > described from the start. Also there is a reset line that should > probably > be here from the start. > > Potentially also the two power supplies though that's less critical > (nice to have though) > > It is also an i2c and spi part though that can probably be added > later as > we can argue we are only documenting the bindings for the device in > i2c mode > for now. > > So what is here is fine, but I think we need to describe more. > > It's all well understood details of how it is connected so no need to > have tested it with a driver to be sure it will be right. > > Jonathan Ok, so i'm thinking about adding both interrupts, the reset line and the regulators. If i say they are optional in the device tree document, i shouldn't need to add any more code immediately and could just implement support for it later right?
[PATCH] spi: tegra20-slink: explicitly enable/disable clock
From: Marcel Ziswiler
Depending on the SPI instance one may get an interrupt storm upon
requesting resp. interrupt unless the clock is explicitly enabled
beforehand. This has been observed trying to bring up instance 4 on
T20.
Signed-off-by: Marcel Ziswiler
---
drivers/spi/spi-tegra20-slink.c | 31 +++
1 file changed, 23 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c
index 6f7b946b5ced..1427f343b39a 100644
--- a/drivers/spi/spi-tegra20-slink.c
+++ b/drivers/spi/spi-tegra20-slink.c
@@ -1063,6 +1063,24 @@ static int tegra_slink_probe(struct platform_device
*pdev)
goto exit_free_master;
}
+ /* disabled clock may cause interrupt storm upon request */
+ tspi->clk = devm_clk_get(>dev, NULL);
+ if (IS_ERR(tspi->clk)) {
+ ret = PTR_ERR(tspi->clk);
+ dev_err(>dev, "Can not get clock %d\n", ret);
+ goto exit_free_master;
+ }
+ ret = clk_prepare(tspi->clk);
+ if (ret < 0) {
+ dev_err(>dev, "Clock prepare failed %d\n", ret);
+ goto exit_free_master;
+ }
+ ret = clk_enable(tspi->clk);
+ if (ret < 0) {
+ dev_err(>dev, "Clock enable failed %d\n", ret);
+ goto exit_free_master;
+ }
+
spi_irq = platform_get_irq(pdev, 0);
tspi->irq = spi_irq;
ret = request_threaded_irq(tspi->irq, tegra_slink_isr,
@@ -1071,14 +1089,7 @@ static int tegra_slink_probe(struct platform_device
*pdev)
if (ret < 0) {
dev_err(>dev, "Failed to register ISR for IRQ %d\n",
tspi->irq);
- goto exit_free_master;
- }
-
- tspi->clk = devm_clk_get(>dev, NULL);
- if (IS_ERR(tspi->clk)) {
- dev_err(>dev, "can not get clock\n");
- ret = PTR_ERR(tspi->clk);
- goto exit_free_irq;
+ goto exit_clk_disable;
}
tspi->rst = devm_reset_control_get_exclusive(>dev, "spi");
@@ -1138,6 +1149,8 @@ static int tegra_slink_probe(struct platform_device *pdev)
tegra_slink_deinit_dma_param(tspi, true);
exit_free_irq:
free_irq(spi_irq, tspi);
+exit_clk_disable:
+ clk_disable(tspi->clk);
exit_free_master:
spi_master_put(master);
return ret;
@@ -1150,6 +1163,8 @@ static int tegra_slink_remove(struct platform_device
*pdev)
free_irq(tspi->irq, tspi);
+ clk_disable(tspi->clk);
+
if (tspi->tx_dma_chan)
tegra_slink_deinit_dma_param(tspi, false);
--
2.14.4
Re: [PATCH v2 02/18] clk: intel: Add clock driver for Intel MIPS SoCs
On 8/28/2018 3:09 AM, Stephen Boyd wrote:
Quoting yixin zhu (2018-08-08 01:52:20)
On 8/8/2018 1:50 PM, Stephen Boyd wrote:
Quoting Songjun Wu (2018-08-02 20:02:21)
+ struct clk *clk;
+ int idx;
+
+ for (idx = 0; idx < nr_clks; idx++, osc++) {
+ if (!osc->dt_freq ||
+ of_property_read_u32(ctx->np, osc->dt_freq, ))
+ freq = osc->def_rate;
+
+ clk = clk_register_fixed_rate(NULL, osc->name, NULL, 0, freq);
Should come from DT itself.
Yes. It can be defined as fixed-clock node in device tree.
Do you mean it should be defined in device tree and driver reference it
via device tree?
Yes the oscillator should be in DT and then the DT node here can call
clk_get() or just hardcode the parent name to be what it knows it is.
Eventually we'd like to be able to move away from string names for
hierarchy descriptions but that's far off. To get there, we would need
DT nodes for clock controllers to indicate their clk parents with the
clocks and clock-names properties. So for the oscillator, DT would
define it and then the driver would eventually have a way to specify
that some parent is index 5 or clock name "foo" and then the clk core
could figure out the linkage. I haven't written that code yet, but I'll
probably do it soon if nobody beats me to it.
Thanks. Will update.
+/**
+ * struct intel_clk_provider
+ * @map: regmap type base address for register.
+ * @np: device node
+ * @clk_data: array of hw clocks and clk number.
+ */
+struct intel_clk_provider {
+ struct regmap *map;
+ struct device_node *np;
+ struct clk_onecell_data clk_data;
Please register clk_hw pointers instead of clk pointers with the of
provider APIs.
Sorry. I'm not sure I understand you correctly.
If only registering clk_hw pointer, not registering of_provider API, then
how to reference it in the user drivers ?
Could you please give me more hints ?
Clk provider drivers shouldn't be using clk pointers directly. Usually
when that happens something is wrong. So new clk drivers should register
clk_hw pointers and pretty much only deal with clk_hw pointers instead
of struct clk pointers. You still register an of_provider, but that
provider hands out clk_hw pointers so that clk provider drivers aren't
tempted to use struct clk pointers.
Understood. Will update to use clk_hw_onecell_data and change the
registration accordingly.
+ */
+struct intel_pll_clk {
+ unsigned intid;
+ const char *name;
+ const char *const *parent_names;
+ u8 num_parents;
Can the PLL have multiple parents?
Yes. But not in this platform.
The define here make it easy to expand to support new platform.
Ok, so it has a mux inside.
+ unsigned intid;
+ enum intel_clk_type type;
+ const char *name;
+ const char *const *parent_names;
+ u8 num_parents;
+ unsigned long flags;
+ unsigned intmux_off;
+ u8 mux_shift;
+ u8 mux_width;
+ unsigned long mux_flags;
+ unsigned intmux_val;
+ unsigned intdiv_off;
+ u8 div_shift;
+ u8 div_width;
+ unsigned long div_flags;
+ unsigned intdiv_val;
+ const struct clk_div_table *div_table;
+ unsigned intgate_off;
+ u8 gate_shift;
+ unsigned long gate_flags;
+ unsigned intgate_val;
+ unsigned intmult;
+ unsigned intdiv;
+};
+
+/* clock flags definition */
+#define CLOCK_FLAG_VAL_INITBIT(16)
+#define GATE_CLK_HWBIT(17)
+#define GATE_CLK_SWBIT(18)
+#define GATE_CLK_VTBIT(19)
What does VT mean? Virtual?
Yes. VT means virtual here.
Will change to GATE_CLK_VIRT.
Is it a hardware concept? Or virtualization with hypervisor?
Some peripheral drivers want to use same code cross platforms.
But not all platforms provide HW gate clock. So in this case, clock
driver creates
a virtual gate clock to make it work if no HW gate clock in the SoC.
+}
+
+CLK_OF_DECLARE(intel_grx500_cgu, "intel,grx500-cgu", grx500_clk_init);
Any reason a platform driver can't be used instead of CLK_OF_DECLARE()?
It provides CPU clock which is used in early boot stage.
Ok. What is the CPU clock doing in early boot stage? Some sort of timer
frequency? If the driver can be split into two pieces, one to handle the
really early stuff that must be in place to get timers up and running
and the other to
[PATCH] ARM: configs: add generic resistive touchscreen
Add generic resistive touchscreen CONFIG_TOUCHSCREEN_ADC to defconfigs Signed-off-by: Eugen Hristev --- arch/arm/configs/multi_v7_defconfig | 1 + arch/arm/configs/sama5_defconfig| 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index fc33444..a1b2cfa 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -282,6 +282,7 @@ CONFIG_MOUSE_PS2_ELANTECH=y CONFIG_MOUSE_CYAPA=m CONFIG_MOUSE_ELAN_I2C=y CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADC=m CONFIG_TOUCHSCREEN_ATMEL_MXT=m CONFIG_TOUCHSCREEN_MMS114=m CONFIG_TOUCHSCREEN_WM97XX=m diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig index 2080025..ead6826 100644 --- a/arch/arm/configs/sama5_defconfig +++ b/arch/arm/configs/sama5_defconfig @@ -116,6 +116,7 @@ CONFIG_KEYBOARD_QT1070=y CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADC=y CONFIG_TOUCHSCREEN_ATMEL_MXT=y # CONFIG_SERIO is not set CONFIG_LEGACY_PTY_COUNT=4 -- 2.7.4
[PATCH v2] dt-binding: arm/cpus.txt: fix dynamic-power-coefficient unit
The unit of dynamic-power-coefficient is described as mW/MHz/uV^2 whereas its usage in the code assumes that unit is uW/MHz/V^2 In drivers/thermal/cpu_cooling.c, the code is : power = (u64)capacitance * freq_mhz * voltage_mv * voltage_mv; do_div(power, 10); which can be summarized as : power (mW) = capacitance * freq_mhz/1000 * (voltage_mv/1000)^2 or power (mW) = (capacitance * freq_mhz * (voltage_mv/1000)^2) / 1000 then power (mW) = power (uW) / 1000 so power (uW) = capacitance * freq_mhz * (voltage_mv/1000)^2 Furthermore, if we test basic values like : voltage_mv = 1000mV = 1V freq_mhz = 1000Mhz The minimum possible power, when dynamic-power-coefficient equals 1, will be with current unit: min power = 1 * 1000 * (100)^2 = 10^15 mW which is not realistic With the unit used by the code, the min power is min power = 1 * 1000 * 1^2 = 1000uW = 1mW which is far more realistic Signed-off-by: Vincent Guittot --- Documentation/devicetree/bindings/arm/cpus.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 29e1dc5..71d8cd0 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -274,7 +274,7 @@ described below. Usage: optional Value type: Definition: A u32 value that represents the running time dynamic - power coefficient in units of mW/MHz/uV^2. The + power coefficient in units of uW/MHz/V^2. The coefficient can either be calculated from power measurements or derived by analysis. @@ -285,7 +285,7 @@ described below. Pdyn = dynamic-power-coefficient * V^2 * f - where voltage is in uV, frequency is in MHz. + where voltage is in V, frequency is in MHz. Example 1 (dual-cluster big.LITTLE system 32-bit): -- 2.7.4
Re: [PATCH v2] x86/dumpstack: don't dump kernel memory based on usermode RIP
On Tue, Aug 28, 2018 at 06:29:43PM +0200, Jann Horn wrote: > No, you can also get user opcode bytes printed by WARN() and friends. > When you add a WARN() in the pagefault handler, you get something like Ok, let's always do the checking then - who knows in what context we might be dumping opcodes so we better be prepared. Thx. -- Regards/Gruss, Boris. SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg) --
Re: [PATCH v2 1/3] arm64: implement ftrace with regs
On Fri, Aug 17, 2018 at 12:27:24PM +0200, Torsten Duwe wrote: > Check for compiler support of -fpatchable-function-entry and use it > to intercept functions immediately on entry, saving the LR in x9. > Disable ftracing in efi/libstub, because this triggers cross-section > linker errors now (-pg is disabled already for those files). > Add an ftrace_caller which can handle LR in x9, as well as an I think that we have a bit detailed descriptions about what a function's initial prologue looks like and how it will be patched to enable or disable ftrace on that function for the sake of better understandings. (in entry-ftrace.S or ftrace.c?) > ftrace_regs_caller that additionally writes out a set of pt_regs > for inspection. > > Signed-off-by: Torsten Duwe > > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -110,6 +110,7 @@ config ARM64 > select HAVE_DEBUG_KMEMLEAK > select HAVE_DMA_CONTIGUOUS > select HAVE_DYNAMIC_FTRACE > + select HAVE_DYNAMIC_FTRACE_WITH_REGS > select HAVE_EFFICIENT_UNALIGNED_ACCESS > select HAVE_FTRACE_MCOUNT_RECORD > select HAVE_FUNCTION_TRACER > --- a/arch/arm64/Makefile > +++ b/arch/arm64/Makefile > @@ -78,6 +78,15 @@ ifeq ($(CONFIG_ARM64_MODULE_PLTS),y) > KBUILD_LDFLAGS_MODULE+= -T $(srctree)/arch/arm64/kernel/module.lds > endif > > +ifdef CONFIG_DYNAMIC_FTRACE_WITH_REGS > + CC_FLAGS_FTRACE := -fpatchable-function-entry=2 > + KBUILD_CPPFLAGS += -DCC_USING_PATCHABLE_FUNCTION_ENTRY > + ifeq ($(call cc-option,-fpatchable-function-entry=2),) > +$(error Cannot use CONFIG_DYNAMIC_FTRACE_WITH_REGS: \ > + -fpatchable-function-entry not supported by compiler) > + endif > +endif > + > # Default value > head-y := arch/arm64/kernel/head.o > > --- a/arch/arm64/include/asm/ftrace.h > +++ b/arch/arm64/include/asm/ftrace.h > @@ -16,6 +16,13 @@ > #define MCOUNT_ADDR ((unsigned long)_mcount) > #define MCOUNT_INSN_SIZE AARCH64_INSN_SIZE > > +#ifdef CONFIG_DYNAMIC_FTRACE_WITH_REGS > +#define ARCH_SUPPORTS_FTRACE_OPS 1 > +#define REC_IP_BRANCH_OFFSET 4 Some explanation about "4" will be helpful here. > +#else > +#define REC_IP_BRANCH_OFFSET 0 > +#endif > + > #ifndef __ASSEMBLY__ > #include > > --- a/arch/arm64/kernel/Makefile > +++ b/arch/arm64/kernel/Makefile > @@ -7,9 +7,9 @@ CPPFLAGS_vmlinux.lds := -DTEXT_OFFSET=$( > AFLAGS_head.o:= -DTEXT_OFFSET=$(TEXT_OFFSET) > CFLAGS_armv8_deprecated.o := -I$(src) > > -CFLAGS_REMOVE_ftrace.o = -pg > -CFLAGS_REMOVE_insn.o = -pg > -CFLAGS_REMOVE_return_address.o = -pg > +CFLAGS_REMOVE_ftrace.o = -pg $(CC_FLAGS_FTRACE) > +CFLAGS_REMOVE_insn.o = -pg $(CC_FLAGS_FTRACE) > +CFLAGS_REMOVE_return_address.o = -pg $(CC_FLAGS_FTRACE) You don't need to remove "-pg" explicitly here because it won't be added to XX_CFLAGS when you defines CC_FLAGS_FTRACE. > # Object file lists. > arm64-obj-y := debug-monitors.o entry.o irq.o fpsimd.o > \ > --- a/drivers/firmware/efi/libstub/Makefile > +++ b/drivers/firmware/efi/libstub/Makefile > @@ -11,7 +11,8 @@ cflags-$(CONFIG_X86)+= -m$(BITS) -D__K > -fPIC -fno-strict-aliasing -mno-red-zone \ > -mno-mmx -mno-sse -fshort-wchar > > -cflags-$(CONFIG_ARM64) := $(subst -pg,,$(KBUILD_CFLAGS)) -fpie > +cflags-$(CONFIG_ARM64) := $(filter-out -pg $(CC_FLAGS_FTRACE)\ > + ,$(KBUILD_CFLAGS)) -fpie > cflags-$(CONFIG_ARM) := $(subst -pg,,$(KBUILD_CFLAGS)) \ > -fno-builtin -fpic -mno-single-pic-base > > --- a/arch/arm64/kernel/entry-ftrace.S > +++ b/arch/arm64/kernel/entry-ftrace.S > @@ -13,6 +13,8 @@ > #include > #include > #include > +#include > +#include > > /* > * Gcc with -pg will put the following code in the beginning of each > function: > @@ -123,6 +125,7 @@ skip_ftrace_call: // } > ENDPROC(_mcount) > > #else /* CONFIG_DYNAMIC_FTRACE */ > +#ifndef CC_USING_PATCHABLE_FUNCTION_ENTRY I think that using CONFIG_DYNAMIC_FTRACE_WITH_REG here sounds more consistent. > /* > * _mcount() is used to build the kernel with -pg option, but all the branch > * instructions to _mcount() are replaced to NOP initially at kernel start > up, > @@ -162,6 +165,88 @@ ftrace_graph_call: // > ftrace_graph_cal > > mcount_exit > ENDPROC(ftrace_caller) > +#else /* CC_USING_PATCHABLE_FUNCTION_ENTRY */ > +ENTRY(_mcount) > + mov x10, lr > + mov lr, x9 > + ret x10 > +ENDPROC(_mcount) I don't think we need a definition of _mcount because patchable-function-entry won't generate a call site of _mcount nor other code does. You can simply define MCOUNT_ADDR as ULONG_MAX. > +ENTRY(ftrace_regs_caller) > + stp x29, x9, [sp, #-16]! > + sub sp, sp, #S_FRAME_SIZE > + > + stp x10, x11, [sp, #80] > + stp x12, x13,
Re: [PATCH RESEND 0/7] switch several architectures NO_BOOTMEM
Any updates on this? On Fri, Aug 03, 2018 at 10:58:43PM +0300, Mike Rapoport wrote: > > Hi, > > These patches perform conversion to NO_BOOTMEM of hexagon, nios2, uml and > unicore32. The architecture maintainers have acked the patches, but, since > I've got no confirmation the patches are going through the arch tree I'd > appreciate if the set would be applied to the -mm tree. > > Mike Rapoport (7): > hexagon: switch to NO_BOOTMEM > of: ignore sub-page memory regions > nios2: use generic early_init_dt_add_memory_arch > nios2: switch to NO_BOOTMEM > um: setup_physmem: stop using global variables > um: switch to NO_BOOTMEM > unicore32: switch to NO_BOOTMEM > > arch/hexagon/Kconfig | 3 +++ > arch/hexagon/mm/init.c| 20 +++--- > arch/nios2/Kconfig| 3 +++ > arch/nios2/kernel/prom.c | 17 --- > arch/nios2/kernel/setup.c | 39 ++ > arch/um/Kconfig.common| 2 ++ > arch/um/kernel/physmem.c | 22 +-- > arch/unicore32/Kconfig| 1 + > arch/unicore32/mm/init.c | 54 > +-- > drivers/of/fdt.c | 11 +- > 10 files changed, 41 insertions(+), 131 deletions(-) > > -- > 2.7.4 > -- Sincerely yours, Mike.
Re: [PATCH v2 00/32] Device Tree Updates for GTA04 (A3/A4/A5 variants)
Hi OMAP3 DTS Maintainers, is there any progress in merging this patch series? We have some more patches in our queue which depend on them. BR and thanks, Nikolaus Schaller > Am 31.07.2018 um 09:11 schrieb H. Nikolaus Schaller : > > * Sebastian Reichel > asked why we have reg=<0> for port@1. > Based on his comment we have removed the change for > the opa362 reg property in the DT, but worked out a correct > fix in the opa362 driver which solves the issue better. > See: https://lore.kernel.org/patchwork/patch/968407/ > * Ladislav Michl > has found a typo and we discussed NAND/OneNAND and > how the partitions should be setup. A better solution > would be to do it completely by u-boot, but unless we have > that, we must fix it here. > * we omit the patch that replaces ti,non-removable by non-removable > since additional internal tests have shown that it makes > problems with finding the rootfs boot partition. > * instead we add a patch that explicitly sets broken-cd for mmc1. > > PATCH V1 2018-07-25 09:00:42: > We have not upstreamed significant improvements collected > in the GTA04 vendor kernel tree for some years. The result > is that distribution kernels derived from upstream (e.g. > Debian) lag behind and miss significant features and fixes. > > > H. Nikolaus Schaller (32): > ARM: dts: omap3-gta04: fix typo in backlight pins node name > ARM: dts: omap3-gta04: fix some whitespace and tab style errors > ARM: dts: omap3-gta04: give spi_lcd node a label so that we can >overwrite in other DTS files > ARM: dts: omap3-gta04: fixes for tvout / venc > ARM: dts: omap3-gta04: add devconf1 setup for correct tvout pins > ARM: dts: omap3-gta04: tvout: enable as display1 alias > ARM: dts: omap3-gta04: fix touchscreen tsc2007 > ARM: dts: omap3-gta04: add pinmux for bmp085 EOC interrupt > ARM: dts: omap3-gta04: make NAND partitions compatible with recent >U-Boot > ARM: dts: omap3-gta04: update gpmc NAND setup > ARM: dts: omap3-gta04: keep vpll2 always on > ARM: dts: omap3-gta04: add a comment how to reference the tca6507 gpio > ARM: dts: omap3-gta04: add warning comment to vaux2 regulator > ARM: dts: omap3-gta04: explicitly describe that mmc1 has no CD/WP > ARM: dts: omap3-gta04: make use of input event include file and >constants > ARM: dts: omap3-gta04: map antenna detect GPIO to SW_LINEIN_INSERT key >event > ARM: dts: omap3-gta04: add camera interface parallel port > ARM: dts: omap3-gta04: add camera pinmux > ARM: dts: omap3-gta04: add mcbsp (audio subsystem) pinmux > ARM: dts: omap3-gta04: add devconf0 setup for mcbsp1 clock pins > ARM: dts: omap3-gta04: add mcbsp (audio subsystem) nodes > ARM: dts: omap3-gta04a3: fix model name for A3 variant > ARM: dts: omap3-gta04a4: fix model name for A4 variant > ARM: dts: omap3-gta04a5: fix copyright of A5 variant > ARM: dts: omap3-gta04a5: fix model name > ARM: dts: omap3-gta04a5: fix whitepsace and tab style > ARM: dts: omap3-gta04a5: add support for PPS > ARM: dts: omap3-gta04a5: disable IrDA receiver to save power > ARM: dts: omap3-gta04a5: add support for ti,wl1837 module > ARM: dts: omap3-gta04a5: uses different sensors than gta04a4 > ARM: dts: omap3-gta04a5: define pinmux for bluetooth enable of >ti,wl1837 module > ARM: dts: omap3-gta04a5one: define GTA04A5 variant with OneNAND > > arch/arm/boot/dts/omap3-gta04.dtsi | 248 + > arch/arm/boot/dts/omap3-gta04a3.dts| 2 +- > arch/arm/boot/dts/omap3-gta04a4.dts| 2 +- > arch/arm/boot/dts/omap3-gta04a5.dts| 129 - > arch/arm/boot/dts/omap3-gta04a5one.dts | 114 +++ > 5 files changed, 462 insertions(+), 33 deletions(-) > create mode 100644 arch/arm/boot/dts/omap3-gta04a5one.dts > > -- > 2.12.2 >
Re: [PATCH v2] pinctrl: uniphier: drop meaningless pin from SD1 pin-mux of Pro4
On Sat, Aug 11, 2018 at 4:16 AM Masahiro Yamada wrote: > The pin 327 was supposed to be used as a voltage control line for the > SD card regulator, but the SD card port1 does not support UHS-I. It > only supports 3.3V signaling, hence this pin is pointless. > > Just a note about the background. At first, hardware engineers tried > to implement the UHS for this port. Then, they needed to shrink the > silicon die size, and gave up the UHS, but forgot to remove the pin > assignment. > > Signed-off-by: Masahiro Yamada Patch applied. Yours, Linus Walleij
[PATCH] sched/schedutil : optimize utilization scaling for guest kernel
Scaling the utilization of CPUs with irq util_avg in schedutil doesn't give
any benefit and just waste CPU cycles when irq time is not accounted but
only steal time.
Add an internal _scale_irq_capacity() for scale_rt_capacity but scale
cpu utilization in schedutil only if we are accounting irq time.
Suggested-by: Wanpeng Li
Signed-off-by: Vincent Guittot
---
kernel/sched/fair.c | 2 +-
kernel/sched/sched.h | 22 --
2 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
index 309c93f..c1334be 100644
--- a/kernel/sched/fair.c
+++ b/kernel/sched/fair.c
@@ -7501,7 +7501,7 @@ static unsigned long scale_rt_capacity(int cpu)
free = max - used;
- return scale_irq_capacity(free, irq, max);
+ return _scale_irq_capacity(free, irq, max);
}
static void update_cpu_capacity(struct sched_domain *sd, int cpu)
diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h
index 4a2e8ca..1003d69 100644
--- a/kernel/sched/sched.h
+++ b/kernel/sched/sched.h
@@ -2221,14 +2221,14 @@ static inline unsigned long cpu_util_irq(struct rq *rq)
}
static inline
-unsigned long scale_irq_capacity(unsigned long util, unsigned long irq,
unsigned long max)
+unsigned long _scale_irq_capacity(unsigned long util, unsigned long irq,
unsigned long max)
{
util *= (max - irq);
util /= max;
return util;
-
}
+
#else
static inline unsigned long cpu_util_irq(struct rq *rq)
{
@@ -2236,8 +2236,26 @@ static inline unsigned long cpu_util_irq(struct rq *rq)
}
static inline
+unsigned long _scale_irq_capacity(unsigned long util, unsigned long irq,
unsigned long max)
+{
+ return util;
+}
+#endif
+
+/*
+ * scale_irq_capacity is used by schedutil to scale utilization only when
+ * irq time is accounted. This scaling is not necessary when only virtual time
+ * is accounted as guest doesn't have access to frequency scaling.
+ */
+#ifdef CONFIG_IRQ_TIME_ACCOUNTING
+
+#define scale_irq_capacity _scale_irq_capacity
+
+#else
+static inline
unsigned long scale_irq_capacity(unsigned long util, unsigned long irq,
unsigned long max)
{
return util;
}
#endif
+
--
2.7.4
Re: [BUG] gpio: gpiolib: possible sleep-in-atomic-context bugs in gpiochip_lock_as_irq()
Hi Jia-Ju, Hans Verkuil is working on revamping the IRQ locking API for GPIO, and I think these semantic problems will simply disappear when that is done. Yours, Linus Walleij On Sat, Aug 11, 2018 at 4:22 AM Jia-Ju Bai wrote: > > The driver may sleep with holding a spinlock. > > The function call paths (from bottom to top) in Linux-4.16 are: > > [FUNC] mutex_lock_nested > drivers/gpio/gpio-exar.c, 69: mutex_lock_nested in exar_get > drivers/gpio/gpio-exar.c, 83: exar_get in exar_get_direction > drivers/gpio/gpiolib.c, 3103: [FUNC_PTR]exar_get_direction in > gpiochip_lock_as_irq > drivers/gpio/gpio-tegra.c, 326: gpiochip_lock_as_irq in > tegra_gpio_irq_set_type > kernel/irq/chip.c, 1335: [FUNC_PTR]tegra_gpio_irq_set_type in > irq_chip_set_type_parent > kernel/irq/manage.c, 686: [FUNC_PTR]irq_chip_set_type_parent in > __irq_set_trigger > kernel/irq/manage.c, 1350: __irq_set_trigger in __setup_irq > kernel/irq/manage.c, 1238: _raw_spin_lock_irqsave in __setup_irq > > [FUNC] mutex_lock_nested > drivers/gpio/gpio-pca953x.c, 372: mutex_lock_nested in > pca953x_gpio_get_direction > drivers/gpio/gpiolib.c, 3103: [FUNC_PTR]pca953x_gpio_get_direction in > gpiochip_lock_as_irq > drivers/gpio/gpio-tegra.c, 326: gpiochip_lock_as_irq in > tegra_gpio_irq_set_type > kernel/irq/chip.c, 1335: [FUNC_PTR]tegra_gpio_irq_set_type in > irq_chip_set_type_parent > kernel/irq/manage.c, 686: [FUNC_PTR]irq_chip_set_type_parent in > __irq_set_trigger > kernel/irq/manage.c, 1350: __irq_set_trigger in __setup_irq > kernel/irq/manage.c, 1238: _raw_spin_lock_irqsave in __setup_irq > > [FUNC] mutex_lock_nested > drivers/mfd/stmpe.c, 170: mutex_lock_nested in stmpe_reg_read > drivers/gpio/gpio-stmpe.c, 83: stmpe_reg_read in stmpe_gpio_get_direction > drivers/gpio/gpiolib.c, 3103: [FUNC_PTR]stmpe_gpio_get_direction in > gpiochip_lock_as_irq > drivers/gpio/gpio-tegra.c, 326: gpiochip_lock_as_irq in > tegra_gpio_irq_set_type > kernel/irq/chip.c, 1335: [FUNC_PTR]tegra_gpio_irq_set_type in > irq_chip_set_type_parent > kernel/irq/manage.c, 686: [FUNC_PTR]irq_chip_set_type_parent in > __irq_set_trigger > kernel/irq/manage.c, 1350: __irq_set_trigger in __setup_irq > kernel/irq/manage.c, 1238: _raw_spin_lock_irqsave in __setup_irq > > Note that [FUNC_PTR] means a function pointer call is used. > > I do not find a good way to fix, so I only report. > This is found by my static analysis tool (DSAC). > > > Best wishes, > Jia-Ju Bai
Re: [PATCH v4 07/16] sched/core: uclamp: extend cpu's cgroup controller
On 28-Aug 11:29, Randy Dunlap wrote: > On 08/28/2018 06:53 AM, Patrick Bellasi wrote: > > +config UCLAMP_TASK_GROUP > > + bool "Utilization clamping per group of tasks" > > + depends on CGROUP_SCHED > > + depends on UCLAMP_TASK > > + default n > > + help > > + This feature enables the scheduler to track the clamped utilization > > + of each CPU based on RUNNABLE tasks currently scheduled on that CPU. > > + > > + When this option is enabled, the user can specify a min and max > > + CPU bandwidth which is allowed for each single task in a group. > > + The max bandwidth allows to clamp the maximum frequency a task > > + can use, while the min bandwidth allows to define a minimum > > + frequency a task will always use. > > + > > + When task group based utilization clamping is enabled, an eventually > > + specified task-specific clamp value is constrained by the cgroup > > + specified clamp value. Both minimum and maximum task clamping cannot > > + be bigger than the corresponding clamping defined at task group > > level. > > The 4 lines above should all be indented the same (one tab + 2 spaces). Right... then there's definitively something broken with my vim reformat shortcut, which sometimes uses spaces instead of tabs :( Unfortunately this pattern is not covered by checkpatch, which returns not errors/warnings on this patch. > > + > > + If in doubt, say N. > > + Anyway, thanks for spotting it... easy fix for the next respin. Best, Patrick -- #include Patrick Bellasi
Re: [PATCH] drivers: gpio: gpio-adp5588: Fix sleep-in-atomic-context bug
On Mon, Aug 13, 2018 at 3:53 PM wrote: > From: Michael Hennerich > > This fixes: > [BUG] gpio: gpio-adp5588: A possible sleep-in-atomic-context bug > in adp5588_gpio_write() > [BUG] gpio: gpio-adp5588: A possible sleep-in-atomic-context bug > in adp5588_gpio_direction_input() > > Reported-by: Jia-Ju Bai > Signed-off-by: Michael Hennerich Thanks Michael, excellent and prompt fix. Patch applied for fixes (v4.19-rcs). Should we even tag it for stable? Yours, Linus Walleij
Re: [RFC PATCH 1/6] x86/alternative: assert text_mutex is taken
On Wed, 29 Aug 2018 01:11:42 -0700
Nadav Amit wrote:
> Use lockdep to ensure that text_mutex is taken when text_poke() is
> called.
>
> Actually it is not always taken, specifically when it is called by kgdb,
> so take the lock in these cases.
Can we really take a mutex in kgdb context?
kgdb_arch_remove_breakpoint
<- dbg_deactivate_sw_breakpoints
<- kgdb_reenter_check
<- kgdb_handle_exception
<- __kgdb_notify
<- kgdb_ll_trap
<- do_int3
<- kgdb_notify
<- die notifier
kgdb_arch_set_breakpoint
<- dbg_activate_sw_breakpoints
<- kgdb_reenter_check
<- kgdb_handle_exception
...
Both seems called in exception context, so we can not take a mutex lock.
I think kgdb needs a special path.
Thanks,
>
> Cc: Andy Lutomirski
> Cc: Masami Hiramatsu
> Cc: Kees Cook
> Suggested-by: Peter Zijlstra
> Signed-off-by: Nadav Amit
> ---
> arch/x86/kernel/alternative.c | 1 +
> arch/x86/kernel/kgdb.c| 9 +
> 2 files changed, 10 insertions(+)
>
> diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
> index 014f214da581..916c11b410c4 100644
> --- a/arch/x86/kernel/alternative.c
> +++ b/arch/x86/kernel/alternative.c
> @@ -699,6 +699,7 @@ void *text_poke(void *addr, const void *opcode, size_t
> len)
>* pages as they are not yet initialized.
>*/
> BUG_ON(!after_bootmem);
> + lockdep_assert_held(_mutex);
>
> if (!core_kernel_text((unsigned long)addr)) {
> pages[0] = vmalloc_to_page(addr);
> diff --git a/arch/x86/kernel/kgdb.c b/arch/x86/kernel/kgdb.c
> index 8e36f249646e..60b99c76086c 100644
> --- a/arch/x86/kernel/kgdb.c
> +++ b/arch/x86/kernel/kgdb.c
> @@ -768,8 +768,12 @@ int kgdb_arch_set_breakpoint(struct kgdb_bkpt *bpt)
>*/
> if (mutex_is_locked(_mutex))
> return -EBUSY;
> +
> + /* Take the mutex to avoid lockdep assertion failures. */
> + mutex_lock(_mutex);
> text_poke((void *)bpt->bpt_addr, arch_kgdb_ops.gdb_bpt_instr,
> BREAK_INSTR_SIZE);
> + mutex_unlock(_mutex);
> err = probe_kernel_read(opc, (char *)bpt->bpt_addr, BREAK_INSTR_SIZE);
> if (err)
> return err;
> @@ -793,7 +797,12 @@ int kgdb_arch_remove_breakpoint(struct kgdb_bkpt *bpt)
>*/
> if (mutex_is_locked(_mutex))
> goto knl_write;
> +
> + /* Take the mutex to avoid lockdep assertion failures. */
> + mutex_lock(_mutex);
> text_poke((void *)bpt->bpt_addr, bpt->saved_instr, BREAK_INSTR_SIZE);
> + mutex_unlock(_mutex);
> +
> err = probe_kernel_read(opc, (char *)bpt->bpt_addr, BREAK_INSTR_SIZE);
> if (err || memcmp(opc, bpt->saved_instr, BREAK_INSTR_SIZE))
> goto knl_write;
> --
> 2.17.1
>
--
Masami Hiramatsu
Re: [PATCH] KVM: LAPIC: Fix pv ipis out-of-bounds access
> On 29 Aug 2018, at 8:52, Wanpeng Li wrote:
>
> From: Wanpeng Li
>
> Dan Carpenter reported that the untrusted data returns from
> kvm_register_read()
> results in the following static checker warning:
> arch/x86/kvm/lapic.c:576 kvm_pv_send_ipi()
> error: buffer underflow 'map->phys_map' 's32min-s32max'
>
> KVM guest can easily trigger this by executing the following assembly
> sequence
> in Ring0:
>
> mov $10, %rax
> mov $0x, %rbx
> mov $0x, %rdx
> mov $0, %rsi
> vmcall
>
> As this will cause KVM to execute the following code-path:
> vmx_handle_exit() -> handle_vmcall() -> kvm_emulate_hypercall() ->
> kvm_pv_send_ipi()
> which will reach out-of-bounds access.
>
> This patch fixes it by adding a check to kvm_pv_send_ipi() against
> map->max_apic_id
> and also checking whether or not map->phys_map[min + i] is NULL since the
> max_apic_id
> is set according to the max apic id, however, some phys_map maybe NULL when
> apic id
> is sparse, in addition, kvm also unconditionally set max_apic_id to 255 to
> reserve
> enough space for any xAPIC ID.
>
> Reported-by: Dan Carpenter
> Cc: Paolo Bonzini
> Cc: Radim Krčmář
> Cc: Liran Alon
> Cc: Dan Carpenter
> Signed-off-by: Wanpeng Li
> ---
> arch/x86/kvm/lapic.c | 17 +
> 1 file changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> index 0cefba2..86e933c 100644
> --- a/arch/x86/kvm/lapic.c
> +++ b/arch/x86/kvm/lapic.c
> @@ -571,18 +571,27 @@ int kvm_pv_send_ipi(struct kvm *kvm, unsigned long
> ipi_bitmap_low,
> rcu_read_lock();
> map = rcu_dereference(kvm->arch.apic_map);
>
> + if (unlikely((s32)(map->max_apic_id - __fls(ipi_bitmap_low)) < min))
> + goto out;
I personally think “if ((min + __fls(ipi_bitmap_low)) > map->max_apic_id)” is
more readable.
But that’s just a matter of taste :)
> /* Bits above cluster_size are masked in the caller. */
> for_each_set_bit(i, _bitmap_low, BITS_PER_LONG) {
> - vcpu = map->phys_map[min + i]->vcpu;
> - count += kvm_apic_set_irq(vcpu, , NULL);
> + if (map->phys_map[min + i]) {
> + vcpu = map->phys_map[min + i]->vcpu;
> + count += kvm_apic_set_irq(vcpu, , NULL);
> + }
> }
>
> min += cluster_size;
> + if (unlikely((s32)(map->max_apic_id - __fls(ipi_bitmap_high)) < min))
> + goto out;
> for_each_set_bit(i, _bitmap_high, BITS_PER_LONG) {
> - vcpu = map->phys_map[min + i]->vcpu;
> - count += kvm_apic_set_irq(vcpu, , NULL);
> + if (map->phys_map[min + i]) {
> + vcpu = map->phys_map[min + i]->vcpu;
> + count += kvm_apic_set_irq(vcpu, , NULL);
> + }
> }
>
> +out:
> rcu_read_unlock();
> return count;
> }
> --
> 2.7.4
>
Reviewed-By: Liran Alon
Re: [PATCH] remoteproc: qcom: Rename Hexagon v5 PAS driver
On Mon, Aug 27, 2018 at 10:12:03PM -0700, Bjorn Andersson wrote:
> The Hexagon v5 ADSP driver is used for more than only the ADSP and
> there's an upcoming non-PAS ADSP PIL for SDM845, so rename the driver to
> qcom_q6v5_pas in order to better suite this.
Hello Bjorn,
so I'm a bit new to this, but after your rename we will have:
QCOM_Q6V5_PIL
and
QCOM_Q6V5_PAS
that both are PILs.
I guess that the difference is that the latter uses TrustZone?
The ADSP for some QCOM SoCs is a Hexagon v5, therefore the
QCOM_Q6V5_PAS can also boot certain ADSPs?
But we also have QCOM_Q6V5_WCSS
"Qualcomm Hexagon based WCSS Peripheral Image Loader",
which also appears to be Hexagon v5 based, but I assume that
neither QCOM_Q6V5_PIL nor QCOM_Q6V5_PAS can boot the WCSS?
There is also an upcoming non-PAS ADSP PIL loader for SDM845,
but I guess that the ADSP there is not based on Hexagon v5,
so the QCOM_Q6V5_PIL will not be able to boot it?
This all seems to be quite confusing, perhaps the help texts
could be improved to mitigate this confusion?
>
> Cc: Rohit kumar
> Signed-off-by: Bjorn Andersson
> ---
> drivers/remoteproc/Kconfig| 22 +--
> drivers/remoteproc/Makefile | 2 +-
> .../{qcom_adsp_pil.c => qcom_q6v5_pas.c} | 4 ++--
You should probably also edit the qcom_defconfig:
arch/arm/configs/qcom_defconfig:CONFIG_QCOM_ADSP_PIL=y
> 3 files changed, 14 insertions(+), 14 deletions(-)
> rename drivers/remoteproc/{qcom_adsp_pil.c => qcom_q6v5_pas.c} (98%)
>
> diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
> index 052d4dd347f9..c98c0b2a2237 100644
> --- a/drivers/remoteproc/Kconfig
> +++ b/drivers/remoteproc/Kconfig
> @@ -84,8 +84,16 @@ config KEYSTONE_REMOTEPROC
> It's safe to say N here if you're not interested in the Keystone
> DSPs or just want to use a bare minimum kernel.
>
> -config QCOM_ADSP_PIL
> - tristate "Qualcomm ADSP Peripheral Image Loader"
> +config QCOM_RPROC_COMMON
> + tristate
> +
> +config QCOM_Q6V5_COMMON
> + tristate
> + depends on ARCH_QCOM
> + depends on QCOM_SMEM
> +
> +config QCOM_Q6V5_PAS
> + tristate "Qualcomm Hexagon v5 Peripheral Authentication Service support"
> depends on OF && ARCH_QCOM
> depends on QCOM_SMEM
> depends on RPMSG_QCOM_SMD || (COMPILE_TEST && RPMSG_QCOM_SMD=n)
> @@ -98,15 +106,7 @@ config QCOM_ADSP_PIL
> select QCOM_SCM
> help
> Say y here to support the TrustZone based Peripherial Image Loader
Since you are editing this help text, yoy may just as well
s/Peripherial/Peripheral.
Kind regards,
Niklas
> - for the Qualcomm ADSP remote processors.
> -
> -config QCOM_RPROC_COMMON
> - tristate
> -
> -config QCOM_Q6V5_COMMON
> - tristate
> - depends on ARCH_QCOM
> - depends on QCOM_SMEM
> + for the Qualcomm Hexagon v5 based remote processors.
>
> config QCOM_Q6V5_PIL
> tristate "Qualcomm Hexagon V5 Peripherial Image Loader"
> diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
> index 03332fa7e2ee..eb86c8ba5a87 100644
> --- a/drivers/remoteproc/Makefile
> +++ b/drivers/remoteproc/Makefile
> @@ -14,9 +14,9 @@ obj-$(CONFIG_OMAP_REMOTEPROC) +=
> omap_remoteproc.o
> obj-$(CONFIG_WKUP_M3_RPROC) += wkup_m3_rproc.o
> obj-$(CONFIG_DA8XX_REMOTEPROC) += da8xx_remoteproc.o
> obj-$(CONFIG_KEYSTONE_REMOTEPROC)+= keystone_remoteproc.o
> -obj-$(CONFIG_QCOM_ADSP_PIL) += qcom_adsp_pil.o
> obj-$(CONFIG_QCOM_RPROC_COMMON) += qcom_common.o
> obj-$(CONFIG_QCOM_Q6V5_COMMON) += qcom_q6v5.o
> +obj-$(CONFIG_QCOM_Q6V5_PAS) += qcom_q6v5_pas.o
> obj-$(CONFIG_QCOM_Q6V5_PIL) += qcom_q6v5_pil.o
> obj-$(CONFIG_QCOM_Q6V5_WCSS) += qcom_q6v5_wcss.o
> obj-$(CONFIG_QCOM_SYSMON)+= qcom_sysmon.o
> diff --git a/drivers/remoteproc/qcom_adsp_pil.c
> b/drivers/remoteproc/qcom_q6v5_pas.c
> similarity index 98%
> rename from drivers/remoteproc/qcom_adsp_pil.c
> rename to drivers/remoteproc/qcom_q6v5_pas.c
> index d4339a6da616..2478ef3cd519 100644
> --- a/drivers/remoteproc/qcom_adsp_pil.c
> +++ b/drivers/remoteproc/qcom_q6v5_pas.c
> @@ -364,11 +364,11 @@ static struct platform_driver adsp_driver = {
> .probe = adsp_probe,
> .remove = adsp_remove,
> .driver = {
> - .name = "qcom_adsp_pil",
> + .name = "qcom_q6v5_pas",
> .of_match_table = adsp_of_match,
> },
> };
>
> module_platform_driver(adsp_driver);
> -MODULE_DESCRIPTION("Qualcomm MSM8974/MSM8996 ADSP Peripherial Image Loader");
> +MODULE_DESCRIPTION("Qualcomm Hexagon v5 Peripheral Authentication Service
> driver");
> MODULE_LICENSE("GPL v2");
> --
> 2.18.0
>
Re: [RFC PATCH 5/6] x86/alternatives: use temporary mm for text poking
On Wed, Aug 29, 2018 at 01:11:46AM -0700, Nadav Amit wrote:
> +static void text_poke_fixmap(void *addr, const void *opcode, size_t len,
> + struct page *pages[2])
> +{
> + u8 *vaddr;
> +
> + set_fixmap(FIX_TEXT_POKE0, page_to_phys(pages[0]));
> + if (pages[1])
> + set_fixmap(FIX_TEXT_POKE1, page_to_phys(pages[1]));
> + vaddr = (u8 *)fix_to_virt(FIX_TEXT_POKE0);
> + memcpy(vaddr + offset_in_page(addr), opcode, len);
> +
> + /*
> + * clear_fixmap() performs a TLB flush, so no additional TLB
> + * flush is needed.
> + */
> + clear_fixmap(FIX_TEXT_POKE0);
> + if (pages[1])
> + clear_fixmap(FIX_TEXT_POKE1);
> + sync_core();
> + /* Could also do a CLFLUSH here to speed up CPU recovery; but
> +that causes hangs on some VIA CPUs. */
Please take this opportunity to fix that comment style.
> +}
> +
> +__ro_after_init struct mm_struct *poking_mm;
> +__ro_after_init unsigned long poking_addr;
> +
> +/**
> + * text_poke_safe() - Pokes the text using a separate address space.
> + *
> + * This is the preferable way for patching the kernel after boot, as it does
> not
> + * allow other cores to accidentally or maliciously modify the code using the
> + * temporary PTEs.
> + */
> +static void text_poke_safe(void *addr, const void *opcode, size_t len,
> +struct page *pages[2])
> +{
> + temporary_mm_state_t prev;
> + pte_t pte, *ptep;
> + spinlock_t *ptl;
> +
> + /*
> + * The lock is not really needed, but this allows to avoid open-coding.
> + */
> + ptep = get_locked_pte(poking_mm, poking_addr, );
> +
> + pte = mk_pte(pages[0], PAGE_KERNEL);
> + set_pte_at(poking_mm, poking_addr, ptep, pte);
> +
> + if (pages[1]) {
> + pte = mk_pte(pages[1], PAGE_KERNEL);
> + set_pte_at(poking_mm, poking_addr + PAGE_SIZE, ptep + 1, pte);
> + }
> +
> + /*
> + * Loading the temporary mm behaves as a compiler barrier, which
> + * guarantees that the PTE will be set at the time memcpy() is done.
> + */
> + prev = use_temporary_mm(poking_mm);
> +
> + memcpy((u8 *)poking_addr + offset_in_page(addr), opcode, len);
> +
> + /*
> + * Ensure that the PTE is only cleared after copying is done by using a
> + * compiler barrier.
> + */
> + barrier();
I tripped over the use of 'done', because even with TSO the store isn't
done once the instruction retires.
All we want to ensure is that the pte_clear() store is issued after the
copy, and that is indeed guaranteed by this.
> + pte_clear(poking_mm, poking_addr, ptep);
> +
> + /*
> + * __flush_tlb_one_user() performs a redundant TLB flush when PTI is on,
> + * as it also flushes the corresponding "user" address spaces, which
> + * does not exist.
> + *
> + * Poking, however, is already very inefficient since it does not try to
> + * batch updates, so we ignore this problem for the time being.
> + *
> + * Since the PTEs do not exist in other kernel address-spaces, we do
> + * not use __flush_tlb_one_kernel(), which when PTI is on would cause
> + * more unwarranted TLB flushes.
> + */
yuck :-), but yeah.
> + __flush_tlb_one_user(poking_addr);
> + if (pages[1]) {
> + pte_clear(poking_mm, poking_addr + PAGE_SIZE, ptep + 1);
> + __flush_tlb_one_user(poking_addr + PAGE_SIZE);
> + }
> + /*
> + * Loading the previous page-table hierarchy requires a serializing
> + * instruction that already allows the core to see the updated version.
> + * Xen-PV is assumed to serialize execution in a similar manner.
> + */
> + unuse_temporary_mm(prev);
> +
> + pte_unmap_unlock(ptep, ptl);
> +}
[PATCH] mfd: motorola-cpcap: Add audio-codec support
From: Sebastian Reichel
Add support for the audio-codec node by converting from
devm_of_platform_populate() to devm_mfd_add_devices().
Tested-by: Pavel Machek
Acked-by: Tony Lindgren
Signed-off-by: Sebastian Reichel
Signed-off-by: Pavel Machek
diff --git a/drivers/mfd/motorola-cpcap.c b/drivers/mfd/motorola-cpcap.c
index 5276911..20d9692 100644
--- a/drivers/mfd/motorola-cpcap.c
+++ b/drivers/mfd/motorola-cpcap.c
@@ -18,6 +18,7 @@
#include
#include
+#include
#include
#include
@@ -216,6 +217,53 @@ static const struct regmap_config cpcap_regmap_config = {
.val_format_endian = REGMAP_ENDIAN_LITTLE,
};
+static const struct mfd_cell cpcap_mfd_devices[] = {
+ {
+ .name = "cpcap_adc",
+ .of_compatible = "motorola,mapphone-cpcap-adc",
+ }, {
+ .name = "cpcap_battery",
+ .of_compatible = "motorola,cpcap-battery",
+ }, {
+ .name = "cpcap-charger",
+ .of_compatible = "motorola,mapphone-cpcap-charger",
+ }, {
+ .name = "cpcap-regulator",
+ .of_compatible = "motorola,mapphone-cpcap-regulator",
+ }, {
+ .name = "cpcap-rtc",
+ .of_compatible = "motorola,cpcap-rtc",
+ }, {
+ .name = "cpcap-pwrbutton",
+ .of_compatible = "motorola,cpcap-pwrbutton",
+ }, {
+ .name = "cpcap-usb-phy",
+ .of_compatible = "motorola,mapphone-cpcap-usb-phy",
+ }, {
+ .name = "cpcap-led",
+ .id= 0,
+ .of_compatible = "motorola,cpcap-led-red",
+ }, {
+ .name = "cpcap-led",
+ .id= 1,
+ .of_compatible = "motorola,cpcap-led-green",
+ }, {
+ .name = "cpcap-led",
+ .id= 2,
+ .of_compatible = "motorola,cpcap-led-blue",
+ }, {
+ .name = "cpcap-led",
+ .id= 3,
+ .of_compatible = "motorola,cpcap-led-adl",
+ }, {
+ .name = "cpcap-led",
+ .id= 4,
+ .of_compatible = "motorola,cpcap-led-cp",
+ }, {
+ .name = "cpcap-codec",
+ }
+};
+
static int cpcap_probe(struct spi_device *spi)
{
const struct of_device_id *match;
@@ -260,7 +308,8 @@ static int cpcap_probe(struct spi_device *spi)
if (ret)
return ret;
- return devm_of_platform_populate(>spi->dev);
+ return devm_mfd_add_devices(>dev, 0, cpcap_mfd_devices,
+ ARRAY_SIZE(cpcap_mfd_devices), NULL, 0,
NULL);
}
static struct spi_driver cpcap_driver = {
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures)
http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
signature.asc
Description: Digital signature
[PATCH] mfd: ti-lmu: constify mfd_cell tables
From: Sebastian Reichel
mfd: ti-lmu: constify mfd_cell tables
Add const attribute to all mfd_cell structures.
Signed-off-by: Sebastian Reichel
Signed-off-by: Pavel Machek
diff --git a/drivers/mfd/ti-lmu.c b/drivers/mfd/ti-lmu.c
index cfb411c..990437e 100644
--- a/drivers/mfd/ti-lmu.c
+++ b/drivers/mfd/ti-lmu.c
@@ -25,7 +25,7 @@
#include
struct ti_lmu_data {
- struct mfd_cell *cells;
+ const struct mfd_cell *cells;
int num_cells;
unsigned int max_register;
};
@@ -63,7 +63,7 @@ static void ti_lmu_disable_hw(struct ti_lmu *lmu)
gpio_set_value(lmu->en_gpio, 0);
}
-static struct mfd_cell lm3532_devices[] = {
+static const struct mfd_cell lm3532_devices[] = {
{
.name = "ti-lmu-backlight",
.id= LM3532,
@@ -78,7 +78,7 @@ static struct mfd_cell lm3532_devices[] = {
.of_compatible = "ti,lm363x-regulator", \
} \
-static struct mfd_cell lm3631_devices[] = {
+static const struct mfd_cell lm3631_devices[] = {
LM363X_REGULATOR(LM3631_BOOST),
LM363X_REGULATOR(LM3631_LDO_CONT),
LM363X_REGULATOR(LM3631_LDO_OREF),
@@ -91,7 +91,7 @@ static struct mfd_cell lm3631_devices[] = {
},
};
-static struct mfd_cell lm3632_devices[] = {
+static const struct mfd_cell lm3632_devices[] = {
LM363X_REGULATOR(LM3632_BOOST),
LM363X_REGULATOR(LM3632_LDO_POS),
LM363X_REGULATOR(LM3632_LDO_NEG),
@@ -102,7 +102,7 @@ static struct mfd_cell lm3632_devices[] = {
},
};
-static struct mfd_cell lm3633_devices[] = {
+static const struct mfd_cell lm3633_devices[] = {
{
.name = "ti-lmu-backlight",
.id= LM3633,
@@ -120,7 +120,7 @@ static struct mfd_cell lm3633_devices[] = {
},
};
-static struct mfd_cell lm3695_devices[] = {
+static const struct mfd_cell lm3695_devices[] = {
{
.name = "ti-lmu-backlight",
.id= LM3695,
@@ -128,7 +128,7 @@ static struct mfd_cell lm3695_devices[] = {
},
};
-static struct mfd_cell lm3697_devices[] = {
+static const struct mfd_cell lm3697_devices[] = {
{
.name = "ti-lmu-backlight",
.id= LM3697,
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures)
http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
signature.asc
Description: Digital signature
Re: [PATCH] locking/lockdep: Delete unnecesary #include
On Tue, Aug 28, 2018 at 09:33:15PM +0100, Ben Hutchings wrote:
> Commit c3bc8fd637a9 ("tracing: Centralize preemptirq tracepoints and u
> nify their usage") added the inclusion of .
> liblockdep doesn't have a stub version of that header so now fails to
> build.
>
> However, commit bff1b208a5d1 ("tracing: Partial revert of "tracing:
> Centralize preemptirq tracepoints and unify their usage"") removed the
> use of functions declared in that header. So delete the #include.
>
> Fixes: c3bc8fd637a9 ("tracing: Centralize preemptirq tracepoints ...")
> Fixes: bff1b208a5d1 ("tracing: Partial revert of "tracing: Centralize ...")
There's no actual breakage because of this extra include, is there?
[PATCH] staging: fsl-dpaa2/ethsw: remove redundant pointer 'port_priv'
From: Colin Ian King
Pointer 'port_priv' is being assigned but is never used hence it is
redundant and can be removed.
Cleans up clang warning:
variable 'port_priv' set but not used [-Wunused-but-set-variable]
Signed-off-by: Colin Ian King
---
drivers/staging/fsl-dpaa2/ethsw/ethsw.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/staging/fsl-dpaa2/ethsw/ethsw.c
b/drivers/staging/fsl-dpaa2/ethsw/ethsw.c
index ecdd3d84f956..0066ca3072c1 100644
--- a/drivers/staging/fsl-dpaa2/ethsw/ethsw.c
+++ b/drivers/staging/fsl-dpaa2/ethsw/ethsw.c
@@ -1014,10 +1014,8 @@ static void ethsw_switchdev_event_work(struct
work_struct *work)
container_of(work, struct ethsw_switchdev_event_work, work);
struct net_device *dev = switchdev_work->dev;
struct switchdev_notifier_fdb_info *fdb_info;
- struct ethsw_port_priv *port_priv;
rtnl_lock();
- port_priv = netdev_priv(dev);
fdb_info = _work->fdb_info;
switch (switchdev_work->event) {
--
2.17.1
RE: [PATCH v1 2/7] extcon: Switch to use kasprintf() instead of open coded
From: Andy Shevchenko
> Sent: 27 August 2018 16:36
>
> Switch to use kasprintf() instead of open coded variant.
> No functional change intended.
>
> Signed-off-by: Andy Shevchenko
> ---
> drivers/extcon/extcon.c | 13 +++--
> 1 file changed, 3 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/extcon/extcon.c b/drivers/extcon/extcon.c
> index c21650a92689..5ab0498be652 100644
> --- a/drivers/extcon/extcon.c
> +++ b/drivers/extcon/extcon.c
> @@ -1123,7 +1123,6 @@ int extcon_dev_register(struct extcon_dev *edev)
> (unsigned long)atomic_inc_return(_no));
>
> if (edev->max_supported) {
> - char buf[10];
> char *str;
> struct extcon_cable *cable;
>
> @@ -1137,9 +1136,7 @@ int extcon_dev_register(struct extcon_dev *edev)
> for (index = 0; index < edev->max_supported; index++) {
> cable = >cables[index];
>
> - snprintf(buf, 10, "cable.%d", index);
> - str = kzalloc(strlen(buf) + 1,
> - GFP_KERNEL);
> + str = kasprintf(GFP_KERNEL, "cable.%d", index);
Hmmm... Why now just allocate the space for the string in the
'extcon_cable' structure.
(Then work out how to stop gcc complaining there isn't room
for 4G cables ...)
David
-
Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT,
UK
Registration No: 1397386 (Wales)
Re: [PATCH v1] arm64: dts: sdm845: enable tsens thermal zones
On 18/07/2018 09:49, Amit Kucheria wrote:
> One thermal zone per cpu is defined
The thermal zones are very close, especially when the CPUs belong to the
same 'cluster'. Very likely the temperature will propagate from one core
to another core, so when one core reaches the trip0, there is good
chance the other cores will be close and cross the trip0 threshold too.
Having multiple thermal zones, one per CPU, may trigger an interrupts
storm with the passive polling timer delay.
Does this board have a cooling device per CPU also ?
> Signed-off-by: Amit Kucheria
> ---
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 170
> +++
> 1 file changed, 170 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 01ff146..a75be7c 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -340,4 +340,174 @@
> };
> };
> };
> +
> + thermal-zones {
> + cpu0-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = < 1>;
> +
> + trips {
> + cpu_alert0: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit0: trip1 {
> + temperature = <11>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu1-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = < 2>;
> +
> + trips {
> + cpu_alert1: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit1: trip1 {
> + temperature = <11>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu2-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = < 3>;
> +
> + trips {
> + cpu_alert2: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit2: trip1 {
> + temperature = <11>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu3-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = < 4>;
> +
> + trips {
> + cpu_alert3: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit3: trip1 {
> + temperature = <11>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu4-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = < 7>;
> +
> + trips {
> + cpu_alert4: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit4: trip1 {
> + temperature = <11>;
> + hysteresis = <1000>;
> +
[PATCH v2] perf: Support for Arm A32/T32 instruction sets in CoreSight trace
This patch adds support for generating instruction samples from trace of
AArch32 programs using the A32 and T32 instruction sets.
T32 has variable 2 or 4 byte instruction size, so the conversion between
addresses and instruction counts requires extra information from the trace
decoder, requiring version 0.9.1 of OpenCSD. A check for the new struct
member has been added to the feature check for OpenCSD.
Signed-off-by: Robert Walker
---
v2: Minor fixes following review comments from Mathieu
Rebased on v4.19-rc1
tools/build/feature/test-libopencsd.c | 7 +++
tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 27 ++
tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 10
tools/perf/util/cs-etm.c| 71 +++--
4 files changed, 75 insertions(+), 40 deletions(-)
diff --git a/tools/build/feature/test-libopencsd.c
b/tools/build/feature/test-libopencsd.c
index 5ff1246..d96b2df 100644
--- a/tools/build/feature/test-libopencsd.c
+++ b/tools/build/feature/test-libopencsd.c
@@ -3,6 +3,13 @@
int main(void)
{
+ /*
+* Requires ocsd_generic_trace_elem.num_instr_range introduced in
+* OpenCSD 0.9
+*/
+ ocsd_generic_trace_elem elem;
+ (void)elem.num_instr_range;
+
(void)ocsd_get_version();
return 0;
}
diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
index 938def6..73d8384 100644
--- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
+++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
@@ -263,9 +263,12 @@ static void cs_etm_decoder__clear_buffer(struct
cs_etm_decoder *decoder)
decoder->tail = 0;
decoder->packet_count = 0;
for (i = 0; i < MAX_BUFFER; i++) {
+ decoder->packet_buffer[i].isa = CS_ETM_ISA_UNKNOWN;
decoder->packet_buffer[i].start_addr = CS_ETM_INVAL_ADDR;
decoder->packet_buffer[i].end_addr = CS_ETM_INVAL_ADDR;
+ decoder->packet_buffer[i].instr_count = 0;
decoder->packet_buffer[i].last_instr_taken_branch = false;
+ decoder->packet_buffer[i].last_instr_size = 0;
decoder->packet_buffer[i].exc = false;
decoder->packet_buffer[i].exc_ret = false;
decoder->packet_buffer[i].cpu = INT_MIN;
@@ -294,11 +297,13 @@ cs_etm_decoder__buffer_packet(struct cs_etm_decoder
*decoder,
decoder->packet_count++;
decoder->packet_buffer[et].sample_type = sample_type;
+ decoder->packet_buffer[et].isa = CS_ETM_ISA_UNKNOWN;
decoder->packet_buffer[et].exc = false;
decoder->packet_buffer[et].exc_ret = false;
decoder->packet_buffer[et].cpu = *((int *)inode->priv);
decoder->packet_buffer[et].start_addr = CS_ETM_INVAL_ADDR;
decoder->packet_buffer[et].end_addr = CS_ETM_INVAL_ADDR;
+ decoder->packet_buffer[et].instr_count = 0;
if (decoder->packet_count == MAX_BUFFER - 1)
return OCSD_RESP_WAIT;
@@ -321,8 +326,28 @@ cs_etm_decoder__buffer_range(struct cs_etm_decoder
*decoder,
packet = >packet_buffer[decoder->tail];
+ switch (elem->isa) {
+ case ocsd_isa_aarch64:
+ packet->isa = CS_ETM_ISA_A64;
+ break;
+ case ocsd_isa_arm:
+ packet->isa = CS_ETM_ISA_A32;
+ break;
+ case ocsd_isa_thumb2:
+ packet->isa = CS_ETM_ISA_T32;
+ break;
+ case ocsd_isa_tee:
+ case ocsd_isa_jazelle:
+ case ocsd_isa_custom:
+ case ocsd_isa_unknown:
+ default:
+ packet->isa = CS_ETM_ISA_UNKNOWN;
+ }
+
packet->start_addr = elem->st_addr;
packet->end_addr = elem->en_addr;
+ packet->instr_count = elem->num_instr_range;
+
switch (elem->last_i_type) {
case OCSD_INSTR_BR:
case OCSD_INSTR_BR_INDIRECT:
@@ -336,6 +361,8 @@ cs_etm_decoder__buffer_range(struct cs_etm_decoder *decoder,
break;
}
+ packet->last_instr_size = elem->last_instr_sz;
+
return ret;
}
diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h
b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h
index 612b575..9351bd1 100644
--- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h
+++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h
@@ -28,11 +28,21 @@ enum cs_etm_sample_type {
CS_ETM_TRACE_ON = 1 << 1,
};
+enum cs_etm_isa {
+ CS_ETM_ISA_UNKNOWN,
+ CS_ETM_ISA_A64,
+ CS_ETM_ISA_A32,
+ CS_ETM_ISA_T32,
+};
+
struct cs_etm_packet {
enum cs_etm_sample_type sample_type;
+ enum cs_etm_isa isa;
u64 start_addr;
u64 end_addr;
+ u32 instr_count;
u8 last_instr_taken_branch;
+ u8 last_instr_size;
u8 exc;
u8 exc_ret;
int cpu;
diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c
index 2ae6402..fcaa73f 100644
Re: [PATCH 5/5] net: mvneta: reduce smp_processor_id() calling in mvneta_tx_done_gbe
Hi Jisheng,
On mer., août 29 2018, Jisheng Zhang wrote:
> In the loop of mvneta_tx_done_gbe(), we call the smp_processor_id()
> each time, move the call out of the loop to optimize the code a bit.
>
> Before the patch, the loop looks like(under arm64):
>
> ldr x1, [x29,#120]
> ...
> ldr w24, [x1,#36]
> ...
> bl 0 <_raw_spin_lock>
> str w24, [x27,#132]
> ...
>
> After the patch, the loop looks like(under arm64):
>
> ...
> bl 0 <_raw_spin_lock>
> str w23, [x28,#132]
> ...
> where w23 is loaded so be ready before the loop.
>
> From another side, mvneta_tx_done_gbe() is called from mvneta_poll()
> which is in non-preemptible context, so it's safe to call the
> smp_processor_id() function once.
This improvement should go to net-next. Besides this patch looks nice:
Reviewed-by: Gregory CLEMENT
Thanks,
Gregory
>
> Signed-off-by: Jisheng Zhang
> ---
> drivers/net/ethernet/marvell/mvneta.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/marvell/mvneta.c
> b/drivers/net/ethernet/marvell/mvneta.c
> index 7d98f7828a30..62e81e267e13 100644
> --- a/drivers/net/ethernet/marvell/mvneta.c
> +++ b/drivers/net/ethernet/marvell/mvneta.c
> @@ -2507,12 +2507,13 @@ static void mvneta_tx_done_gbe(struct mvneta_port
> *pp, u32 cause_tx_done)
> {
> struct mvneta_tx_queue *txq;
> struct netdev_queue *nq;
> + int cpu = smp_processor_id();
>
> while (cause_tx_done) {
> txq = mvneta_tx_done_policy(pp, cause_tx_done);
>
> nq = netdev_get_tx_queue(pp->dev, txq->id);
> - __netif_tx_lock(nq, smp_processor_id());
> + __netif_tx_lock(nq, cpu);
>
> if (txq->count)
> mvneta_txq_done(pp, txq);
> --
> 2.18.0
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
RE: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
[snip..]
> > >
> > > @@ -38,6 +39,18 @@ static LIST_HEAD(sgx_active_page_list); static
> > > DEFINE_SPINLOCK(sgx_active_page_list_lock);
> > > static struct task_struct *ksgxswapd_tsk; static
> > > DECLARE_WAIT_QUEUE_HEAD(ksgxswapd_waitq);
> > > +static struct notifier_block sgx_pm_notifier; static u64
> > > +sgx_pm_cnt;
> > > +
> > > +/* The cache for the last known values of IA32_SGXLEPUBKEYHASHx
> > > +MSRs
> > > for each
> > > + * CPU. The entries are initialized when they are first used by
> > > sgx_einit().
> > > + */
> > > +struct sgx_lepubkeyhash {
> > > + u64 msrs[4];
> > > + u64 pm_cnt;
> >
> > May I ask why do we need pm_cnt here? In fact why do we need suspend
> > staff (namely, sgx_pm_cnt above, and related code in this patch) here
> > in this patch? From the patch commit message I don't see why we need
> > PM staff here. Please give comment why you need PM staff, or you may
> > consider to split the PM staff to another patch.
>
> Refining the commit message probably makes more sense because without PM
> code sgx_einit() would be broken. The MSRs have been reset after waking up.
>
> Some kind of counter is required to keep track of the power cycle. When going
> to sleep the sgx_pm_cnt is increased. sgx_einit() compares the current value
> of
> the global count to the value in the cache entry to see whether we are in a
> new
> power cycle.
You mean reset to Intel default? I think we can also just reset the cached MSR
values on each power cycle, which would be simpler, IMHO?
I think we definitely need some code to handle S3-S5, but should be in separate
patches, since I think the major impact of S3-S5 is entire EPC being destroyed.
I think keeping pm_cnt is not sufficient enough to handle such case?
>
> This brings up one question though: how do we deal with VM host going to
> sleep?
> VM guest would not be aware of this.
IMO VM just gets "sudden loss of EPC" after suspend & resume in host. SGX
driver and SDK should be able to handle "sudden loss of EPC", ie, co-working
together to re-establish the missing enclaves.
Actually supporting "sudden loss of EPC" is a requirement to support live
migration of VM w/ SGX. Internally long time ago we had a discussion and the
decision was we should support SGX live migration given two facts:
1) losing platform-dependent is not important. For example, losing sealing key
is not a problem, as we could get secrets provisioned again from remote. 2)
Both windows & linux driver commit to support "sudden loss of EPC".
I don't think we have to support in very first upstream driver, but I think we
need to support someday.
Sean,
Would you be able to comment here?
>
> I think the best measure would be to add a new parameter to sgx_einit() that
> enforces update of the MSRs. The driver can then set this parameter in the
> case
> when sgx_einit() returns SGX_INVALID_LICENSE. This is coherent because the
> driver requires writable MSRs. It would not be coherent to do it directly in
> the
> core because KVM does not require writable MSRs.
IMHO this is not required, as I mentioned above.
And
[snip...]
Thanks,
-Kai
[PATCH] PM / devfreq: Add new name attribute for sysfs
commit 4585fbcb5331 ("PM / devfreq: Modify the device name as devfreq(X) for
sysfs") changed the node name to devfreq(x). After this commit, it is not
possible to get the device name through /sys/class/devfreq/devfreq(X)/*.
Add new name attribute in order to get device name.
Cc: sta...@vger.kernel.org
Fixes: 4585fbcb5331 ("PM / devfreq: Modify the device name as devfreq(X) for
sysfs")
Signed-off-by: Chanwoo Choi
---
drivers/devfreq/devfreq.c | 11 +++
include/linux/devfreq.h | 3 +++
2 files changed, 14 insertions(+)
diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c
index 4c49bb1330b5..2145563d5ee5 100644
--- a/drivers/devfreq/devfreq.c
+++ b/drivers/devfreq/devfreq.c
@@ -620,6 +620,9 @@ struct devfreq *devfreq_add_device(struct device *dev,
}
devfreq->max_freq = devfreq->scaling_max_freq;
+ devfreq->name = dev_name(devfreq->dev.parent);
+ if (IS_ERR_OR_NULL(devfreq->name))
+ return -EINVAL;
dev_set_name(>dev, "devfreq%d",
atomic_inc_return(_no));
err = device_register(>dev);
@@ -1261,6 +1264,13 @@ static ssize_t trans_stat_show(struct device *dev,
}
static DEVICE_ATTR_RO(trans_stat);
+static ssize_t name_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%s\n", to_devfreq(dev)->name);
+}
+static DEVICE_ATTR_RO(name);
+
static struct attribute *devfreq_attrs[] = {
_attr_governor.attr,
_attr_available_governors.attr,
@@ -1271,6 +1281,7 @@ static ssize_t trans_stat_show(struct device *dev,
_attr_min_freq.attr,
_attr_max_freq.attr,
_attr_trans_stat.attr,
+ _attr_name.attr,
NULL,
};
ATTRIBUTE_GROUPS(devfreq);
diff --git a/include/linux/devfreq.h b/include/linux/devfreq.h
index 3aae5b3af87c..f79b5a666102 100644
--- a/include/linux/devfreq.h
+++ b/include/linux/devfreq.h
@@ -111,6 +111,7 @@ struct devfreq_dev_profile {
/**
* struct devfreq - Device devfreq structure
+ * @name: name of the device
* @node: list node - contains the devices with devfreq that have been
* registered.
* @lock: a mutex to protect accessing devfreq.
@@ -146,6 +147,8 @@ struct devfreq_dev_profile {
* to protect its own private data in void *data as well.
*/
struct devfreq {
+ const char *name;
+
struct list_head node;
struct mutex lock;
--
1.9.1
Re: [PATCH v3 1/3] pinctrl: msm: Really mask level interrupts to prevent latching
On Thu, Aug 16, 2018 at 10:06 PM Stephen Boyd wrote: > The interrupt controller hardware in this pin controller has two status > enable bits. The first "normal" status enable bit enables or disables > the summary interrupt line being raised when a gpio interrupt triggers > and the "raw" status enable bit allows or prevents the hardware from > latching an interrupt into the status register for a gpio interrupt. > Currently we just toggle the "normal" status enable bit in the mask and > unmask ops so that the summary irq interrupt going to the CPU's > interrupt controller doesn't trigger for the masked gpio interrupt. > > For a level triggered interrupt, the flow would be as follows: the pin > controller sees the interrupt, latches the status into the status > register, raises the summary irq to the CPU, summary irq handler runs > and calls handle_level_irq(), handle_level_irq() masks and acks the gpio > interrupt, the interrupt handler runs, and finally unmask the interrupt. > When the interrupt handler completes, we expect that the interrupt line > level will go back to the deasserted state so the genirq code can unmask > the interrupt without it triggering again. > > If we only mask the interrupt by clearing the "normal" status enable bit > then we'll ack the interrupt but it will continue to show up as pending > in the status register because the raw status bit is enabled, the > hardware hasn't deasserted the line, and thus the asserted state latches > into the status register again. When the hardware deasserts the > interrupt the pin controller still thinks there is a pending unserviced > level interrupt because it latched it earlier. This behavior causes > software to see an extra interrupt for level type interrupts each time > the interrupt is handled. > > Let's fix this by clearing the raw status enable bit for level type > interrupts so that the hardware stops latching the status of the > interrupt after we ack it. We don't do this for edge type interrupts > because it seems that toggling the raw status enable bit for edge type > interrupts causes spurious edge interrupts. > > Cc: Bjorn Andersson > Cc: Doug Anderson > Signed-off-by: Stephen Boyd This patch applied for fixes with Doug and Bjorn's ACKs. I suppose you will respin the two others and obtain buy-in from the same people for these. Yours, Linus Walleij
Re: [RFC PATCH] EDAC, ghes: Enable per-layer error reporting for ARM
On Tue, Aug 28, 2018 at 06:09:24PM +0100, James Morse wrote: > Does x86 have another source of memory-topology information it needs to > correlate smbios with? Bah, pinpointing the DIMM on x86 is a mess. There's no reliable way to say which DIMM it is in certain cases (interleaving, mirrorring, ...) and it is all platform-dependent. So we do the layers to dump a memory location (node, memory controller, ) so that we can at least limit the number of DIMMs the user needs to replace/try. In an ideal world, I'd like to be able to query the SPD chips on the DIMMs and build the topology and then when an error happens to say, "error in DIMM " where silkscreen is what is written on the motherboard under the DIMM socket. But I don't see that happening any time soon... > For arm there is nothing else describing the memory-topology, so as long as we > can correlate the smbios table and ghes:cper records through the handles, we > can > get this working for all systems. And then make sure vendors fill in the proper info in smbios. Because that's also a mess on x86. -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply. --
Re: [PATCH v3 1/3] pinctrl: msm: Really mask level interrupts to prevent latching
On Wed, Aug 29, 2018 at 9:40 AM Linus Walleij wrote: > This patch applied for fixes with Doug and Bjorn's ACKs. > > I suppose you will respin the two others and obtain buy-in from > the same people for these. Scrap that. I saw Bjorn has ACKed the two others so applied them for next (v4.20). Yours, Linus Walleij
Re: [PATCH v3 3/3] pinctrl: msm: Configure interrupts as input and gpio mode
On Thu, Aug 16, 2018 at 10:06 PM Stephen Boyd wrote: > When requesting a gpio as an interrupt, we should make sure to mux the > pin as the GPIO function and configure it to be an input so that various > functions or output signals don't affect the interrupt state of the pin. > So far, we've relied on pinmux configurations in DT to handle this, but > let's explicitly configure this in the code so that DT implementers > don't have to get this part right. > > Cc: Bjorn Andersson > Cc: Doug Anderson > Signed-off-by: Stephen Boyd Patch applied for v4.20 with Bjorn's ACK. Yours, Linus Walleij
Re: [PATCH] regulator: Convert to using %pOFn instead of device_node.name
On Tue, 28 Aug 2018 at 03:55, Rob Herring wrote: > > In preparation to remove the node name pointer from struct device_node, > convert printf users to use the %pOFn format specifier. > > Cc: Liam Girdwood > Cc: Mark Brown > Cc: Sangbeom Kim > Cc: Krzysztof Kozlowski > Cc: Bartlomiej Zolnierkiewicz > Cc: linux-samsung-...@vger.kernel.org > Signed-off-by: Rob Herring > --- > drivers/regulator/max8997-regulator.c | 4 +- > drivers/regulator/mc13xxx-regulator-core.c | 2 +- > drivers/regulator/of_regulator.c | 44 +++--- > drivers/regulator/qcom-rpmh-regulator.c| 14 +++ > drivers/regulator/s5m8767.c| 12 +++--- For S5M8767: Acked-by: Krzysztof Kozlowski Best regards, Krzysztof
[PATCH v6 1/9] soc: qcom: smem: Add missing include of sizes.h
Add missing include of sizes.h. drivers/soc/qcom/smem.c: In function ‘qcom_smem_get_ptable’: drivers/soc/qcom/smem.c:666:64: error: ‘SZ_4K’ undeclared ptable = smem->regions[0].virt_base + smem->regions[0].size - SZ_4K; ^ Signed-off-by: Niklas Cassel Reviewed-by: Vivek Gautam Reviewed-by: Vinod Koul --- drivers/soc/qcom/smem.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index bf4bd71ab53f..b77573eed596 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include -- 2.17.1
[PATCH v6 4/9] soc: qcom: smsm: Add select IRQ_DOMAIN
Since we are using irq_domain_add_linear(), add a select on IRQ_DOMAIN. This is needed in order to be able to remove the depends on ARCH_QCOM. drivers/soc/qcom/smsm.c: In function ‘smsm_inbound_entry’: drivers/soc/qcom/smsm.c:411:18: error: implicit declaration of function ‘irq_domain_add_linear’ entry->domain = irq_domain_add_linear(node, 32, _irq_ops, entry); ^ Signed-off-by: Niklas Cassel Reviewed-by: Vivek Gautam Reviewed-by: Vinod Koul --- drivers/soc/qcom/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 6e063202ad0b..7da6e67c7ea1 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -143,6 +143,7 @@ config QCOM_SMSM tristate "Qualcomm Shared Memory State Machine" depends on QCOM_SMEM select QCOM_SMEM_STATE + select IRQ_DOMAIN help Say yes here to support the Qualcomm Shared Memory State Machine. The state machine is represented by bits in shared memory. -- 2.17.1
[PATCH v6 0/9] soc: qcom: Allow COMPILE_TEST of qcom SoC Kconfigs
Since commit cab673583d96 ("soc: Unconditionally include qcom Makefile"),
we unconditionally include the soc/qcom/Makefile.
This opens up the possibility to compile test the code even when
building for other architectures.
This patch series prepares and enables all but two Kconfigs to be
compile tested even when building for other architectures.
Changes since v5:
-kbuild test robot now uses gcc 8, so it found some new warnings
with -Wstringop-truncation, created 2 new patches for this.
-Removed depends on OF from QCOM_RPMH, new patch.
Niklas Cassel (9):
soc: qcom: smem: Add missing include of sizes.h
soc: qcom: llcc-slice: Add missing include of sizes.h
soc: qcom: smp2p: Add select IRQ_DOMAIN
soc: qcom: smsm: Add select IRQ_DOMAIN
soc: qcom: Remove bogus depends on OF from QCOM_SMD_RPM
soc: qcom: Remove depends on OF from QCOM_RPMH
soc: qcom: wcnss_ctrl: Avoid string overflow
soc: qcom: apr: Avoid string overflow
soc: qcom: Allow COMPILE_TEST of qcom SoC Kconfigs
drivers/soc/qcom/Kconfig | 21 -
drivers/soc/qcom/apr.c| 4 ++--
drivers/soc/qcom/llcc-slice.c | 1 +
drivers/soc/qcom/smem.c | 1 +
drivers/soc/qcom/wcnss_ctrl.c | 2 +-
5 files changed, 17 insertions(+), 12 deletions(-)
--
2.17.1
Re: [PATCH v6 1/2] dt-binding: pinctrl: Add NPCM7xx pinctrl and GPIO documentation
On Wed, Aug 8, 2018 at 11:25 AM Tomer Maimon wrote: > Added device tree binding documentation for Nuvoton BMC > NPCM750/730/715/705 pinmux and GPIO controller. > > Signed-off-by: Tomer Maimon > Reviewed-by: Rob Herring Patch applied, bindings are clearly finished! Yours, Linus Walleij
[PATCH v6 7/9] soc: qcom: wcnss_ctrl: Avoid string overflow
'chinfo.name' is used as a NUL-terminated string, but using strncpy() with the length equal to the buffer size may result in lack of the termination: drivers//soc/qcom/wcnss_ctrl.c: In function 'qcom_wcnss_open_channel': drivers//soc/qcom/wcnss_ctrl.c:284:2: warning: 'strncpy' specified bound 32 equals destination size [-Wstringop-truncation] strncpy(chinfo.name, name, sizeof(chinfo.name)); ^~~ This changes it to use the safer strscpy() instead. Signed-off-by: Niklas Cassel --- drivers/soc/qcom/wcnss_ctrl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/wcnss_ctrl.c b/drivers/soc/qcom/wcnss_ctrl.c index df3ccb30bc2d..373400dd816d 100644 --- a/drivers/soc/qcom/wcnss_ctrl.c +++ b/drivers/soc/qcom/wcnss_ctrl.c @@ -281,7 +281,7 @@ struct rpmsg_endpoint *qcom_wcnss_open_channel(void *wcnss, const char *name, rp struct rpmsg_channel_info chinfo; struct wcnss_ctrl *_wcnss = wcnss; - strncpy(chinfo.name, name, sizeof(chinfo.name)); + strscpy(chinfo.name, name, sizeof(chinfo.name)); chinfo.src = RPMSG_ADDR_ANY; chinfo.dst = RPMSG_ADDR_ANY; -- 2.17.1
[PATCH v6 8/9] soc: qcom: apr: Avoid string overflow
'adev->name' is used as a NUL-terminated string, but using strncpy() with the length equal to the buffer size may result in lack of the termination: In function 'apr_add_device', inlined from 'of_register_apr_devices' at drivers//soc/qcom/apr.c:264:7, inlined from 'apr_probe' at drivers//soc/qcom/apr.c:290:2: drivers//soc/qcom/apr.c:222:3: warning: 'strncpy' specified bound 32 equals destination size [-Wstringop-truncation] strncpy(adev->name, np->name, APR_NAME_SIZE); ^~~~ This changes it to use the safer strscpy() instead. Signed-off-by: Niklas Cassel --- drivers/soc/qcom/apr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/apr.c b/drivers/soc/qcom/apr.c index 57af8a537332..ee9197f5aae9 100644 --- a/drivers/soc/qcom/apr.c +++ b/drivers/soc/qcom/apr.c @@ -219,9 +219,9 @@ static int apr_add_device(struct device *dev, struct device_node *np, adev->domain_id = id->domain_id; adev->version = id->svc_version; if (np) - strncpy(adev->name, np->name, APR_NAME_SIZE); + strscpy(adev->name, np->name, APR_NAME_SIZE); else - strncpy(adev->name, id->name, APR_NAME_SIZE); + strscpy(adev->name, id->name, APR_NAME_SIZE); dev_set_name(>dev, "aprsvc:%s:%x:%x", adev->name, id->domain_id, id->svc_id); -- 2.17.1
[PATCH v6 2/9] soc: qcom: llcc-slice: Add missing include of sizes.h
Add missing include of sizes.h. drivers/soc/qcom/llcc-slice.c: In function ‘llcc_update_act_ctrl’: drivers/soc/qcom/llcc-slice.c:41:44: error: ‘SZ_4K’ undeclared #define LLCC_TRP_ACT_CTRLn(n) (n * SZ_4K) ^ Signed-off-by: Niklas Cassel Reviewed-by: Vivek Gautam Reviewed-by: Vinod Koul --- drivers/soc/qcom/llcc-slice.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/llcc-slice.c b/drivers/soc/qcom/llcc-slice.c index 54063a31132f..344dc2daf431 100644 --- a/drivers/soc/qcom/llcc-slice.c +++ b/drivers/soc/qcom/llcc-slice.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include -- 2.17.1
[PATCH v6 5/9] soc: qcom: Remove bogus depends on OF from QCOM_SMD_RPM
QCOM_SMD_RPM builds perfectly fine without CONFIG_OF set. Remove the bogus depends on OF. Signed-off-by: Niklas Cassel Reviewed-by: Vivek Gautam Reviewed-by: Vinod Koul --- drivers/soc/qcom/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 7da6e67c7ea1..ac657164a136 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -114,7 +114,7 @@ config QCOM_SMEM config QCOM_SMD_RPM tristate "Qualcomm Resource Power Manager (RPM) over SMD" depends on ARCH_QCOM - depends on RPMSG && OF + depends on RPMSG help If you say yes to this option, support will be included for the Resource Power Manager system found in the Qualcomm 8974 based -- 2.17.1
[PATCH v6 3/9] soc: qcom: smp2p: Add select IRQ_DOMAIN
Since we are using irq_domain_add_linear(), add a select on IRQ_DOMAIN. This is needed in order to be able to remove the depends on ARCH_QCOM. drivers/soc/qcom/smp2p.c: In function ‘qcom_smp2p_inbound_entry’: drivers/soc/qcom/smp2p.c:317:18: error: implicit declaration of function ‘irq_domain_add_linear’ entry->domain = irq_domain_add_linear(node, 32, _irq_ops, entry); ^ Signed-off-by: Niklas Cassel Reviewed-by: Vivek Gautam Reviewed-by: Vinod Koul --- drivers/soc/qcom/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index ba79b609aca2..6e063202ad0b 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -134,6 +134,7 @@ config QCOM_SMP2P depends on MAILBOX depends on QCOM_SMEM select QCOM_SMEM_STATE + select IRQ_DOMAIN help Say yes here to support the Qualcomm Shared Memory Point to Point protocol. -- 2.17.1
Re: [PATCH RESEND 1/2] gpio: mvebu: Add support for multiple PWM lines per GPIO chip
Hello Linus, On Wed, 29 Aug 2018 09:54:04 +0200, Linus Walleij wrote: > On Mon, Aug 6, 2018 at 4:31 AM Aditya Prayoga wrote: > > > Allow more than 1 PWM request (eg. PWM fan) on the same GPIO chip. > > > > based on initial work on LK4.4 by Alban Browaeys. > > URL: https://github.com/helios-4/linux-marvell/commit/743ae97 > > [Aditya Prayoga: forward port, cleanup] > > Signed-off-by: Aditya Prayoga > > It would be awesome to get some feedback from the MVEBU maintainers > on this patch set. > > Who are most active on Marvell stuff these days? Thomas? Andrew Lunn did the initial support for PWM in this driver, and he outlined in the commit log the limitation of his first implementation: However, there are only two sets of PWM configuration registers for all the GPIO lines. This driver simply allows a single GPIO line per GPIO chip of 32 lines to be used as a PWM. Attempts to use more return EBUSY. Andrew, perhaps you could review the patch posted by Aditya, since you already looked at PWM support on mvebu platforms ? Thanks! Thomas -- Thomas Petazzoni, CTO, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
[PATCH]] zram: kselftests: correct README
CONFIG_ZRAM=y should be CONFIG_ZRAM=m it obviously uses zram kernel module in the testing Signed-off-by: Lei Yang --- tools/testing/selftests/zram/README | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/testing/selftests/zram/README b/tools/testing/selftests/zram/README index 7972cc5..501223a 100644 --- a/tools/testing/selftests/zram/README +++ b/tools/testing/selftests/zram/README @@ -12,7 +12,7 @@ Statistics for individual zram devices are exported through sysfs nodes at /sys/block/zram/ Kconfig required: -CONFIG_ZRAM=y +CONFIG_ZRAM=m CONFIG_CRYPTO_LZ4=y CONFIG_ZPOOL=y CONFIG_ZSMALLOC=y -- 1.9.1
Re: [PATCH RESEND 1/2] gpio: mvebu: Add support for multiple PWM lines per GPIO chip
Hi Linus, On mer., août 29 2018, Linus Walleij wrote: > On Mon, Aug 6, 2018 at 4:31 AM Aditya Prayoga wrote: > >> Allow more than 1 PWM request (eg. PWM fan) on the same GPIO chip. >> >> based on initial work on LK4.4 by Alban Browaeys. >> URL: https://github.com/helios-4/linux-marvell/commit/743ae97 >> [Aditya Prayoga: forward port, cleanup] >> Signed-off-by: Aditya Prayoga > > It would be awesome to get some feedback from the MVEBU maintainers > on this patch set. There already has been reviewed from Andrew and also from Richard who worked on the PWM part too. There were many questions raised, but no feedback yet, so for now this patch set is clearly not ready to be merged. We are waiting for answers and a new version. Gregory > > Who are most active on Marvell stuff these days? Thomas? > > Likewise I'd be very grateful for a nod from the PWM maintainer that > this is OK with him. > > Yours, > Linus Walleij -- Gregory Clement, Bootlin Embedded Linux and Kernel engineering http://bootlin.com
Re: [PATCH v4 2/7] dmaengine: xilinx_dma: in axidma slave_sg and dma_cylic mode align split descriptors
On Mon, Aug 27, 2018 at 7:30 AM Vinod wrote:
>
> On 02-08-18, 16:10, Andrea Merello wrote:
>
> s/cylic/cyclic in patch title
OK
> > Whenever a single or cyclic transaction is prepared, the driver
> > could eventually split it over several SG descriptors in order
> > to deal with the HW maximum transfer length.
> >
> > This could end up in DMA operations starting from a misaligned
> > address. This seems fatal for the HW if DRE is not enabled.
>
> DRE?
Stands for "Data Realignment Engine". I will add this string nearby
the acronym..
> >
> > This patch eventually adjusts the transfer size in order to make sure
> > all operations start from an aligned address.
> >
> > Cc: Radhey Shyam Pandey
> > Signed-off-by: Andrea Merello
> > Reviewed-by: Radhey Shyam Pandey
> > ---
> > Changes in v2:
> > - don't introduce copy_mask field, rather rely on already-esistent
> > copy_align field. Suggested by Radhey Shyam Pandey
> > - reword title
> > Changes in v3:
> > - fix bug introduced in v2: wrong copy size when DRE is enabled
> > - use implementation suggested by Radhey Shyam Pandey
> > Changes in v4:
> > - rework on the top of 1/6
> > ---
> > drivers/dma/xilinx/xilinx_dma.c | 22 ++
> > 1 file changed, 18 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/dma/xilinx/xilinx_dma.c
> > b/drivers/dma/xilinx/xilinx_dma.c
> > index a3aaa0e34cc7..aaa6de8a70e4 100644
> > --- a/drivers/dma/xilinx/xilinx_dma.c
> > +++ b/drivers/dma/xilinx/xilinx_dma.c
> > @@ -954,15 +954,28 @@ static int xilinx_dma_alloc_chan_resources(struct
> > dma_chan *dchan)
> >
> > /**
> > * xilinx_dma_calc_copysize - Calculate the amount of data to copy
> > + * @chan: Driver specific DMA channel
> > * @size: Total data that needs to be copied
> > * @done: Amount of data that has been already copied
> > *
> > * Return: Amount of data that has to be copied
> > */
> > -static int xilinx_dma_calc_copysize(int size, int done)
> > +static int xilinx_dma_calc_copysize(struct xilinx_dma_chan *chan,
> > + int size, int done)
>
> please align with opening brace
OK
> > {
> > - return min_t(size_t, size - done,
> > + size_t copy = min_t(size_t, size - done,
> >XILINX_DMA_MAX_TRANS_LEN);
> > +
> > + if ((copy + done < size) &&
> > + chan->xdev->common.copy_align) {
> > + /*
> > + * If this is not the last descriptor, make sure
> > + * the next one will be properly aligned
> > + */
> > + copy = rounddown(copy,
> > + (1 << chan->xdev->common.copy_align));
> > + }
> > + return copy;
> > }
> >
> > /**
> > @@ -1804,7 +1817,7 @@ static struct dma_async_tx_descriptor
> > *xilinx_dma_prep_slave_sg(
> >* Calculate the maximum number of bytes to transfer,
> >* making sure it is less than the hw limit
> >*/
> > - copy = xilinx_dma_calc_copysize(sg_dma_len(sg),
> > + copy = xilinx_dma_calc_copysize(chan, sg_dma_len(sg),
> > sg_used);
> > hw = >hw;
> >
> > @@ -1909,7 +1922,8 @@ static struct dma_async_tx_descriptor
> > *xilinx_dma_prep_dma_cyclic(
> >* Calculate the maximum number of bytes to transfer,
> >* making sure it is less than the hw limit
> >*/
> > - copy = xilinx_dma_calc_copysize(period_len, sg_used);
> > + copy = xilinx_dma_calc_copysize(chan,
> > + period_len, sg_used);
> > hw = >hw;
> > xilinx_axidma_buf(chan, hw, buf_addr, sg_used,
> > period_len * i);
> > --
> > 2.17.1
>
> --
> ~Vinod
[PATCH 01/31] ARM: tegra: colibri_t20: move aliases from module to carrier board
From: Marcel Ziswiler
Move RTC aliases from module to carrier board to be more in-line with
all our other device trees.
Signed-off-by: Marcel Ziswiler
---
arch/arm/boot/dts/tegra20-colibri-iris.dts | 2 ++
arch/arm/boot/dts/tegra20-colibri.dtsi | 5 -
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts
b/arch/arm/boot/dts/tegra20-colibri-iris.dts
index 57f16c0e9917..496b96e229d2 100644
--- a/arch/arm/boot/dts/tegra20-colibri-iris.dts
+++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts
@@ -8,6 +8,8 @@
compatible = "toradex,iris", "toradex,colibri_t20-512",
"nvidia,tegra20";
aliases {
+ rtc0 = "/i2c@7000d000/tps6586x@34";
+ rtc1 = "/rtc@7000e000";
serial0 =
serial1 =
};
diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi
b/arch/arm/boot/dts/tegra20-colibri.dtsi
index fa1af2dc276c..e34ab4a76158 100644
--- a/arch/arm/boot/dts/tegra20-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri.dtsi
@@ -5,11 +5,6 @@
model = "Toradex Colibri T20 256/512 MB";
compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
- aliases {
- rtc0 = "/i2c@7000d000/tps6586x@34";
- rtc1 = "/rtc@7000e000";
- };
-
memory@0 {
/*
* Set memory to 256 MB to be safe as this could be used on
--
2.14.4
Re: [PATCH v4 3/7] dt-bindings: dmaengine: xilinx_dma: add optional xlnx,sg-length-width property
On Mon, Aug 27, 2018 at 7:31 AM Vinod wrote:
>
> On 02-08-18, 16:10, Andrea Merello wrote:
> > The width of the "length register" cannot be autodetected, and it is now
> > specified with a DT property. Add DOC for it.
>
> Add Documentation for it...
OK
> >
> > Cc: Rob Herring
> > Cc: Mark Rutland
> > Cc: devicet...@vger.kernel.org
> > Cc: Radhey Shyam Pandey
> > Signed-off-by: Andrea Merello
> > Reviewed-by: Radhey Shyam Pandey
> > ---
> > Changes in v2:
> > - change property name
> > - property is now optional
> > - cc DT maintainer
> > Changes in v3:
> > - reword
> > - cc DT maintainerS and ML
> > Changes in v4:
> > - specify the unit, the valid range and the default value
> > ---
> > Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 4
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
> > b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
> > index a2b8bfaec43c..aec4a41a03ae 100644
> > --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
> > +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
> > @@ -41,6 +41,10 @@ Optional properties:
> > - xlnx,include-sg: Tells configured for Scatter-mode in
> > the hardware.
> > Optional properties for AXI DMA:
> > +- xlnx,sg-length-width: Should be set to the width in bits of the length
> > + register as configured in h/w. Takes values {8...26}. If the property
> > + is missing or invalid then the default value 23 is used. This is the
> > + maximum value that is supported by all IP versions.
> > - xlnx,mcdma: Tells whether configured for multi-channel mode in the
> > hardware.
> > Optional properties for VDMA:
> > - xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
> > --
> > 2.17.1
>
> --
> ~Vinod
[PATCH 07/31] ARM: tegra: colibri_t20: iris: use no-1-8-v
From: Marcel Ziswiler
Use no-1-8-v property rather than vmmc/vqmmc supplies and drop now
obsolete and anyway non-existent vcc_sd.
Signed-off-by: Marcel Ziswiler
---
arch/arm/boot/dts/tegra20-colibri-iris.dts | 13 +
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts
b/arch/arm/boot/dts/tegra20-colibri-iris.dts
index cc9e372a3b58..3d430fa93e8c 100644
--- a/arch/arm/boot/dts/tegra20-colibri-iris.dts
+++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts
@@ -101,8 +101,7 @@
sdhci@c8000600 {
status = "okay";
bus-width = <4>;
- vmmc-supply = <_sd_reg>;
- vqmmc-supply = <_sd_reg>;
+ no-1-8-v;
};
regulators {
@@ -116,15 +115,5 @@
regulator-always-on;
gpio = < TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
};
-
- vcc_sd_reg: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "vcc_sd";
- regulator-min-microvolt = <330>;
- regulator-max-microvolt = <330>;
- regulator-boot-on;
- regulator-always-on;
- };
};
};
--
2.14.4
[PATCH 12/31] ARM: tegra: colibri_t20: indentation/line-feed/white-space clean-up
From: Marcel Ziswiler
Cleaning up indentation, line-feed and white-space.
Signed-off-by: Marcel Ziswiler
---
arch/arm/boot/dts/tegra20-colibri.dtsi | 18 ++
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi
b/arch/arm/boot/dts/tegra20-colibri.dtsi
index 06d0be29c0b4..5559008efc5f 100644
--- a/arch/arm/boot/dts/tegra20-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri.dtsi
@@ -206,10 +206,10 @@
ac97: ac97@70002000 {
status = "okay";
- nvidia,codec-reset-gpio = < TEGRA_GPIO(V, 0)
- GPIO_ACTIVE_HIGH>;
- nvidia,codec-sync-gpio = < TEGRA_GPIO(P, 0)
- GPIO_ACTIVE_HIGH>;
+ nvidia,codec-reset-gpio =
+ < TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>;
+ nvidia,codec-sync-gpio =
+ < TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
};
nand-controller@70008000 {
@@ -254,12 +254,9 @@
compatible = "ti,tps6586x";
reg = <0x34>;
interrupts = ;
-
ti,system-power-controller;
-
#gpio-cells = <2>;
gpio-controller;
-
sys-supply = <_module_3v3>;
vin-sm0-supply = <_3v3_vsys>;
vin-sm1-supply = <_3v3_vsys>;
@@ -468,8 +465,8 @@
usb-phy@c5004000 {
status = "okay";
- nvidia,phy-reset-gpio = < TEGRA_GPIO(V, 1)
- GPIO_ACTIVE_LOW>;
+ nvidia,phy-reset-gpio =
+ < TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
vbus-supply = <_lan_v_bus>;
};
@@ -511,16 +508,13 @@
compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
"nvidia,tegra-audio-wm9712";
nvidia,model = "Colibri T20 AC97 Audio";
-
nvidia,audio-routing =
"Headphone", "HPOUTL",
"Headphone", "HPOUTR",
"LineIn", "LINEINL",
"LineIn", "LINEINR",
"Mic", "MIC1";
-
nvidia,ac97-controller = <>;
-
clocks = <_car TEGRA20_CLK_PLL_A>,
<_car TEGRA20_CLK_PLL_A_OUT0>,
<_car TEGRA20_CLK_CDEV1>;
--
2.14.4
[PATCH 11/31] ARM: tegra: colibri_t20: remove phy-reset-gpio from controller node
From: Marcel Ziswiler
Remove the phy-reset-gpio from the USB controller node as it is already
specified in the PHY node.
Signed-off-by: Marcel Ziswiler
---
arch/arm/boot/dts/tegra20-colibri.dtsi | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi
b/arch/arm/boot/dts/tegra20-colibri.dtsi
index 77e99caf5606..06d0be29c0b4 100644
--- a/arch/arm/boot/dts/tegra20-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri.dtsi
@@ -457,8 +457,6 @@
/* EHCI instance 1: ULPI PHY -> AX88772B (On-module) */
usb@c5004000 {
status = "okay";
- nvidia,phy-reset-gpio = < TEGRA_GPIO(V, 1)
- GPIO_ACTIVE_LOW>;
#address-cells = <1>;
#size-cells = <0>;
--
2.14.4
[PATCH 00/31] ARM: dts: tegra: colibri_t20: major revamp incl. eval board support
This series is a major overhaul and adds support for the Colibri Evaluation Board device tree. Marcel Ziswiler (31): ARM: tegra: colibri_t20: move aliases from module to carrier board ARM: tegra: colibri_t20: iris: integrate i2c real time clock support ARM: tegra: colibri_t20: iris: annotate i2c busses ARM: tegra: colibri_t20: iris: add missing aliases ARM: tegra: colibri_t20: add local-mac-address property ARM: tegra: colibri_t20: reorder host1x/hdmi properties ARM: tegra: colibri_t20: iris: use no-1-8-v ARM: tegra: colibri_t20: regulator clean-up ARM: tegra: colibri_t20: add missing regulators ARM: tegra: colibri_t20: annotate usb ehci instances ARM: tegra: colibri_t20: remove phy-reset-gpio from controller node ARM: tegra: colibri_t20: indentation/line-feed/white-space clean-up ARM: tegra: colibri_t20: update sound nvidia,model ARM: tegra: colibri_t20: pinmux clean-up ARM: tegra: colibri_t20: add missing pinmux ARM: tegra: colibri_t20: iris: display controller rgb panel support ARM: tegra: colibri_t20: iris: annotate uarts ARM: tegra: colibri_t20: iris: add uart-c ARM: tegra: colibri_t20: use high speed uart driver ARM: tegra: colibri_t20: iris: add gpio wakeup key ARM: tegra: colibri_t20: iris: add dr_mode property ARM: tegra: colibri_t20: annotate/rename lm95245 temperature sensor ARM: tegra: colibri_t20: add i2c-thermtrip ARM: tegra: colibri_t20: add gpio hog to unreset usb ethernet chip ARM: tegra: colibri_t20: add gpio hogs for gmi_wr_n buffers ARM: tegra: colibri_t20: annotate/move sd card detect ARM: tegra: colibri_t20: add compatibility comment ARM: tegra: colibri_t20: simplify model and compatible properties ARM: tegra: colibri_t20: iris: simplify model and compatible properties ARM: tegra: colibri_t20: iris: add colibri ssp support ARM: tegra: colibri_t20: add evaluation board device tree arch/arm/boot/dts/Makefile| 1 + arch/arm/boot/dts/tegra20-colibri-eval-v3.dts | 266 +++ arch/arm/boot/dts/tegra20-colibri-iris.dts| 198 ++-- arch/arm/boot/dts/tegra20-colibri.dtsi| 629 +- 4 files changed, 858 insertions(+), 236 deletions(-) create mode 100644 arch/arm/boot/dts/tegra20-colibri-eval-v3.dts -- 2.14.4
[PATCH 08/31] ARM: tegra: colibri_t20: regulator clean-up
From: Marcel Ziswiler
Just cosmetic regulator clean-up.
Signed-off-by: Marcel Ziswiler
---
arch/arm/boot/dts/tegra20-colibri-iris.dts | 20 ++--
arch/arm/boot/dts/tegra20-colibri.dtsi | 147 +++--
2 files changed, 66 insertions(+), 101 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts
b/arch/arm/boot/dts/tegra20-colibri-iris.dts
index 3d430fa93e8c..6f89a417b0f2 100644
--- a/arch/arm/boot/dts/tegra20-colibri-iris.dts
+++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts
@@ -104,16 +104,14 @@
no-1-8-v;
};
- regulators {
- regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "usb_host_vbus";
- regulator-min-microvolt = <500>;
- regulator-max-microvolt = <500>;
- regulator-boot-on;
- regulator-always-on;
- gpio = < TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
- };
+ /* USBH_PEN resp. USB_P_EN */
+ reg_usbh_vbus: regulator-usbh-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_USB1";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regulator-boot-on;
+ regulator-always-on;
+ gpio = < TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
};
};
diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi
b/arch/arm/boot/dts/tegra20-colibri.dtsi
index c060b58cb490..1cf64f197c08 100644
--- a/arch/arm/boot/dts/tegra20-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri.dtsi
@@ -19,8 +19,8 @@
nvidia,ddc-i2c-bus = <_ddc>;
nvidia,hpd-gpio =
< TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
- pll-supply = <_pll_reg>;
- vdd-supply = <_vdd_reg>;
+ pll-supply = <_1v8_avdd_hdmi_pll>;
+ vdd-supply = <_3v3_avdd_hdmi>;
};
};
@@ -260,49 +260,38 @@
#gpio-cells = <2>;
gpio-controller;
- sys-supply = <_3v3_reg>;
- vin-sm0-supply = <_reg>;
- vin-sm1-supply = <_reg>;
- vin-sm2-supply = <_reg>;
- vinldo01-supply = <_reg>;
- vinldo23-supply = <_3v3_reg>;
- vinldo4-supply = <_3v3_reg>;
- vinldo678-supply = <_3v3_reg>;
- vinldo9-supply = <_3v3_reg>;
+ sys-supply = <_module_3v3>;
+ vin-sm0-supply = <_3v3_vsys>;
+ vin-sm1-supply = <_3v3_vsys>;
+ vin-sm2-supply = <_3v3_vsys>;
+ vinldo01-supply = <_1v8_vdd_ddr2>;
+ vinldo23-supply = <_module_3v3>;
+ vinldo4-supply = <_module_3v3>;
+ vinldo678-supply = <_module_3v3>;
+ vinldo9-supply = <_module_3v3>;
regulators {
- #address-cells = <1>;
- #size-cells = <0>;
-
- sys_reg: regulator@0 {
- reg = <0>;
- regulator-compatible = "sys";
- regulator-name = "vdd_sys";
+ reg_3v3_vsys: sys {
+ regulator-name = "VSYS_3.3V";
regulator-always-on;
};
- regulator@1 {
- reg = <1>;
- regulator-compatible = "sm0";
- regulator-name = "vdd_sm0,vdd_core";
+ sm0 {
+ regulator-name = "VDD_CORE_1.2V";
regulator-min-microvolt = <120>;
regulator-max-microvolt = <120>;
regulator-always-on;
};
- regulator@2 {
- reg = <2>;
- regulator-compatible = "sm1";
- regulator-name = "vdd_sm1,vdd_cpu";
+ sm1 {
+ regulator-name = "VDD_CPU_1.0V";
regulator-min-microvolt = <100>;
regulator-max-microvolt = <100>;
[PATCH 04/31] ARM: tegra: colibri_t20: iris: add missing aliases
From: Marcel Ziswiler
Add rtc0 being the ultra low-power I2C one as found on the carrier board
and the 3rd UART being NVIDIA's UARTB.
Signed-off-by: Marcel Ziswiler
---
arch/arm/boot/dts/tegra20-colibri-iris.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts
b/arch/arm/boot/dts/tegra20-colibri-iris.dts
index cbf1f4d76813..cc9e372a3b58 100644
--- a/arch/arm/boot/dts/tegra20-colibri-iris.dts
+++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts
@@ -73,6 +73,11 @@
};
};
+ /* GEN2_I2C: unused */
+
+ /* CAM_I2C (I2C3): unused */
+
+ /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */
i2c_ddc: i2c@7000c400 {
status = "okay";
};
--
2.14.4
[RFC PATCH 0/6] x86: text_poke() fixes
This patch-set addresses some issues that were raised in the recent correspondence and might affect the security and the correctness of code patching. (Note that patching performance is not addressed by this patch-set). The main issue that the patches deal with is the fact that the fixmap PTEs that are used for patching are available for access from other cores and might be exploited. They are not even flushed from the TLB in remote cores, so the risk is even higher. Address this issue by introducing a temporary mm that is only used during patching. Unfortunately, due to init ordering, fixmap is still used during boot-time patching. Future patches can eliminate the need for it. The second issue is the missing lockdep assertion to ensure text_mutex is taken. It is actually not always taken, so fix the instances that were found not to take the lock (although they should be safe even without taking the lock). Finally, try to be more conservative and to map a single page, instead of two, when possible. This helps both security and performance. In addition, there is some cleanup of the patching code to make it more readable. [ Andy: please provide your SOB for your patch ] Cc: Andy Lutomirski Cc: Masami Hiramatsu Cc: Kees Cook Cc: Peter Zijlstra Andy Lutomirski (1): x86/mm: temporary mm struct Nadav Amit (5): x86/alternative: assert text_mutex is taken fork: provide a function for copying init_mm x86/alternatives: initializing temporary mm for patching x86/alternatives: use temporary mm for text poking x86/alternatives: remove text_poke() return value arch/x86/include/asm/mmu_context.h | 20 arch/x86/include/asm/pgtable.h | 4 + arch/x86/include/asm/text-patching.h | 4 +- arch/x86/kernel/alternative.c| 157 +++ arch/x86/kernel/kgdb.c | 9 ++ arch/x86/mm/init_64.c| 35 ++ include/asm-generic/pgtable.h| 4 + include/linux/sched/task.h | 1 + init/main.c | 1 + kernel/fork.c| 24 +++- 10 files changed, 230 insertions(+), 29 deletions(-) -- 2.17.1
[RFC PATCH 5/6] x86/alternatives: use temporary mm for text poking
text_poke() can potentially compromise the security as it sets temporary
PTEs in the fixmap. These PTEs might be used to rewrite the kernel code
from other cores accidentally or maliciously, if an attacker gains the
ability to write onto kernel memory.
Moreover, since remote TLBs are not flushed after the temporary PTEs are
removed, the time-window in which the code is writable is not limited if
the fixmap PTEs - maliciously or accidentally - are cached in the TLB.
To address these potential security hazards, we use a temporary mm for
patching the code. Unfortunately, the temporary-mm cannot be initialized
early enough during the init, and as a result x86_late_time_init() needs
to use text_poke() before it can be initialized. text_poke() therefore
keeps the two poking versions - using fixmap and using temporary mm -
and uses them accordingly.
More adventurous developers can try to reorder the init sequence or use
text_poke_early() instead of text_poke() to remove the use of fixmap for
patching completely.
Finally, text_poke() is also not conservative enough when mapping pages,
as it always tries to map 2 pages, even when a single one is sufficient.
So try to be more conservative, and do not map more than needed.
Cc: Andy Lutomirski
Cc: Masami Hiramatsu
Cc: Kees Cook
Cc: Peter Zijlstra
Signed-off-by: Nadav Amit
---
arch/x86/kernel/alternative.c | 154 +-
1 file changed, 133 insertions(+), 21 deletions(-)
diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index 916c11b410c4..0feac3dfabe9 100644
--- a/arch/x86/kernel/alternative.c
+++ b/arch/x86/kernel/alternative.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -674,6 +675,113 @@ void *__init_or_module text_poke_early(void *addr, const
void *opcode,
return addr;
}
+/**
+ * text_poke_fixmap - poke using the fixmap.
+ *
+ * Fallback function for poking the text using the fixmap. It is used during
+ * early boot and in the rare case in which initialization of safe poking
fails.
+ *
+ * Poking in this manner should be avoided, since it allows other cores to use
+ * the fixmap entries, and can be exploited by an attacker to overwrite the
code
+ * (assuming he gained the write access through another bug).
+ */
+static void text_poke_fixmap(void *addr, const void *opcode, size_t len,
+struct page *pages[2])
+{
+ u8 *vaddr;
+
+ set_fixmap(FIX_TEXT_POKE0, page_to_phys(pages[0]));
+ if (pages[1])
+ set_fixmap(FIX_TEXT_POKE1, page_to_phys(pages[1]));
+ vaddr = (u8 *)fix_to_virt(FIX_TEXT_POKE0);
+ memcpy(vaddr + offset_in_page(addr), opcode, len);
+
+ /*
+* clear_fixmap() performs a TLB flush, so no additional TLB
+* flush is needed.
+*/
+ clear_fixmap(FIX_TEXT_POKE0);
+ if (pages[1])
+ clear_fixmap(FIX_TEXT_POKE1);
+ sync_core();
+ /* Could also do a CLFLUSH here to speed up CPU recovery; but
+ that causes hangs on some VIA CPUs. */
+}
+
+__ro_after_init struct mm_struct *poking_mm;
+__ro_after_init unsigned long poking_addr;
+
+/**
+ * text_poke_safe() - Pokes the text using a separate address space.
+ *
+ * This is the preferable way for patching the kernel after boot, as it does
not
+ * allow other cores to accidentally or maliciously modify the code using the
+ * temporary PTEs.
+ */
+static void text_poke_safe(void *addr, const void *opcode, size_t len,
+ struct page *pages[2])
+{
+ temporary_mm_state_t prev;
+ pte_t pte, *ptep;
+ spinlock_t *ptl;
+
+ /*
+* The lock is not really needed, but this allows to avoid open-coding.
+*/
+ ptep = get_locked_pte(poking_mm, poking_addr, );
+
+ pte = mk_pte(pages[0], PAGE_KERNEL);
+ set_pte_at(poking_mm, poking_addr, ptep, pte);
+
+ if (pages[1]) {
+ pte = mk_pte(pages[1], PAGE_KERNEL);
+ set_pte_at(poking_mm, poking_addr + PAGE_SIZE, ptep + 1, pte);
+ }
+
+ /*
+* Loading the temporary mm behaves as a compiler barrier, which
+* guarantees that the PTE will be set at the time memcpy() is done.
+*/
+ prev = use_temporary_mm(poking_mm);
+
+ memcpy((u8 *)poking_addr + offset_in_page(addr), opcode, len);
+
+ /*
+* Ensure that the PTE is only cleared after copying is done by using a
+* compiler barrier.
+*/
+ barrier();
+
+ pte_clear(poking_mm, poking_addr, ptep);
+
+ /*
+* __flush_tlb_one_user() performs a redundant TLB flush when PTI is on,
+* as it also flushes the corresponding "user" address spaces, which
+* does not exist.
+*
+* Poking, however, is already very inefficient since it does not try to
+* batch updates, so we ignore this problem for the time being.
+*
+* Since the
[RFC PATCH 6/6] x86/alternatives: remove text_poke() return value
The return value of text_poke() is meaningless - it is one of the
function inputs. One day someone may allow the callers to deal with
text_poke() failures, if those actually happen.
In the meanwhile, remove the return value.
Cc: Andy Lutomirski
Cc: Masami Hiramatsu
Cc: Kees Cook
Cc: Peter Zijlstra
Signed-off-by: Nadav Amit
---
arch/x86/include/asm/text-patching.h | 2 +-
arch/x86/kernel/alternative.c| 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/text-patching.h
b/arch/x86/include/asm/text-patching.h
index ffe7902cc326..1f73f71b4de2 100644
--- a/arch/x86/include/asm/text-patching.h
+++ b/arch/x86/include/asm/text-patching.h
@@ -34,7 +34,7 @@ extern void *text_poke_early(void *addr, const void *opcode,
size_t len);
* On the local CPU you need to be protected again NMI or MCE handlers seeing
an
* inconsistent instruction while you patch.
*/
-extern void *text_poke(void *addr, const void *opcode, size_t len);
+extern void text_poke(void *addr, const void *opcode, size_t len);
extern int poke_int3_handler(struct pt_regs *regs);
extern void *text_poke_bp(void *addr, const void *opcode, size_t len, void
*handler);
extern int after_bootmem;
diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index 0feac3dfabe9..45b7fdeaed90 100644
--- a/arch/x86/kernel/alternative.c
+++ b/arch/x86/kernel/alternative.c
@@ -795,7 +795,7 @@ static void text_poke_safe(void *addr, const void *opcode,
size_t len,
*
* Note: Must be called under text_mutex.
*/
-void *text_poke(void *addr, const void *opcode, size_t len)
+void text_poke(void *addr, const void *opcode, size_t len)
{
bool cross_page_boundary = offset_in_page(addr) + len > PAGE_SIZE;
struct page *pages[2] = {0};
--
2.17.1
[RFC PATCH 2/6] x86/mm: temporary mm struct
From: Andy Lutomirski
Sometimes we want to set a temporary page-table entries (PTEs) in one of
the cores, without allowing other cores to use - even speculatively -
these mappings. There are two benefits for doing so:
(1) Security: if sensitive PTEs are set, temporary mm prevents their use
in other cores. This hardens the security as it prevents exploding a
dangling pointer to overwrite sensitive data using the sensitive PTE.
(2) Avoiding TLB shootdowns: the PTEs do not need to be flushed in
remote page-tables.
To do so a temporary mm_struct can be used. Mappings which are private
for this mm can be set in the userspace part of the address-space.
During the whole time in which the temporary mm is loaded, interrupts
must be disabled.
The first use-case for temporary PTEs, which will follow, is for poking
the kernel text.
[ Commit message was written by Nadav ]
Cc: Andy Lutomirski
Cc: Masami Hiramatsu
Cc: Kees Cook
Cc: Peter Zijlstra
Signed-off-by: Nadav Amit
---
arch/x86/include/asm/mmu_context.h | 20
1 file changed, 20 insertions(+)
diff --git a/arch/x86/include/asm/mmu_context.h
b/arch/x86/include/asm/mmu_context.h
index eeeb9289c764..96afc8c0cf15 100644
--- a/arch/x86/include/asm/mmu_context.h
+++ b/arch/x86/include/asm/mmu_context.h
@@ -338,4 +338,24 @@ static inline unsigned long __get_current_cr3_fast(void)
return cr3;
}
+typedef struct {
+ struct mm_struct *prev;
+} temporary_mm_state_t;
+
+static inline temporary_mm_state_t use_temporary_mm(struct mm_struct *mm)
+{
+ temporary_mm_state_t state;
+
+ lockdep_assert_irqs_disabled();
+ state.prev = this_cpu_read(cpu_tlbstate.loaded_mm);
+ switch_mm_irqs_off(NULL, mm, current);
+ return state;
+}
+
+static inline void unuse_temporary_mm(temporary_mm_state_t prev)
+{
+ lockdep_assert_irqs_disabled();
+ switch_mm_irqs_off(NULL, prev.prev, current);
+}
+
#endif /* _ASM_X86_MMU_CONTEXT_H */
--
2.17.1
[RFC PATCH 4/6] x86/alternatives: initializing temporary mm for patching
To prevent improper use of the PTEs that are used for text patching, we
want to use a temporary mm struct. We initailize it by copying the init
mm.
The address that will be used for patching is taken from the lower area
that is usually used for the task memory. Doing so prevents the need to
frequently synchronize the temporary-mm (e.g., when BPF programs are
installed), since different PGDs are used for the task memory.
Finally, we randomize the address of the PTEs to harden against exploits
that use these PTEs.
Cc: Masami Hiramatsu
Cc: Kees Cook
Cc: Peter Zijlstra
Suggested-by: Andy Lutomirski
Signed-off-by: Nadav Amit
---
arch/x86/include/asm/pgtable.h | 4
arch/x86/include/asm/text-patching.h | 2 ++
arch/x86/mm/init_64.c| 35
include/asm-generic/pgtable.h| 4
init/main.c | 1 +
5 files changed, 46 insertions(+)
diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h
index e4ffa565a69f..c65d2b146ff6 100644
--- a/arch/x86/include/asm/pgtable.h
+++ b/arch/x86/include/asm/pgtable.h
@@ -1022,6 +1022,10 @@ static inline void __meminit
init_trampoline_default(void)
/* Default trampoline pgd value */
trampoline_pgd_entry = init_top_pgt[pgd_index(__PAGE_OFFSET)];
}
+
+void __init poking_init(void);
+#define poking_init poking_init
+
# ifdef CONFIG_RANDOMIZE_MEMORY
void __meminit init_trampoline(void);
# else
diff --git a/arch/x86/include/asm/text-patching.h
b/arch/x86/include/asm/text-patching.h
index e85ff65c43c3..ffe7902cc326 100644
--- a/arch/x86/include/asm/text-patching.h
+++ b/arch/x86/include/asm/text-patching.h
@@ -38,5 +38,7 @@ extern void *text_poke(void *addr, const void *opcode, size_t
len);
extern int poke_int3_handler(struct pt_regs *regs);
extern void *text_poke_bp(void *addr, const void *opcode, size_t len, void
*handler);
extern int after_bootmem;
+extern __ro_after_init struct mm_struct *poking_mm;
+extern __ro_after_init unsigned long poking_addr;
#endif /* _ASM_X86_TEXT_PATCHING_H */
diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c
index dd519f372169..ed4a46a89946 100644
--- a/arch/x86/mm/init_64.c
+++ b/arch/x86/mm/init_64.c
@@ -33,6 +33,7 @@
#include
#include
#include
+#include
#include
#include
@@ -54,6 +55,7 @@
#include
#include
#include
+#include
#include "mm_internal.h"
@@ -1389,6 +1391,39 @@ unsigned long memory_block_size_bytes(void)
return memory_block_size_probed;
}
+/*
+ * Initialize an mm_struct to be used during poking and a pointer to be used
+ * during patching. If anything fails during initialization, poking will be
done
+ * using the fixmap, which is unsafe, so warn the user about it.
+ */
+void __init poking_init(void)
+{
+ unsigned long poking_addr;
+
+ poking_mm = copy_init_mm();
+ if (!poking_mm)
+ goto error;
+
+ /*
+* Randomize the poking address, but make sure that the following page
+* will be mapped at the same PMD. We need 2 pages, so find space for 3,
+* and adjust the address if the PMD ends after the first one.
+*/
+ poking_addr = TASK_UNMAPPED_BASE +
+ (kaslr_get_random_long("Poking") & PAGE_MASK) %
+ (TASK_SIZE - TASK_UNMAPPED_BASE - 3 * PAGE_SIZE);
+
+ if (((poking_addr + PAGE_SIZE) & ~PMD_MASK) == 0)
+ poking_addr += PAGE_SIZE;
+
+ return;
+error:
+ if (poking_mm)
+ mmput(poking_mm);
+ poking_mm = NULL;
+ pr_err("x86/mm: error setting a separate poking address space\n");
+}
+
#ifdef CONFIG_SPARSEMEM_VMEMMAP
/*
* Initialise the sparsemem vmemmap using huge-pages at the PMD level.
diff --git a/include/asm-generic/pgtable.h b/include/asm-generic/pgtable.h
index 88ebc6102c7c..c66579d0ee67 100644
--- a/include/asm-generic/pgtable.h
+++ b/include/asm-generic/pgtable.h
@@ -,6 +,10 @@ static inline bool arch_has_pfn_modify_check(void)
#ifndef PAGE_KERNEL_EXEC
# define PAGE_KERNEL_EXEC PAGE_KERNEL
+
+#ifndef poking_init
+static inline void poking_init(void) { }
+#endif
#endif
#endif /* !__ASSEMBLY__ */
diff --git a/init/main.c b/init/main.c
index 18f8f0140fa0..6754ff2687c8 100644
--- a/init/main.c
+++ b/init/main.c
@@ -725,6 +725,7 @@ asmlinkage __visible void __init start_kernel(void)
taskstats_init_early();
delayacct_init();
+ poking_init();
check_bugs();
acpi_subsystem_init();
--
2.17.1
[RFC PATCH 1/6] x86/alternative: assert text_mutex is taken
Use lockdep to ensure that text_mutex is taken when text_poke() is
called.
Actually it is not always taken, specifically when it is called by kgdb,
so take the lock in these cases.
Cc: Andy Lutomirski
Cc: Masami Hiramatsu
Cc: Kees Cook
Suggested-by: Peter Zijlstra
Signed-off-by: Nadav Amit
---
arch/x86/kernel/alternative.c | 1 +
arch/x86/kernel/kgdb.c| 9 +
2 files changed, 10 insertions(+)
diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index 014f214da581..916c11b410c4 100644
--- a/arch/x86/kernel/alternative.c
+++ b/arch/x86/kernel/alternative.c
@@ -699,6 +699,7 @@ void *text_poke(void *addr, const void *opcode, size_t len)
* pages as they are not yet initialized.
*/
BUG_ON(!after_bootmem);
+ lockdep_assert_held(_mutex);
if (!core_kernel_text((unsigned long)addr)) {
pages[0] = vmalloc_to_page(addr);
diff --git a/arch/x86/kernel/kgdb.c b/arch/x86/kernel/kgdb.c
index 8e36f249646e..60b99c76086c 100644
--- a/arch/x86/kernel/kgdb.c
+++ b/arch/x86/kernel/kgdb.c
@@ -768,8 +768,12 @@ int kgdb_arch_set_breakpoint(struct kgdb_bkpt *bpt)
*/
if (mutex_is_locked(_mutex))
return -EBUSY;
+
+ /* Take the mutex to avoid lockdep assertion failures. */
+ mutex_lock(_mutex);
text_poke((void *)bpt->bpt_addr, arch_kgdb_ops.gdb_bpt_instr,
BREAK_INSTR_SIZE);
+ mutex_unlock(_mutex);
err = probe_kernel_read(opc, (char *)bpt->bpt_addr, BREAK_INSTR_SIZE);
if (err)
return err;
@@ -793,7 +797,12 @@ int kgdb_arch_remove_breakpoint(struct kgdb_bkpt *bpt)
*/
if (mutex_is_locked(_mutex))
goto knl_write;
+
+ /* Take the mutex to avoid lockdep assertion failures. */
+ mutex_lock(_mutex);
text_poke((void *)bpt->bpt_addr, bpt->saved_instr, BREAK_INSTR_SIZE);
+ mutex_unlock(_mutex);
+
err = probe_kernel_read(opc, (char *)bpt->bpt_addr, BREAK_INSTR_SIZE);
if (err || memcmp(opc, bpt->saved_instr, BREAK_INSTR_SIZE))
goto knl_write;
--
2.17.1
[PATCH 09/31] ARM: tegra: colibri_t20: add missing regulators
From: Marcel Ziswiler
Add missing regulators:
- reg_lan_v_bus being USB Ethernet chip vbus supply
- carrier board reg_3v3 to be used as backlight and panel power supply
- carrier board HDMI supply being reg_5v0
- reg_usbc_vbus being the USB vbus supply of the EHCI instance 0
Signed-off-by: Marcel Ziswiler
---
arch/arm/boot/dts/tegra20-colibri-iris.dts | 28 ++--
arch/arm/boot/dts/tegra20-colibri.dtsi | 1 +
2 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts
b/arch/arm/boot/dts/tegra20-colibri-iris.dts
index 6f89a417b0f2..9f0a819c68f2 100644
--- a/arch/arm/boot/dts/tegra20-colibri-iris.dts
+++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts
@@ -23,6 +23,7 @@
host1x@5000 {
hdmi@5428 {
status = "okay";
+ hdmi-supply = <_5v0>;
};
};
@@ -88,6 +89,7 @@
usb-phy@c500 {
status = "okay";
+ vbus-supply = <_usbc_vbus>;
};
usb@c5008000 {
@@ -96,6 +98,7 @@
usb-phy@c5008000 {
status = "okay";
+ vbus-supply = <_usbh_vbus>;
};
sdhci@c8000600 {
@@ -104,14 +107,35 @@
no-1-8-v;
};
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+
+ reg_5v0: regulator-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ };
+
+ reg_usbc_vbus: regulator-usbc-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_USB2";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <_5v0>;
+ };
+
/* USBH_PEN resp. USB_P_EN */
reg_usbh_vbus: regulator-usbh-vbus {
compatible = "regulator-fixed";
regulator-name = "VCC_USB1";
regulator-min-microvolt = <500>;
regulator-max-microvolt = <500>;
- regulator-boot-on;
- regulator-always-on;
gpio = < TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
+ vin-supply = <_5v0>;
};
};
diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi
b/arch/arm/boot/dts/tegra20-colibri.dtsi
index 1cf64f197c08..5e98f225322b 100644
--- a/arch/arm/boot/dts/tegra20-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri.dtsi
@@ -471,6 +471,7 @@
status = "okay";
nvidia,phy-reset-gpio = < TEGRA_GPIO(V, 1)
GPIO_ACTIVE_LOW>;
+ vbus-supply = <_lan_v_bus>;
};
sdhci@c8000600 {
--
2.14.4
[RFC PATCH 3/6] fork: provide a function for copying init_mm
Provide a function for copying init_mm. This function will be later used
for setting a temporary mm.
Cc: Andy Lutomirski
Cc: Masami Hiramatsu
Cc: Kees Cook
Cc: Peter Zijlstra
Signed-off-by: Nadav Amit
---
include/linux/sched/task.h | 1 +
kernel/fork.c | 24 ++--
2 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/include/linux/sched/task.h b/include/linux/sched/task.h
index 108ede99e533..ac0a675678f5 100644
--- a/include/linux/sched/task.h
+++ b/include/linux/sched/task.h
@@ -74,6 +74,7 @@ extern void exit_itimers(struct signal_struct *);
extern long _do_fork(unsigned long, unsigned long, unsigned long, int __user
*, int __user *, unsigned long);
extern long do_fork(unsigned long, unsigned long, unsigned long, int __user *,
int __user *);
struct task_struct *fork_idle(int);
+struct mm_struct *copy_init_mm(void);
extern pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
extern long kernel_wait4(pid_t, int __user *, int, struct rusage *);
diff --git a/kernel/fork.c b/kernel/fork.c
index d896e9ca38b0..a1c637b903c1 100644
--- a/kernel/fork.c
+++ b/kernel/fork.c
@@ -1254,13 +1254,20 @@ void mm_release(struct task_struct *tsk, struct
mm_struct *mm)
complete_vfork_done(tsk);
}
-/*
- * Allocate a new mm structure and copy contents from the
- * mm structure of the passed in task structure.
+/**
+ * dup_mm() - duplicates an existing mm structure
+ * @tsk: the task_struct with which the new mm will be associated.
+ * @oldmm: the mm to duplicate.
+ *
+ * Allocates a new mm structure and copy contents from the provided
+ * @oldmm structure.
+ *
+ * Return: the duplicated mm or NULL on failure.
*/
-static struct mm_struct *dup_mm(struct task_struct *tsk)
+static struct mm_struct *dup_mm(struct task_struct *tsk,
+ struct mm_struct *oldmm)
{
- struct mm_struct *mm, *oldmm = current->mm;
+ struct mm_struct *mm;
int err;
mm = allocate_mm();
@@ -1327,7 +1334,7 @@ static int copy_mm(unsigned long clone_flags, struct
task_struct *tsk)
}
retval = -ENOMEM;
- mm = dup_mm(tsk);
+ mm = dup_mm(tsk, current->mm);
if (!mm)
goto fail_nomem;
@@ -2127,6 +2134,11 @@ struct task_struct *fork_idle(int cpu)
return task;
}
+struct mm_struct *copy_init_mm(void)
+{
+ return dup_mm(NULL, _mm);
+}
+
/*
* Ok, this is the main fork-routine.
*
--
2.17.1
[PATCH 16/31] ARM: tegra: colibri_t20: iris: display controller rgb panel support
From: Marcel Ziswiler
Add display controller parallel RGB panel support incl. backlight PWM.
Signed-off-by: Marcel Ziswiler
---
arch/arm/boot/dts/tegra20-colibri-iris.dts | 31 ++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts
b/arch/arm/boot/dts/tegra20-colibri-iris.dts
index be531d4c2ae8..e5e26a6c2861 100644
--- a/arch/arm/boot/dts/tegra20-colibri-iris.dts
+++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts
@@ -21,6 +21,13 @@
};
host1x@5000 {
+ dc@5420 {
+ rgb {
+ status = "okay";
+ nvidia,panel = <>;
+ };
+ };
+
hdmi@5428 {
status = "okay";
hdmi-supply = <_5v0>;
@@ -99,6 +106,10 @@
status = "okay";
};
+ pwm@7000a000 {
+ status = "okay";
+ };
+
/*
* GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
* board)
@@ -149,6 +160,26 @@
no-1-8-v;
};
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ brightness-levels = <255 128 64 32 16 8 4 0>;
+ default-brightness-level = <6>;
+ /* BL_ON */
+ enable-gpios = < TEGRA_GPIO(T, 4) GPIO_ACTIVE_HIGH>;
+ power-supply = <_3v3>;
+ pwms = < 0 500>; /* PWM */
+ };
+
+ panel: panel {
+ /*
+* edt,et057090dhu: EDT 5.7" LCD TFT
+* edt,et070080dh6: EDT 7.0" LCD TFT
+*/
+ compatible = "edt,et057090dhu", "simple-panel";
+ backlight = <>;
+ power-supply = <_3v3>;
+ };
+
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3.3V";
--
2.14.4
[PATCH 14/31] ARM: tegra: colibri_t20: pinmux clean-up
From: Marcel Ziswiler
Just cosmetic pinmux clean-up.
Signed-off-by: Marcel Ziswiler
---
arch/arm/boot/dts/tegra20-colibri-iris.dts | 10 +-
arch/arm/boot/dts/tegra20-colibri.dtsi | 283 -
2 files changed, 200 insertions(+), 93 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts
b/arch/arm/boot/dts/tegra20-colibri-iris.dts
index 194f40646a83..f2f01b0d9336 100644
--- a/arch/arm/boot/dts/tegra20-colibri-iris.dts
+++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts
@@ -29,23 +29,23 @@
pinmux@7014 {
state_default: pinmux {
- hdint {
+ ddc {
nvidia,tristate = ;
};
- i2cddc {
+ hotplug_detect {
nvidia,tristate = ;
};
- sdio4 {
+ mmc {
nvidia,tristate = ;
};
- uarta {
+ uart_a {
nvidia,tristate = ;
};
- uartd {
+ uart_b {
nvidia,tristate = ;
};
};
diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi
b/arch/arm/boot/dts/tegra20-colibri.dtsi
index ba84184e09b8..2e6ecc3040f7 100644
--- a/arch/arm/boot/dts/tegra20-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri.dtsi
@@ -29,175 +29,282 @@
pinctrl-0 = <_default>;
state_default: pinmux {
+ /* Analogue Audio AC97 to WM9712 (On-module) */
audio_refclk {
nvidia,pins = "cdev1";
nvidia,function = "plla_out";
nvidia,pull = ;
nvidia,tristate = ;
};
- crt {
- nvidia,pins = "crtp";
- nvidia,function = "crt";
- nvidia,pull = ;
- nvidia,tristate = ;
- };
dap3 {
nvidia,pins = "dap3";
nvidia,function = "dap3";
nvidia,pull = ;
nvidia,tristate = ;
};
- displaya {
- nvidia,pins = "ld0", "ld1", "ld2", "ld3",
- "ld4", "ld5", "ld6", "ld7", "ld8",
- "ld9", "ld10", "ld11", "ld12", "ld13",
- "ld14", "ld15", "ld16", "ld17",
- "lhs", "lpw0", "lpw2", "lsc0",
- "lsc1", "lsck", "lsda", "lspi", "lvs";
- nvidia,function = "displaya";
- nvidia,tristate = ;
- };
- gpio_dte {
- nvidia,pins = "dte";
- nvidia,function = "rsvd1";
- nvidia,pull = ;
- nvidia,tristate = ;
- };
- gpio_gmi {
- nvidia,pins = "ata", "atc", "atd", "ate",
- "dap1", "dap2", "dap4", "gpu", "irrx",
- "irtx", "spia", "spib", "spic";
- nvidia,function = "gmi";
+
+ /*
+* AC97_RESET, ULPI_RESET, AC97_INT aka WM9712 GENIRQ
+* (All on-module), SODIMM Pin 45 Wakeup
+*/
+ gpio_uac {
+ nvidia,pins = "uac";
+ nvidia,function = "rsvd2";
nvidia,pull = ;
nvidia,tristate = ;
};
+
+ /*
+* Buffer Enables for nPWE and RDnWR (On-module,
+* see GPIO hogging further down below)
+*/
gpio_pta {
nvidia,pins = "pta";
nvidia,function = "rsvd4";
nvidia,pull = ;
nvidia,tristate = ;
};
- gpio_uac {
- nvidia,pins = "uac";
- nvidia,function = "rsvd2";
- nvidia,pull = ;
+
+ /*
+*
[PATCH 05/31] ARM: tegra: colibri_t20: add local-mac-address property
From: Marcel Ziswiler
Add empty local-mac-address property to be filled in by boot loader
(e.g. U-Boot).
Signed-off-by: Marcel Ziswiler
---
arch/arm/boot/dts/tegra20-colibri.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi
b/arch/arm/boot/dts/tegra20-colibri.dtsi
index e34ab4a76158..ad816fa827f7 100644
--- a/arch/arm/boot/dts/tegra20-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri.dtsi
@@ -482,6 +482,13 @@
status = "okay";
nvidia,phy-reset-gpio = < TEGRA_GPIO(V, 1)
GPIO_ACTIVE_LOW>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ asix@1 {
+ reg = <1>;
+ local-mac-address = [00 00 00 00 00 00];
+ };
};
usb-phy@c5004000 {
--
2.14.4
[PATCH 02/31] ARM: tegra: colibri_t20: iris: integrate i2c real time clock support
From: Marcel Ziswiler
Integrate support for GEN1_I2C aka I2C_SDA/SCL on SODIMM pin 194/196 and
the M41T0M6 real time clock on the carrier board.
Signed-off-by: Marcel Ziswiler
---
arch/arm/boot/dts/tegra20-colibri-iris.dts | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts
b/arch/arm/boot/dts/tegra20-colibri-iris.dts
index 496b96e229d2..b6d05da8c93c 100644
--- a/arch/arm/boot/dts/tegra20-colibri-iris.dts
+++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts
@@ -56,6 +56,21 @@
status = "okay";
};
+ /*
+* GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
+* board)
+*/
+ i2c@7000c000 {
+ status = "okay";
+ clock-frequency = <40>;
+
+ /* M41T0M6 real time clock on carrier board */
+ rtc@68 {
+ compatible = "st,m41t0";
+ reg = <0x68>;
+ };
+ };
+
i2c_ddc: i2c@7000c400 {
status = "okay";
};
--
2.14.4
[PATCH 10/31] ARM: tegra: colibri_t20: annotate usb ehci instances
From: Marcel Ziswiler
Annotate USB EHCI instances.
Signed-off-by: Marcel Ziswiler
---
arch/arm/boot/dts/tegra20-colibri-iris.dts | 2 ++
arch/arm/boot/dts/tegra20-colibri.dtsi | 1 +
2 files changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts
b/arch/arm/boot/dts/tegra20-colibri-iris.dts
index 9f0a819c68f2..194f40646a83 100644
--- a/arch/arm/boot/dts/tegra20-colibri-iris.dts
+++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts
@@ -83,6 +83,7 @@
status = "okay";
};
+ /* EHCI instance 0: USB1_DP/N -> USBC_P/N */
usb@c500 {
status = "okay";
};
@@ -92,6 +93,7 @@
vbus-supply = <_usbc_vbus>;
};
+ /* EHCI instance 2: USB3_DP/N -> USBH_P/N */
usb@c5008000 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi
b/arch/arm/boot/dts/tegra20-colibri.dtsi
index 5e98f225322b..77e99caf5606 100644
--- a/arch/arm/boot/dts/tegra20-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri.dtsi
@@ -454,6 +454,7 @@
};
};
+ /* EHCI instance 1: ULPI PHY -> AX88772B (On-module) */
usb@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = < TEGRA_GPIO(V, 1)
--
2.14.4
[PATCH 13/31] ARM: tegra: colibri_t20: update sound nvidia,model
From: Marcel Ziswiler
Update sound nvidia,model to be more in-line with our other device
trees.
Signed-off-by: Marcel Ziswiler
---
arch/arm/boot/dts/tegra20-colibri.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi
b/arch/arm/boot/dts/tegra20-colibri.dtsi
index 5559008efc5f..ba84184e09b8 100644
--- a/arch/arm/boot/dts/tegra20-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri.dtsi
@@ -507,7 +507,7 @@
sound {
compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
"nvidia,tegra-audio-wm9712";
- nvidia,model = "Colibri T20 AC97 Audio";
+ nvidia,model = "Toradex Colibri T20";
nvidia,audio-routing =
"Headphone", "HPOUTL",
"Headphone", "HPOUTR",
--
2.14.4
[PATCH 03/31] ARM: tegra: colibri_t20: iris: annotate i2c busses
From: Marcel Ziswiler
Annotate I2C busses: GEN2_I2C and CAM_I2C (I2C3) being unused and
DDC_CLOCK/DATA on X3 pin 15/16 e.g. used for display EDID.
Signed-off-by: Marcel Ziswiler
---
arch/arm/boot/dts/tegra20-colibri-iris.dts | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts
b/arch/arm/boot/dts/tegra20-colibri-iris.dts
index b6d05da8c93c..cbf1f4d76813 100644
--- a/arch/arm/boot/dts/tegra20-colibri-iris.dts
+++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts
@@ -8,10 +8,12 @@
compatible = "toradex,iris", "toradex,colibri_t20-512",
"nvidia,tegra20";
aliases {
- rtc0 = "/i2c@7000d000/tps6586x@34";
- rtc1 = "/rtc@7000e000";
+ rtc0 = "/i2c@7000c000/rtc@68";
+ rtc1 = "/i2c@7000d000/tps6586x@34";
+ rtc2 = "/rtc@7000e000";
serial0 =
serial1 =
+ serial2 =
};
chosen {
--
2.14.4
[PATCH 06/31] ARM: tegra: colibri_t20: reorder host1x/hdmi properties
From: Marcel Ziswiler
Reorder Host1x/HDMI properties.
Signed-off-by: Marcel Ziswiler
---
arch/arm/boot/dts/tegra20-colibri.dtsi | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi
b/arch/arm/boot/dts/tegra20-colibri.dtsi
index ad816fa827f7..c060b58cb490 100644
--- a/arch/arm/boot/dts/tegra20-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri.dtsi
@@ -16,12 +16,11 @@
host1x@5000 {
hdmi@5428 {
- vdd-supply = <_vdd_reg>;
- pll-supply = <_pll_reg>;
-
nvidia,ddc-i2c-bus = <_ddc>;
- nvidia,hpd-gpio = < TEGRA_GPIO(N, 7)
- GPIO_ACTIVE_HIGH>;
+ nvidia,hpd-gpio =
+ < TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+ pll-supply = <_pll_reg>;
+ vdd-supply = <_vdd_reg>;
};
};
--
2.14.4
[PATCH v5 1/5] pinctrl: actions: define constructor generic to Actions Semi SoC's
Move generic defines common to the Owl family out of S900 driver.
Signed-off-by: Parthiban Nallathambi
Signed-off-by: Saravanan Sekar
---
drivers/pinctrl/actions/pinctrl-owl.h | 131 +++
drivers/pinctrl/actions/pinctrl-s900.c | 139 ++---
2 files changed, 137 insertions(+), 133 deletions(-)
diff --git a/drivers/pinctrl/actions/pinctrl-owl.h
b/drivers/pinctrl/actions/pinctrl-owl.h
index a724d1d406d4..31cc33d7c4a5 100644
--- a/drivers/pinctrl/actions/pinctrl-owl.h
+++ b/drivers/pinctrl/actions/pinctrl-owl.h
@@ -15,6 +15,136 @@
#define OWL_PINCONF_SLEW_SLOW 0
#define OWL_PINCONF_SLEW_FAST 1
+#define MUX_PG(group_name, reg, shift, width) \
+ { \
+ .name = #group_name,\
+ .pads = group_name##_pads, \
+ .npads = ARRAY_SIZE(group_name##_pads), \
+ .funcs = group_name##_funcs,\
+ .nfuncs = ARRAY_SIZE(group_name##_funcs), \
+ .mfpctl_reg = MFCTL##reg, \
+ .mfpctl_shift = shift, \
+ .mfpctl_width = width, \
+ .drv_reg = -1, \
+ .drv_shift = -1,\
+ .drv_width = -1,\
+ .sr_reg = -1, \
+ .sr_shift = -1, \
+ .sr_width = -1, \
+ }
+
+#define DRV_PG(group_name, reg, shift, width) \
+ { \
+ .name = #group_name,\
+ .pads = group_name##_pads, \
+ .npads = ARRAY_SIZE(group_name##_pads), \
+ .mfpctl_reg = -1, \
+ .mfpctl_shift = -1, \
+ .mfpctl_width = -1, \
+ .drv_reg = PAD_DRV##reg,\
+ .drv_shift = shift, \
+ .drv_width = width, \
+ .sr_reg = -1, \
+ .sr_shift = -1, \
+ .sr_width = -1, \
+ }
+
+#define SR_PG(group_name, reg, shift, width) \
+ { \
+ .name = #group_name,\
+ .pads = group_name##_pads, \
+ .npads = ARRAY_SIZE(group_name##_pads), \
+ .mfpctl_reg = -1, \
+ .mfpctl_shift = -1, \
+ .mfpctl_width = -1, \
+ .drv_reg = -1, \
+ .drv_shift = -1,\
+ .drv_width = -1,\
+ .sr_reg = PAD_SR##reg, \
+ .sr_shift = shift, \
+ .sr_width = width, \
+ }
+
+#define FUNCTION(fname)\
+ { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+/* PAD PULL UP/DOWN CONFIGURES */
+#define PULLCTL_CONF(pull_reg, pull_sft, pull_wdt) \
+ { \
+ .reg = PAD_PULLCTL##pull_reg, \
+ .shift = pull_sft, \
+ .width = pull_wdt, \
+ }
+
+#define PAD_PULLCTL_CONF(pad_name, pull_reg, pull_sft, pull_wdt) \
+ struct owl_pullctl pad_name##_pullctl_conf \
+ = PULLCTL_CONF(pull_reg, pull_sft, pull_wdt)
+
+#define ST_CONF(st_reg, st_sft, st_wdt)\
+ { \
+ .reg = PAD_ST##st_reg, \
+
[PATCH v5 5/5] arm64: dts: actions: Add pinctrl node for Actions Semi S700
Add pinctrl nodes for Actions Semi S700 SoC
Signed-off-by: Parthiban Nallathambi
Signed-off-by: Saravanan Sekar
---
arch/arm64/boot/dts/actions/s700.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/actions/s700.dtsi
b/arch/arm64/boot/dts/actions/s700.dtsi
index 66dd5309f0a2..8fbd7b1570a7 100644
--- a/arch/arm64/boot/dts/actions/s700.dtsi
+++ b/arch/arm64/boot/dts/actions/s700.dtsi
@@ -165,5 +165,21 @@
interrupts = ;
interrupt-names = "timer1";
};
+
+ pinctrl: pinctrl@e01b {
+ compatible = "actions,s700-pinctrl";
+ reg = <0x0 0xe01b 0x0 0x1000>;
+ clocks = < CLK_GPIO>;
+ gpio-controller;
+ gpio-ranges = < 0 0 136>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = ,
+,
+,
+,
+;
+ };
};
};
--
2.14.4
Re: [PATCH] pinctrl: Convert to using %pOFn instead of device_node.name
Am Dienstag, 28. August 2018, 03:52:41 CEST schrieb Rob Herring: > In preparation to remove the node name pointer from struct device_node, > convert printf users to use the %pOFn format specifier. > drivers/pinctrl/pinctrl-rockchip.c| 8 ++--- For the Rockchip-part Acked-by: Heiko Stuebner
Re: [PATCH v6 2/2] pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver
On Wed, Aug 8, 2018 at 11:26 AM Tomer Maimon wrote: > Add Nuvoton BMC NPCM750/730/715/705 Pinmux and > GPIO controller driver. > > Signed-off-by: Tomer Maimon Patch applied! It's a very nice driver. I had to add back select GPIO_GENERIC as the driver uses bgpio_init() exactly as I wanted. Yours, Linus Walleij
Re: [PATCH v2] x86/entry/64: wipe KASAN stack shadow before rewind_stack_do_exit()
On 08/28/2018 09:40 PM, Jann Horn wrote:
> Reset the KASAN shadow state of the task stack before rewinding RSP.
> Without this, a kernel oops will leave parts of the stack poisoned, and
> code running under do_exit() can trip over such poisoned regions and cause
> nonsensical false-positive KASAN reports about stack-out-of-bounds bugs.
>
> This patch does not wipe exception stacks; if you oops on an exception
> stack, you might get random KASAN false-positives from other tasks
> afterwards. This is probably relatively uninteresting, since if you're
> oopsing on an exception stack, you likely have bigger things to worry
> about. It'd be more interesting if vmapped stacks and KASAN were
> compatible, since then handle_stack_overflow() would oops from exception
> stack context.
>
> Fixes: 2deb4be28077 ("x86/dumpstack: When OOPSing, rewind the stack before
> do_exit()")
> Signed-off-by: Jann Horn
> ---
Acked-by: Andrey Ryabinin
Re: Flushing user entries for kernel mappings in x86
at 8:45 PM, Andy Lutomirski wrote: > On Tue, Aug 28, 2018 at 6:46 PM, Nadav Amit wrote: >> Hello Andy, >> >> Is there a reason for __flush_tlb_one_kernel() to flush the PTE not only in >> the kernel address space, but also in the user one (as part of >> __flush_tlb_one_user)? [ I obviously regard the case when PTI is on ]. > > In most cases, probably not, but it's fairly cheap, I think. And it > makes it so that we're okay if the TLB entry we're flushing is used by > the entry code. Thanks. I assumed that’s the case. I don’t know how cheap they are (especially if INVPCID is not supported) but I guess they are not that frequent.
