>From 22b71f970f18f5f38161be028ab7ce7cd1f769f7 Mon Sep 17 00:00:00 2001
From: Ingo Molnar
Date: Mon, 3 Dec 2018 09:15:40 +0100
Subject: [PATCH] x86/pci: Remove the dead-code DBG() macro
While reading arch/x86/include/asm/pci_x86.h I noticed that we have ancient
residuals of debugging code, which
- Add opcodes for octal I/O commands
* Read : 1-1-8 and 1-8-8 protocol
* Write : 1-1-8 and 1-8-8 protocol
* opcodes for 4-byte address mode command
- Entry of macros in _convert_3to4_xxx function
- Add flag specifying flash support octal read commands.
Signed-off-by: Vignesh R
On Mon 03-12-18 08:47:00, Ingo Molnar wrote:
[...]
> I reviewed the ->cred_guard_mutex code, and the mutex is held across all
> of exec() - and we always did this.
Yes, this is something that has been pointed out during the review. Oleg
has argued that making this path freezable is really hard
Add support for octal mode I/O data transfer based on the controller (spi)
mode.
Assign hw-capability mask bits for octal transfer.
Signed-off-by: Yogesh Gaur
---
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Add octal read flag for flash mt35xu512aba.
This flash, mt35xu512aba, is only complaint to SFDP JESD216B and does
not seem to support newer JESD216C standard that provides auto
detection of Octal mode capabilities and opcodes. Therefore, this
capability is manually added using new
Add support for octal mode IO data transfer.
Micron flash, mt35xu512aba, supports octal mode data transfer and
NXP FlexSPI controller supports 8 data lines for data transfer (Rx/Tx).
Patch series
* Add support for octal mode flags and parsing of same in spi driver.
* Add parsing logic for spi-mem
Add octal mode flags for octal I/O data transfer support.
NXP FlexSPI controller supports 8 lines Rx/Tx data transfer.
Signed-off-by: Yogesh Gaur
---
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for
Add support for octal mode I/O data transfer in spi-mem framework.
Signed-off-by: Yogesh Gaur
Reviewed-by: Boris Brezillon
---
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- Patch added in v2
Add flags for Octal mode I/O data transfer
Required for the SPI controller which can do the data transfer (TX/RX)
on 8 data lines e.g. NXP FlexSPI controller.
SPI_TX_OCTAL: transmit with 8 wires
SPI_RX_OCTAL: receive with 8 wires
Signed-off-by: Yogesh Gaur
Reviewed-by: Boris Brezillon
---
Flash mt35xu512aba connected to FlexSPI controller supports
1-1-8/1-8-8 protocol.
Added flag spi-rx-bus-width and spi-tx-bus-width with values as
8 and 8 respectively for both flashes connected at CS0 and CS1.
Signed-off-by: Yogesh Gaur
---
Changes for v5:
- None
Changes for v4:
- None
Changes
* Ingo Molnar wrote:
> From 22b71f970f18f5f38161be028ab7ce7cd1f769f7 Mon Sep 17 00:00:00 2001
> From: Ingo Molnar
> Date: Mon, 3 Dec 2018 09:15:40 +0100
> Subject: [PATCH] x86/pci: Remove the dead-code DBG() macro
>
> While reading arch/x86/include/asm/pci_x86.h I noticed that we have
Hi Chunyan,
On 29/11/18 2:53 PM, Adrian Hunter wrote:
> On 29/11/18 8:07 AM, Chunyan Zhang wrote:
>> Some standard SD host controllers can support both external dma
>> controllers as well as ADMA/SDMA in which the SD host controller
>> acts as DMA master. TI's omap controller is the case as an
On Fri, Nov 30, 2018 at 8:28 PM Jarkko Sakkinen
wrote:
>
> In order to comply with the CoC, replace with a hug.
>
> Signed-off-by: Jarkko Sakkinen
> ---
> drivers/cpufreq/powernow-k7.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/cpufreq/powernow-k7.c
On Sat, Dec 1, 2018 at 2:51 AM Yangtao Li wrote:
>
> We already have the DEFINE_SHOW_ATTRIBUTE,There is no need to define such
> a macro,so remove define_genpd_open_function and define_genpd_debugfs_fops.
> Also use DEFINE_SHOW_ATTRIBUTE to simplify somecode.
>
> Signed-off-by: Yangtao Li
It
On Mon, 2018-12-03 at 14:13 +0800, Xingyu Chen wrote:
> The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the
> other Meson SoCs, A totle of 100 pins can be spied on, which is the sum of:
>
> - 223:100 undefined (no interrupt)
> - 99:97 3 pins on bank GPIOE
> - 96:77 20
Add a driver for Renesas R-Car Gen3 RPC SPI controller.
Signed-off-by: Mason Yang
---
drivers/spi/Kconfig | 6 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-renesas-rpc.c | 808 ++
3 files changed, 815 insertions(+)
create mode
* Wen Yang wrote:
> Fix the following warnings reported by coccinelle:
>
> kernel/locking/locktorture.c:703:6-10: WARNING: Assignment of bool to 0/1
> kernel/locking/locktorture.c:918:2-20: WARNING: Assignment of bool to 0/1
> kernel/locking/locktorture.c:949:3-20: WARNING: Assignment of bool
When performing single ended measurements with TSCADC, its recommended
to set negative input (SEL_INM_SWC_3_0) of ADC step to ADC's VREFN in the
corresponding STEP_CONFIGx register.
Also, the positive(SEL_RFP_SWC_2_0) and negative(SEL_RFM_SWC_1_0)
reference voltage for ADC step needs to be set to
Couple of fixes for tscadc drivers that I found while adding support for
new SoC.
Vignesh R (2):
mfd: ti_am335x_tscadc: Use PLATFORM_DEVID_AUTO while registering mfd
cells
iio: adc: ti_am335x_tscadc: Improve accuracy of measurement
drivers/iio/adc/ti_am335x_adc.c | 5 -
When usage exceeds min, min usage should be min other than 0.
Apply the same for low.
Signed-off-by: Xunlei Pang
---
mm/page_counter.c | 12 ++--
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/mm/page_counter.c b/mm/page_counter.c
index de31470655f6..75d53f15f040 100644
Hi Michal,
On 30/11/18 12:48 PM, Michal Simek wrote:
> On 29. 11. 18 17:15, Faiz Abbas wrote:
>> The "ti,am654-sdhci-5.1" binding has been moved to a new driver. Indicate
>> this by a deprecated message.
>>
>> Signed-off-by: Faiz Abbas
>> ---
>>
From: Frieder Schrempf
When reading the status of the on-chip ECC, the Toshiba chip returns
two different states for reporting corrected bitflips. We should check
for both of them.
Also return the free OOB bytes as one contiguous area, instead of
multiple sections.
Suggested-by: Clément Péron
There may be cgroup memory overcommitment, it will become
even common in the future.
Let's enable kswapd to reclaim low-protected memory in case
of memory pressure, to mitigate the global direct reclaim
pressures which could cause jitters to the response time of
lantency-sensitive groups.
* Wen Yang wrote:
> This patch fixes the following checkpatch.pl errors:
>
> ERROR: spaces required around that ':' (ctx:VxW)
> +torture_type, tag, cxt.debug_lock ? " [debug]": "",
There's literally 1 million checkpatch 'failures' in the kernel, so
unless we want to apply 1
When memcgs get reclaimed after its usage exceeds min, some
usages below the min may also be reclaimed in the current
implementation, the amount is considerably large during kswapd
reclaim according to my ftrace results.
This patch calculates the part over hard protection limit,
and allows only
Use PLATFORM_DEVID_AUTO to number mfd cells while registering, so that
different instances are uniquely identified. This is required in order
to support registering of multiple instances of same ti_am335x_tscadc IP.
Signed-off-by: Vignesh R
---
v2: use PLATFORM_DEVID_AUTO as suggested by Lee
Hi Yogesh,
On Thu, 22 Nov 2018 05:14:31 +
Yogesh Narayan Gaur wrote:
> Add flags for Octo mode I/O data transfer
> Required for the SPI controller which can do the data transfer (TX/RX)
> on 8 data lines e.g. NXP FlexSPI controller.
> SPI_TX_OCTO: transmit with 8 wires
> SPI_RX_OCTO:
Hi,
Thank you for your comments.
On 2018/11/30 17:19, Stephen Boyd wrote:
Quoting Sugaya Taichi (2018-11-18 17:01:11)
Add DT bindings document for Milbeaut clock.
Signed-off-by: Sugaya Taichi
---
.../devicetree/bindings/clock/milbeaut-clock.txt | 93 ++
1 file
Finding endpoints of an IPC channel is one of essential task to
understand how a user program works. Procfs and netlink socket provide
enough hints to find endpoints for IPC channels like pipes, unix
sockets, and pseudo terminals. However, there is no simple way to find
endpoints for an eventfd
On Wed, 28 Nov 2018 at 09:03, Huijin Park wrote:
> From: "huijin.park"
>
> The "params->size" is defined as "u64".
> And "info->sector_size" and "info->n_sectors" are defined as
> unsigned int and u16.
> Thus, u64 data might have strange data(loss data) if the result
> overflows an unsigned int.
>From 22b71f970f18f5f38161be028ab7ce7cd1f769f7 Mon Sep 17 00:00:00 2001
From: Ingo Molnar
Date: Mon, 3 Dec 2018 09:15:40 +0100
Subject: [PATCH] x86/pci: Remove the dead-code DBG() macro
While reading arch/x86/include/asm/pci_x86.h I noticed that we have ancient
residuals of debugging code, which
On Sat, Dec 01, 2018 at 05:09:36PM +0800, Wen Yang wrote:
> Fix the following warnings reported by coccinelle:
> kernel//sched/fair.c:7958:3-12: WARNING: Assignment of bool to 0/1
>
> This also makes the code more readable.
I disagree; anybody that has trouble with 0/1 vs false/true needs to
On Sat, Dec 01, 2018 at 12:37:01PM -0800, Paul E. McKenney wrote:
> On Sat, Dec 01, 2018 at 04:31:49PM +0800, Wen Yang wrote:
> > Fix the following warnings reported by coccinelle:
> >
> > kernel/locking/locktorture.c:703:6-10: WARNING: Assignment of bool to 0/1
> >
Hello!
On 03.12.2018 6:45, Yu Chen wrote:
This patch adds binding descriptions to support the dwc3 controller
on HiSilicon SoCs and boards like the HiKey960.
Cc: Greg Kroah-Hartman
Cc: Rob Herring
Cc: Mark Rutland
Cc: John Stultz
Signed-off-by: Yu Chen
---
Hi,
another friendly reminder for this patchset...
Any comments/objections?
regards;Richard.L
On 17.10.18 14:51, Richard Leitner wrote:
> Add reset-gpio, sx8654[056] and common of_touchscreen functions support
> for the sx8654 driver.
>
> Changes v2:
> - use devm_gpiod_get_optional in
This driver supports all versions of stingray SS and HS
USB phys.
In version 1 is combo phy contain both SS and HS phys
in a common IO space.
In version 2 a single HS phy.
These phys support both xHCI host driver and
BDC Broadcom device controller driver.
Signed-off-by: Srinath Mannam
Add DT binding document for stingray usb phy.
Signed-off-by: Srinath Mannam
Reviewed-by: Florian Fainelli
Reviewed-by: Scott Branden
---
.../bindings/phy/brcm,stingray-usb-phy.txt | 62 ++
1 file changed, 62 insertions(+)
create mode 100644
Add DT nodes for
- Two xHCI host controllers
- Two BDC Broadcom USB device controller
- Five USB PHY controllers
[xHCI0] [BDC0][xHCI1][BDC1]
| | | |
--- ---
|
These patches add stingray usb phy driver and its
corresponding DT nodes with documentation.
All patches are based on Linux-4.19.
Changes from v1:
- Addressed Kishon review comments
- phy init call return value handle
Srinath Mannam (3):
dt-bindings: phy: Add binding document for
Add support for octal mode IO data transfer.
Micron flash, mt35xu512aba, supports octal mode data transfer and
NXP FlexSPI controller supports 8 data lines for data transfer (Rx/Tx).
Patch series
* Add support for octal mode flags and parsing of same in spi driver.
* Add parsing logic for spi-mem
Add support for octal mode I/O data transfer in spi-mem framework.
Signed-off-by: Yogesh Gaur
Reviewed-by: Boris Brezillon
---
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- Patch added in v2
Add flags for Octal mode I/O data transfer
Required for the SPI controller which can do the data transfer (TX/RX)
on 8 data lines e.g. NXP FlexSPI controller.
SPI_TX_OCTAL: transmit with 8 wires
SPI_RX_OCTAL: receive with 8 wires
Signed-off-by: Yogesh Gaur
Reviewed-by: Boris Brezillon
---
Add octal mode flags for octal I/O data transfer support.
NXP FlexSPI controller supports 8 lines Rx/Tx data transfer.
Signed-off-by: Yogesh Gaur
---
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for
Flash mt35xu512aba connected to FlexSPI controller supports
1-1-8/1-8-8 protocol.
Added flag spi-rx-bus-width and spi-tx-bus-width with values as
8 and 8 respectively for both flashes connected at CS0 and CS1.
Signed-off-by: Yogesh Gaur
---
Changes for v5:
- None
Changes for v4:
- None
Changes
- Add opcodes for octal I/O commands
* Read : 1-1-8 and 1-8-8 protocol
* Write : 1-1-8 and 1-8-8 protocol
* opcodes for 4-byte address mode command
- Entry of macros in _convert_3to4_xxx function
- Add flag specifying flash support octal read commands.
Signed-off-by: Vignesh R
On Mon 03-12-18 08:47:00, Ingo Molnar wrote:
[...]
> I reviewed the ->cred_guard_mutex code, and the mutex is held across all
> of exec() - and we always did this.
Yes, this is something that has been pointed out during the review. Oleg
has argued that making this path freezable is really hard
Add support for octal mode I/O data transfer based on the controller (spi)
mode.
Assign hw-capability mask bits for octal transfer.
Signed-off-by: Yogesh Gaur
---
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Add octal read flag for flash mt35xu512aba.
This flash, mt35xu512aba, is only complaint to SFDP JESD216B and does
not seem to support newer JESD216C standard that provides auto
detection of Octal mode capabilities and opcodes. Therefore, this
capability is manually added using new
Hi Benjamin,
On 11/12/18 4:23 PM, Benjamin Gaignard wrote:
This serie adds the support of the hardware semaphore block for stm32mp1 SoC.
version 3:
- fix clock name in properties description.
- use postcore_initcall() instead of module_platform_driver()
version 2:
- fix comments done by Bjorn
On Mon, Dec 03, 2018 at 09:35:00AM +0100, Peter Zijlstra wrote:
> On Sat, Dec 01, 2018 at 12:37:01PM -0800, Paul E. McKenney wrote:
> > On Sat, Dec 01, 2018 at 04:31:49PM +0800, Wen Yang wrote:
> > > Fix the following warnings reported by coccinelle:
> > >
> > >
Hi Boris,
> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Monday, December 3, 2018 1:35 PM
> To: Yogesh Narayan Gaur ;
> broo...@kernel.org
> Cc: linux-...@lists.infradead.org; marek.va...@gmail.com; vigne...@ti.com;
> linux-...@vger.kernel.org;
* Ingo Molnar wrote:
> From 22b71f970f18f5f38161be028ab7ce7cd1f769f7 Mon Sep 17 00:00:00 2001
> From: Ingo Molnar
> Date: Mon, 3 Dec 2018 09:15:40 +0100
> Subject: [PATCH] x86/pci: Remove the dead-code DBG() macro
>
> While reading arch/x86/include/asm/pci_x86.h I noticed that we have
On 30-11-18, 10:44, Ulf Hansson wrote:
> On Mon, 26 Nov 2018 at 09:10, Viresh Kumar wrote:
> > +static int _genpd_reeval_performance_state(struct generic_pm_domain *genpd,
> > + unsigned int state, int depth);
> > +
>
> I don't like forward declarations
* Peter Zijlstra wrote:
> On Sat, Dec 01, 2018 at 12:37:01PM -0800, Paul E. McKenney wrote:
> > On Sat, Dec 01, 2018 at 04:31:49PM +0800, Wen Yang wrote:
> > > Fix the following warnings reported by coccinelle:
> > >
> > > kernel/locking/locktorture.c:703:6-10: WARNING: Assignment of bool to
Hi Bich,
On 11/15/18 9:52 AM, Bich HEMON wrote:
This patchset changes the CAN RAM mapping and adds CAN sleep pins.
Bich Hemon (3):
ARM: dts: stm32: change CAN RAM mapping on stm32mp157c
ARM: dts: stm32: add can1 sleep pins muxing
ARM: dts: stm32: add can1 sleep pins muxing on
Hi Chunyan,
On 29/11/18 2:53 PM, Adrian Hunter wrote:
> On 29/11/18 8:07 AM, Chunyan Zhang wrote:
>> Some standard SD host controllers can support both external dma
>> controllers as well as ADMA/SDMA in which the SD host controller
>> acts as DMA master. TI's omap controller is the case as an
On Fri, Nov 30, 2018 at 8:28 PM Jarkko Sakkinen
wrote:
>
> In order to comply with the CoC, replace with a hug.
>
> Signed-off-by: Jarkko Sakkinen
> ---
> drivers/cpufreq/powernow-k7.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/cpufreq/powernow-k7.c
On Mon 03-12-18 04:00:08, Yueyi Li wrote:
> Found warning:
>
> WARNING: EXPORT symbol "gsi_write_channel_scratch" [vmlinux] version
> generation failed, symbol will not be versioned.
> WARNING: vmlinux.o(.text+0x1e0a0): Section mismatch in reference from the
> function valid_phys_addr_range()
Hi, Pan Bian
Thank you for feeding back this patch.
I reviewed this and am thinking this must be sent to upstream.
Did you see any kernel oops on this bug ?
Regards,
Ryusuke Konishi
On Mon, 26 Nov 2018 11:08:29 +0800, Pan Bian wrote:
> brelse(bh) is called to drop the reference count of bh
On Sat, Dec 1, 2018 at 2:51 AM Yangtao Li wrote:
>
> We already have the DEFINE_SHOW_ATTRIBUTE,There is no need to define such
> a macro,so remove define_genpd_open_function and define_genpd_debugfs_fops.
> Also use DEFINE_SHOW_ATTRIBUTE to simplify somecode.
>
> Signed-off-by: Yangtao Li
It
On Fri, Nov 30, 2018 at 3:26 PM Yangtao Li wrote:
>
> In a function whose return type is void, returning on the last line is
> not required.So remove it.Also move the module declaration to the end.
The last piece is not reflected by the subject.
Also, why do you move the MODULE_ stuff around at
On Mon, Dec 03, 2018 at 06:10:51PM +0900, Ryusuke Konishi wrote:
> Hi, Pan Bian
>
> Thank you for feeding back this patch.
> I reviewed this and am thinking this must be sent to upstream.
>
> Did you see any kernel oops on this bug ?
Not yet. In fact, I found it with a static method.
Best
On 12/02/2018 09:43 PM, Arnd Bergmann wrote:
> On Sun, Dec 2, 2018 at 2:47 PM Gabriel Francisco Mandaji
> wrote:
>
>> @@ -667,10 +653,28 @@ static void vivid_overlay(struct vivid_dev *dev,
>> struct vivid_buffer *buf)
>> }
>> }
>>
>> +static void vivid_cap_update_frame_period(struct
* Wen Yang wrote:
> This is the patch to the file cpu.c
> which fixes the following coccinelle warning:
>
> WARNING: Comparison to bool
>
> Signed-off-by: Wen Yang
> CC: Thomas Gleixner
> CC: Ingo Molnar
> CC: Konrad Rzeszutek Wilk
> CC: Josh Poimboeuf
> CC: "Peter Zijlstra (Intel)"
>
This patch set adds Flash Interface Unit(FIU) SPI-NOR
support for the Nuvoton NPCM Baseboard Management
Controller (BMC).
The FIU supports single, dual or quad communication interface.
the FIU controller can operate in following modes:
- User Mode Access(UMA): provides flash access by
Add Nuvoton NPCM BMC Flash Interface Unit(FIU) SPI-NOR
controller driver
The FIU supports single, dual or quad communication interface.
the FIU controller can operate in following modes:
- User Mode Access(UMA): provides flash access by using an
indirect address/data mechanism.
- direct rd/wr
Added device tree binding documentation for Nuvoton BMC
NPCM Flash Interface Unit(FIU) SPI-NOR controller.
Signed-off-by: Tomer Maimon
---
Documentation/devicetree/bindings/mtd/npcm-fiu.txt | 64 ++
1 file changed, 64 insertions(+)
create mode 100644
Hi Mark,
On Mon, 3 Dec 2018 08:39:00 +
Yogesh Narayan Gaur wrote:
>
> Yogesh Gaur (7):
> spi: add support for octal mode I/O data transfer
> spi: spi-mem: add support for octal mode I/O data transfer
Can you take those 2 patches in your tree for 4.21/5.0?
> mtd: spi-nor: add
On Mon, 2018-12-03 at 14:13 +0800, Xingyu Chen wrote:
> The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the
> other Meson SoCs, A totle of 100 pins can be spied on, which is the sum of:
>
> - 223:100 undefined (no interrupt)
> - 99:97 3 pins on bank GPIOE
> - 96:77 20
Add a driver for Renesas R-Car Gen3 RPC SPI controller.
Signed-off-by: Mason Yang
---
drivers/spi/Kconfig | 6 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-renesas-rpc.c | 808 ++
3 files changed, 815 insertions(+)
create mode
On Fri, Nov 30, 2018 at 04:35:06PM -0800, Dan Williams wrote:
> Dan Williams (5):
> generic/pgtable: Make {pmd,pud}_same() unconditionally available
> generic/pgtable: Introduce {p4d,pgd}_same()
> generic/pgtable: Introduce set_pte_safe()
> x86/mm: Validate
On Mon, 3 Dec 2018, Peter Zijlstra wrote:
> On Mon, Dec 03, 2018 at 09:35:00AM +0100, Peter Zijlstra wrote:
> > On Sat, Dec 01, 2018 at 12:37:01PM -0800, Paul E. McKenney wrote:
> > > On Sat, Dec 01, 2018 at 04:31:49PM +0800, Wen Yang wrote:
> > > > Fix the following warnings reported by
On Mon, Dec 03, 2018 at 10:23:03AM +1100, Dave Chinner wrote:
On Sat, Dec 01, 2018 at 02:49:09AM -0500, Sasha Levin wrote:
In 'git log'! You report these every time you fix something in upstream
xfs but don't backport it to stable trees:
That is so wrong on so many levels I don't really know
Le 22/10/2018 à 22:13, Dave Hansen a écrit :
> Persistent memory is cool. But, currently, you have to rewrite
> your applications to use it. Wouldn't it be cool if you could
> just have it show up in your system like normal RAM and get to
> it like a slow blob of memory? Well... have I got the
On Mon, 3 Dec 2018 11:14:54 +0200
Tomer Maimon wrote:
> This patch set adds Flash Interface Unit(FIU) SPI-NOR
> support for the Nuvoton NPCM Baseboard Management
> Controller (BMC).
>
> The FIU supports single, dual or quad communication interface.
>
> the FIU controller can operate
On Fri 2018-11-30 20:51:54, Yangtao Li wrote:
> We already have the DEFINE_SHOW_ATTRIBUTE,There is no need to define such
> a macro,so remove define_genpd_open_function and define_genpd_debugfs_fops.
> Also use DEFINE_SHOW_ATTRIBUTE to simplify somecode.
"and there", ", so".
> Signed-off-by:
On Mon, Dec 03, 2018 at 11:01:00AM +0800, Baoquan He wrote:
> It looks do-able, not sure if the test case is complicated or not, if
> not hard, I can have a try. And I have some internal bugs, can focus on
> this later. I saw you posted another patchset to fix xen issue, it may
> not be needed any
Use kvm_vcpu_map when mapping the L1 MSR bitmap since using
kvm_vcpu_gpa_to_page() and kmap() will only work for guest memory that has
a "struct page".
Signed-off-by: KarimAllah Ahmed
---
v1 -> v2:
- Do not change the lifecycle of the mapping (pbonzini)
---
arch/x86/kvm/vmx.c | 14
Copy the VMCS12 directly from guest memory instead of the map->copy->unmap
sequence. This also avoids using kvm_vcpu_gpa_to_page() and kmap() which
assumes that there is a "struct page" for guest memory.
Signed-off-by: KarimAllah Ahmed
---
v3 -> v4:
- Return
Update the PML table without mapping and unmapping the page. This also
avoids using kvm_vcpu_gpa_to_page(..) which assumes that there is a "struct
page" for guest memory.
Signed-off-by: KarimAllah Ahmed
---
v1 -> v2:
- Use kvm_write_guest_page instead of kvm_write_guest (pbonzini)
- Do not use
Use the new mapping API for mapping guest memory to avoid depending on
"struct page".
Signed-off-by: KarimAllah Ahmed
---
arch/x86/kvm/svm.c | 97 +++---
1 file changed, 49 insertions(+), 48 deletions(-)
diff --git a/arch/x86/kvm/svm.c
Read the data directly from guest memory instead of the map->read->unmap
sequence. This also avoids using kvm_vcpu_gpa_to_page() and kmap() which
assumes that there is a "struct page" for guest memory.
Suggested-by: Jim Mattson
Signed-off-by: KarimAllah Ahmed
Reviewed-by: Jim Mattson
---
v1
Use kvm_vcpu_map in synic_deliver_msg since using kvm_vcpu_gpa_to_page()
and kmap() will only work for guest memory that has a "struct page".
Signed-off-by: KarimAllah Ahmed
---
v1 -> v2:
- Update to match the new API return codes
---
arch/x86/kvm/hyperv.c | 12 ++--
1 file changed, 6
Use kvm_vcpu_map for accessing the enhanced VMCS since using
kvm_vcpu_gpa_to_page() and kmap() will only work for guest memory that has
a "struct page".
Signed-off-by: KarimAllah Ahmed
---
arch/x86/kvm/vmx.c | 16 ++--
1 file changed, 6 insertions(+), 10 deletions(-)
diff --git
Use kvm_vcpu_map when mapping the posted interrupt descriptor table since
using kvm_vcpu_gpa_to_page() and kmap() will only work for guest memory
that has a "struct page".
One additional semantic change is that the virtual host mapping lifecycle
has changed a bit. It now has the same lifetime of
From: Filippo Sironi
cmpxchg_gpte() calls get_user_pages_fast() to retrieve the number of
pages and the respective struct page to map in the kernel virtual
address space.
This doesn't work if get_user_pages_fast() is invoked with a userspace
virtual address that's backed by PFNs outside of
Use kvm_vcpu_map in emulator_cmpxchg_emulated since using
kvm_vcpu_gpa_to_page() and kmap() will only work for guest memory that has
a "struct page".
Signed-off-by: KarimAllah Ahmed
---
v1 -> v2:
- Update to match the new API return codes
---
arch/x86/kvm/x86.c | 13 ++---
1 file
Use kvm_vcpu_map for accessing the shadow VMCS since using
kvm_vcpu_gpa_to_page() and kmap() will only work for guest memory that has
a "struct page".
Signed-off-by: KarimAllah Ahmed
---
arch/x86/kvm/vmx.c | 25 -
1 file changed, 12 insertions(+), 13 deletions(-)
diff
Use kvm_vcpu_map when mapping the virtual APIC page since using
kvm_vcpu_gpa_to_page() and kmap() will only work for guest memory that has
a "struct page".
One additional semantic change is that the virtual host mapping lifecycle
has changed a bit. It now has the same lifetime of the pinning of
Use kvm_vcpu_map in synic_clear_sint_msg_pending since using
kvm_vcpu_gpa_to_page() and kmap() will only work for guest memory that has
a "struct page".
Signed-off-by: KarimAllah Ahmed
---
v1 -> v2:
- Update to match the new API return codes
---
arch/x86/kvm/hyperv.c | 16 ++--
1
On Sun, Dec 02, 2018 at 07:28:55PM -0800, Randy Dunlap wrote:
> Hi,
> I have more editing comments below.
>
>
> On 11/15/18 5:01 PM, Jarkko Sakkinen wrote:
> > Documentation of the features of the Software Guard eXtensions used
> > by the Linux kernel and basic design choices for the core and
In KVM, specially for nested guests, there is a dominant pattern of:
=> map guest memory -> do_something -> unmap guest memory
In addition to all this unnecessarily noise in the code due to boiler plate
code, most of the time the mapping function does not properly handle memory
that is
Guest memory can either be directly managed by the kernel (i.e. have a "struct
page") or they can simply live outside kernel control (i.e. do not have a
"struct page"). KVM mostly support these two modes, except in a few places
where the code seems to assume that guest memory must have a "struct
Hi Shawn,
Thank you for the review.
> On Tue, Nov 13, 2018 at 01:12:13PM +0100, Lukasz Majewski wrote:
> > The procedure to read this ID value is as follows:
> >
> > rmmod spi_fsl_dspi
> > insmod spi-gpio.ko
> >
> > echo 504 > /sys/class/gpio/export
> > cat /sys/class/gpio/gpio504/value
> >
On Sun, 2018-12-02 at 22:42 +0100, Martin Blumenstingl wrote:
> Martin Blumenstingl (3):
> - clk: meson: meson8b: fix the offset of -- vid_pll_dco's N value
> - clk: meson: meson8b: add the fractional divider for -- vid_pll_dco
> - clk: meson: meson8b: add the read-only video clock trees
>
On Fri, Nov 30, 2018 at 1:29 PM Chen-Yu Tsai wrote:
>
> The CSI controller found on the H3 (and H5) is a reduced version of the
> one found on the A31. It only has 1 channel, instead of 4 channels for
> time-multiplexed BT.656. Since the H3 is a reduced version, it cannot
> "fallback" to a
On 2018/12/3 17:19, Jerome Brunet wrote:
On Mon, 2018-12-03 at 14:13 +0800, Xingyu Chen wrote:
The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the
other Meson SoCs, A totle of 100 pins can be spied on, which is the sum of:
- 223:100 undefined (no interrupt)
- 99:97
On Fri, Nov 30, 2018 at 1:29 PM Chen-Yu Tsai wrote:
>
> The CSI controller found on the H3 (and H5) is a reduced version of the
> one found on the A31. It only has 1 channel, instead of 4 channels for
> time-multiplexed BT.656. Since the H3 is a reduced version, it cannot
> "fallback" to a
Hi David,
On 10/5/18 12:08 PM, David HERNANDEZ SANCHEZ wrote:
Add configuration on DT for thermal sensor driver
Signed-off-by: David Hernandez Sanchez
diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi
b/arch/arm/boot/dts/stm32mp157c.dtsi
index 661be94..e90b9f6 100644
---
Scenario 1, ARMv7:
==
If code in arch/arm/kernel/ftrace.c would operate on mcount() pointer
the following may be generated:
0230 :
230: b5f8push{r3, r4, r5, r6, r7, lr}
232: b500push{lr}
234: f7ff fffe bl 0 <__gnu_mcount_nc>
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