On Tue, 11 Dec 2018 17:54:57 -0700
Jeremy Fertic wrote:
> The calculation of the current dac value is using the wrong bits of the
> dac lsb register. Create two macros to shift the lsb register value into
> lsb position, depending on whether the dac is 10 or 12 bit. Initialize
> data to 0 so,
On Tue, 11 Dec 2018 17:54:55 -0700
Jeremy Fertic wrote:
> The only assignment to dac_bits is in adt7316_store_da_high_resolution().
> This function enables or disables 10 bit dac resolution for the adt7316/7
> and adt7516/7 when they're set to output voltage proportional to
> temperature. Remove
Hi Stephen,
On Sun, Dec 16, 2018 at 6:23 AM Stephen Rothwell wrote:
>
> Added from Monday.
Thanks!
> Out of interest, will this tree be sent directly to
> Linus or merged vi some other tree?
It is sent directly to Linus.
Cheers,
Miguel
On Fri, 14 Dec 2018 09:18:20 +0300
Dan Carpenter wrote:
> On Thu, Dec 13, 2018 at 03:06:29PM -0700, Jeremy Fertic wrote:
> > On Wed, Dec 12, 2018 at 11:19:49AM +0300, Dan Carpenter wrote:
> > > On Tue, Dec 11, 2018 at 05:54:54PM -0700, Jeremy Fertic wrote:
> > > > ADT7316_DA_EN_VIA_DAC_LDCA
On Tue, 11 Dec 2018 17:54:53 -0700
Jeremy Fertic wrote:
> Change two register addresses and one bit definition to match the
> datasheet.
>
> Signed-off-by: Jeremy Fertic
One comment inline. I added a fixes tag but also a note saying I would
not suggest backporting to stable.
There are too
On Sun, Dec 16, 2018 at 12:02:49PM +0100, Rafał Miłecki wrote:
> OK, if you say so, I'll try not to panic seeing those errors repeating
> over and over.
Yes, patience is the key :-)
> I know such issues may take months or years to get fixed, so I was
> trying to do some hacking on my own. I'll
On Tue, 11 Dec 2018 13:12:07 -0600
Dan Murphy wrote:
> Migrate the driver to use the devm IIO calls as opposed to
> the unmanaged calls.
>
> Signed-off-by: Dan Murphy
The remove order should always be the opposite of probe.
As devm cleanup is done 'after' whatever is in the remove function
you
On Tue, 11 Dec 2018 13:12:06 -0600
Dan Murphy wrote:
> Per Jonathan Cameron, the buffer needs to allocate room for a
> 64 bit timestamp as well as the channels. Change the buffer
> to allocate this additional space.
>
> Signed-off-by: Dan Murphy
Same question around data types as in the
On Sun, 16 Dec 2018 at 11:44, Borislav Petkov wrote:
> On Sun, Dec 16, 2018 at 11:26:29AM +0100, Rafał Miłecki wrote:
> > Debugging CPU errors.
>
> I told you that this issue is being worked on and there will be a fix
> of sorts at some point. Don't try any funky business of downgrading the
>
On Tue, 11 Dec 2018 13:12:05 -0600
Dan Murphy wrote:
> Introduce the TI ADS124S08 and the ADS124S06 ADC
> devices from TI. The ADS124S08 is the 12 channel ADC
> and the ADS124S06 is the 6 channel ADC device
>
> These devices share a common datasheet:
> http://www.ti.com/lit/gpn/ads124s08
>
>
On Tue, 11 Dec 2018 13:12:04 -0600
Dan Murphy wrote:
> Adding binding documentation for Texas Instruments ADS124S08
> and ADS124S06 ADC.
>
> S08 is a 12 channel ADC
> S06 is a 6 channel ADC
>
> Datesheet can be found here:
> http://www.ti.com/lit/gpn/ads124s08
>
> Signed-off-by: Dan Murphy
>
On Tue, 11 Dec 2018 05:13:20 +
Anson Huang wrote:
> The accelerometer's power supply could be controlled by regulator
> on some platforms, such as i.MX6Q-SABRESD board, the mma8451's
> power supply is controlled by a GPIO fixed regulator, need to make
> sure the regulator is enabled before
On Tue, 11 Dec 2018 05:13:14 +
Anson Huang wrote:
> The accelerometer's power supply could be controlled by regulator
> on some platforms, add optional property "vdd/vddio" power supply
> to let device tree to pass phandles to the regulators to driver.
>
> Signed-off-by: Anson Huang
On Sun, Dec 16, 2018 at 11:26:29AM +0100, Rafał Miłecki wrote:
> Debugging CPU errors.
I told you that this issue is being worked on and there will be a fix
of sorts at some point. Don't try any funky business of downgrading the
microcode and maybe break your boxes in the process. Just ignore the
On 14/12/2018 12:10, David Hildenbrand wrote:
> This will be done by free_reserved_page().
>
> Cc: Catalin Marinas
> Cc: Will Deacon
> Cc: Bhupesh Sharma
> Cc: James Morse
> Cc: Marc Zyngier
> Cc: Dave Kleikamp
> Cc: Mark Rutland
> Cc: Andrew Morton
> Cc: Michal Hocko
> Cc: Matthew
On 07/11/2018 08:10, Ryder Lee wrote:
> This updates dt-binding documentation for MT7629 SoC
>
> Signed-off-by: Ryder Lee
Acked-by: Matthias Brugger
> ---
> Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git
On Sun, 16 Dec 2018 at 11:06, Borislav Petkov wrote:
> > For my hack tests I'd like to replace my 0x0810100b with a 0x08101007.
>
> Why would you even want to downgrade the microcode?!
Debugging CPU errors. I have two notebooks:
1) HP EliteBook 745 G5 with Ryzen 5 PRO 2500U
It runs 1.03.01 BIOS
List LORAWAN and MACLORAWAN in menuconfig and make they can be built.
Signed-off-by: Jian-Hong Pan
---
V2:
- Split the LoRaWAN class module patch in V1 into LoRaWAN socket and
LoRaWAN Soft MAC modules
net/Kconfig | 2 ++
net/Makefile | 2 ++
2 files changed, 4 insertions(+)
diff --git
Add the maclorawan header file for common APIs in the module.
Signed-off-by: Jian-Hong Pan
---
V2:
- Split the LoRaWAN class module patch in V1 into LoRaWAN socket and
LoRaWAN Soft MAC modules
- Use SPDX license identifiers
V4:
- Fix typo in comments
- Fix by coding style report from
LoRaWAN defined by LoRa Alliance(TM) is the MAC layer over LoRa devices.
This patch implements part of Class A end-devices SoftMAC defined in
LoRaWAN(TM) Specification Ver. 1.0.2:
1. End-device receive slot timing
2. Only single channel and single data rate for now
3. Unconfirmed data up/down
Implement the crypto for encryption/decryption and message integrity
code (MIC) according to LoRaWAN(TM) Specification Ver. 1.0.2.
Signed-off-by: Jian-Hong Pan
---
V2:
- Split the LoRaWAN class module patch in V1 into LoRaWAN socket and
LoRaWAN Soft MAC modules
- Rename the lrwsec files to
On Tue, 11 Dec 2018 05:06:20 +
Anson Huang wrote:
> The magnetometer's power supply could be controlled by regulator
> on some platforms, such as i.MX6Q-SABRESD board, the mag3110's
> power supply is controlled by a GPIO fixed regulator, need to make
> sure the regulator is enabled before
LoRaWAN(TM) is the MAC layer defined by LoRa Alliance(TM) over LoRa
devices. LoRa is one of Low-Power Wide-Area Network (LPWAN) technology.
LoRaWAN networks typically are laid out in a star-of-stars topology in
which gateways relay messages between end-devices and a central network
server at the
Add public LoRaWAN API for compatible LoRa device drivers.
Signed-off-by: Jian-Hong Pan
---
V2:
- Split the LoRaWAN class module patch in V1 into LoRaWAN socket and
LoRaWAN Soft MAC modules
- Merge the lrw_operations: set_bw, set_mod, set_sf into set_dr
- Use SPDX license identifiers
V3:
-
This patch adds a new address/protocol family for LoRaWAN network.
It also implements the the functions and maps to Datagram socket for
LoRaWAN unconfirmed data messages.
Signed-off-by: Jian-Hong Pan
---
V2:
- Split the LoRaWAN class module patch in V1 into LoRaWAN socket and
LoRaWAN Soft MAC
On Sun, Dec 16, 2018 at 05:26:49PM +1100, Stephen Rothwell wrote:
> Hi Jens,
>
> Commit
>
> 6f7ceaa0559b ("block: remove the bioset_integrity_free export")
>
> is missing a Signed-off-by from its author.
Ooops. Jens, in case you still feel ok ammending the tree:
Signed-off-by: Christoph
Rob, Clk experts, questions for you below.
Jonathan
On Thu, 13 Dec 2018 17:39:22 -0800
Stephen Boyd wrote:
> Quoting Jonathan Cameron (2018-12-08 07:29:54)
> > On Thu, 6 Dec 2018 11:10:51 +0200
> > Mircea Caprioru wrote:
> >
> > > This patch adds a clock to the state structure of ad7192
On Sun, Dec 16, 2018 at 09:08:00AM +0100, Rafał Miłecki wrote:
> Thanks! I had no idea microcode_amd_fam17h.bin is a container with few
> microcodes. I thought there is a single microcode for a whole family
> (e.g. 17h).
It is a container for all F17h - you're simply making the wrong
assumption
On Sun, Dec 16, 2018 at 02:33:39AM +, Nadav Amit wrote:
> In general, I think that from the start it was clear that the motivation for
> the patch-set is not just performance and also better code. For example, I
> see no reason to revert the PV-changes or the lock-prefix changes that
>
On 2018-12-14 12:59, Greg Kroah-Hartman wrote:
4.4-stable review patch. If anyone has any objections, please let me
know.
--
From: Jiri Wiesner
[ Upstream commit ebaf39e6032faf77218220707fc3fa22487784e0 ]
Commit v4.10-rc4-868-g158f323b9868, which the patch under review
On 2018-12-14 13:00, Greg Kroah-Hartman wrote:
4.9-stable review patch. If anyone has any objections, please let me
know.
--
From: Jiri Wiesner
[ Upstream commit ebaf39e6032faf77218220707fc3fa22487784e0 ]
Commit v4.10-rc4-868-g158f323b9868, which the patch under review
Dear,i am lisa jaster,it would be great to know you,i have a very
important and confidential matter that i want to discuss with
you,reply me back for more discus.
Regards,
Lisa Jaster.
The CPU frequency is managed at the AP level for the Armada 7K/8K. The
CPU frequency is modified by cluster: the CPUs of the same cluster have
the same frequency.
This patch adds the clock driver that will be used by CPUFreq, it is
based on the work of Omri Itach .
Signed-off-by: Gregory CLEMENT
Document the device tree binding for the cluster clock controllers found
in the Armada 7K/8K SoCs.
Signed-off-by: Gregory CLEMENT
---
.../arm/marvell/ap806-system-controller.txt | 22 +++
1 file changed, 22 insertions(+)
diff --git
Clock drivers for Armada AP and Armada CP use the same function to
generate unique clock name. A third drivers is coming with the same
need, so it's time to move this function in a common file.
Signed-off-by: Gregory CLEMENT
---
drivers/clk/mvebu/Kconfig | 5
This commit makes sure the driver for the Armada 7K/8K CPU clock is
enabled.
Signed-off-by: Gregory CLEMENT
---
arch/arm64/Kconfig.platforms | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 51bc479334a4..8a05870b1ba8 100644
Hello,
This is the third version of a series allowing to manage the cpu
clock for Armada 7K/8K. For these SoCs, the CPUs share the same clock
by cluster, so actually the clock management is done at cluster level.
As for the other Armada 7K/8K clocks it is possible to have multiple
AP so here
Actually, the clocks exposed for the cluster are not the CPU clocks, but
the PLL clock used as entry clock for the CPU clocks. The CPU clock will
be managed by a driver submitting in the following patches.
Signed-off-by: Gregory CLEMENT
---
drivers/clk/mvebu/ap806-system-controller.c | 4 ++--
Add cpu clock node on AP
Signed-off-by: Gregory CLEMENT
---
arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi | 4
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 6 ++
2 files changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
Hi,
On 2018/12/15 22:38, Matthew Wilcox wrote:
> On Tue, Dec 04, 2018 at 10:08:40AM +0800, Hou Tao wrote:
>> There is no need to disable __GFP_FS in ->readpage:
>> * It's a read-only fs, so there will be no dirty/writeback page and
>> there will be no deadlock against the caller's locked page
Hi Stephen,
On ven., déc. 14 2018, Stephen Boyd wrote:
> Quoting Gregory CLEMENT (2018-12-06 09:15:11)
>> Hello,
>>
>> This is the second version of a series allowing to manage the cpu
>> clock for Armada 7K/8K. For these SoCs, the CPUs share the same clock
>> by cluster, so actually the
On Sun, Dec 09, 2018 at 02:26:08PM +, Abel Vesa wrote:
...
> diff --git a/arch/arm64/boot/dts/freescale/Makefile
> b/arch/arm64/boot/dts/freescale/Makefile
> index 7748e6d..0001361 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -18,3
On Sun, Dec 09, 2018 at 02:26:06PM +, Abel Vesa wrote:
> From: Lucas Stach
>
> Add basic Kconfig symbols to make the MXC architecture available
> in the ARM64 world.
>
> Signed-off-by: Lucas Stach
> Reviewed-by: Fabio Estevam
> ---
> arch/arm64/Kconfig.platforms | 14 ++
> 1
On Thu, Dec 6, 2018 at 4:54 AM Rob Herring wrote:
>
> Convert string compares of DT node names to use of_node_name_eq helper
> instead. This removes direct access to the node name pointer.
>
> For instances using of_node_cmp, this has the side effect of now using
> case sensitive comparisons.
On Sat, Dec 15, 2018 at 09:46:54AM -0800, Guenter Roeck wrote:
> Hi,
>
> On Fri, Dec 07, 2018 at 11:07:20AM -0800, Christoph Hellwig wrote:
> > Avoid expensive indirect calls in the fast path DMA mapping
> > operations by directly calling the dma_direct_* ops if we are using
> > the directly
Greetings!!
Apologies should my message be a disturbance to you.My Name is Peter Owen a
fund/Investment Manager with a high profile investment company.A huge Sum of
funds has been diverted, representing 1.2% of Excess Magellan Capital Funds
from the Investor Capital Project Funds.
I am
On 16.12.2018 01:05, Borislav Petkov wrote:
On Sun, Dec 16, 2018 at 12:46:05AM +0100, Rafał Miłecki wrote:
[19.736770] microcode: [find_equiv_id] sig:8458000
That's your CPU's family/model/stepping: 0x0810f10
[19.736772] microcode: [find_equiv_id] equiv_table->installed_cpu:8392466
On 12/15/18 5:53 PM, Joe Perches wrote:
On Sat, 2018-12-15 at 17:46 +0100, Michael Straube wrote:
Replace tabs with spaces and/or remove spaces in declarations.
Remove unused/commented declarations, remove unnecessary comment,
remove blank lines between declarations and add missing lines after
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